From be25ae7476039f003ed1b75dfc8c27b622209239 Mon Sep 17 00:00:00 2001 From: "R. Timothy Edwards" Date: Fri, 7 Oct 2022 04:23:07 -0400 Subject: [PATCH] Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com> --- manifest | 6 +++--- verilog/rtl/caravan.v | 6 ++++++ verilog/rtl/caravel.v | 6 ++++++ verilog/rtl/housekeeping.v | 18 ++++++++++++++---- 4 files changed, 29 insertions(+), 7 deletions(-) diff --git a/manifest b/manifest index fe63437f..9cdd7f90 100644 --- a/manifest +++ b/manifest @@ -2,10 +2,10 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -d5d60c099db9d9439a5f7a752e2ec3fc136ad196 verilog/rtl/caravan.v +24ed502194cb86e86abf9d94aa0d0918bf8556c9 verilog/rtl/caravan.v 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -da9ede04122837cb2bfabc5b91c80fb9696ad08a verilog/rtl/caravel.v +c6851e521ea59a923437c3b3efca8ceb225f1d54 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v @@ -17,7 +17,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 1f894f1c43d42017c157d8dd7d2e4674c1a43303 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v -ba579e382efe39852282cec649ca7912f661d0d9 verilog/rtl/housekeeping.v +d77a4f3c753ce8057a59f5e8462487f69a32b8b7 verilog/rtl/housekeeping.v 3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index a4c3041d..935aeac6 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -406,11 +406,13 @@ module caravan ( wire mprj_vdd_pwrgood; wire mprj2_vdd_pwrgood; +`ifdef USE_SRAM_RO_INTERFACE // SRAM read-noly access from housekeeping wire hkspi_sram_clk; wire hkspi_sram_csb; wire [7:0] hkspi_sram_addr; wire [31:0] hkspi_sram_data; +`endif // Management processor (wrapper). Any management core // implementation must match this pinout. @@ -495,11 +497,13 @@ module caravan ( .la_oenb(la_oenb_mprj), .la_iena(la_iena_mprj), +`ifdef USE_SRAM_RO_INTERFACE // SRAM Read-only access from housekeeping .sram_ro_clk(hkspi_sram_clk), .sram_ro_csb(hkspi_sram_csb), .sram_ro_addr(hkspi_sram_addr), .sram_ro_data(hkspi_sram_data), +`endif // Trap status .trap(trap) @@ -801,10 +805,12 @@ module caravan ( .pad_flash_io0_di(flash_io0_di), .pad_flash_io1_di(flash_io1_di), +`ifdef USE_SRAM_RO_INTERFACE .sram_ro_clk(hkspi_sram_clk), .sram_ro_csb(hkspi_sram_csb), .sram_ro_addr(hkspi_sram_addr), .sram_ro_data(hkspi_sram_data), +`endif .usr1_vcc_pwrgood(mprj_vcc_pwrgood), .usr2_vcc_pwrgood(mprj2_vcc_pwrgood), diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 5abfa42c..1aca6bdc 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -360,11 +360,13 @@ module caravel ( wire mprj_vdd_pwrgood; wire mprj2_vdd_pwrgood; +`ifdef USE_SRAM_RO_INTERFACE // SRAM read-only access from houskeeping wire hkspi_sram_clk; wire hkspi_sram_csb; wire [7:0] hkspi_sram_addr; wire [31:0] hkspi_sram_data; +`endif // Management processor (wrapper). Any management core // implementation must match this pinout. @@ -449,11 +451,13 @@ module caravel ( .la_oenb(la_oenb_mprj), .la_iena(la_iena_mprj), +`ifdef USE_SRAM_RO_INTERFACE // SRAM Read-only access from housekeeping .sram_ro_clk(hkspi_sram_clk), .sram_ro_csb(hkspi_sram_csb), .sram_ro_addr(hkspi_sram_addr), .sram_ro_data(hkspi_sram_data), +`endif // Trap status .trap(trap) @@ -743,10 +747,12 @@ module caravel ( .pad_flash_io0_di(flash_io0_di), .pad_flash_io1_di(flash_io1_di), +`ifdef USE_SRAM_RO_INTERFACE .sram_ro_clk(hkspi_sram_clk), .sram_ro_csb(hkspi_sram_csb), .sram_ro_addr(hkspi_sram_addr), .sram_ro_data(hkspi_sram_data), +`endif .usr1_vcc_pwrgood(mprj_vcc_pwrgood), .usr2_vcc_pwrgood(mprj2_vcc_pwrgood), diff --git a/verilog/rtl/housekeeping.v b/verilog/rtl/housekeeping.v index 6c36b7b3..a08b7788 100644 --- a/verilog/rtl/housekeeping.v +++ b/verilog/rtl/housekeeping.v @@ -170,10 +170,12 @@ module housekeeping #( input pad_flash_io0_di, input pad_flash_io1_di, +`ifdef USE_SRAM_RO_INTERFACE output sram_ro_clk, output sram_ro_csb, output [7:0] sram_ro_addr, input [31:0] sram_ro_data, +`endif // System signal monitoring input usr1_vcc_pwrgood, @@ -203,9 +205,11 @@ module housekeeping #( reg serial_xfer; reg hkspi_disable; +`ifdef USE_SRAM_RO_INTERFACE reg sram_ro_clk; reg sram_ro_csb; reg [7:0] sram_ro_addr; +`endif reg clk1_output_dest; reg clk2_output_dest; @@ -250,7 +254,9 @@ module housekeeping #( wire cwstb; // Combination of SPI write strobe and back door write strobe wire csclk; // Combination of SPI SCK and back door access trigger +`ifdef USE_SRAM_RO_INTERFACE wire [31:0] sram_ro_data; +`endif // Housekeeping side 3-wire interface to GPIOs (see below) wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out; @@ -364,13 +370,15 @@ module housekeeping #( serial_bb_load, serial_bb_resetn, serial_bb_enable, serial_busy}; - /* To be added: SRAM read-only port (registers 14 to 19) */ +`ifdef USE_SRAM_RO_INTERFACE + /* Optional: SRAM read-only port (registers 14 to 19) */ 8'h14 : fdata = {6'b000000, sram_ro_clk, sram_ro_csb}; 8'h15 : fdata = sram_ro_addr; 8'h16 : fdata = sram_ro_data[31:24]; 8'h17 : fdata = sram_ro_data[23:16]; 8'h18 : fdata = sram_ro_data[15:8]; 8'h19 : fdata = sram_ro_data[7:0]; +`endif /* System monitoring */ 8'h1a : fdata = {4'b0000, usr1_vcc_pwrgood, usr2_vcc_pwrgood, @@ -517,8 +525,6 @@ module housekeeping #( gpio_adr | 12'h000 : spiaddr = 8'h13; // GPIO control - /* To be added: SRAM read-only interface */ - sys_adr | 12'h000 : spiaddr = 8'h1a; // Power monitor sys_adr | 12'h004 : spiaddr = 8'h1b; // Output redirect sys_adr | 12'h00c : spiaddr = 8'h1c; // Input redirect @@ -1042,9 +1048,11 @@ module housekeeping #( hkspi_disable <= 1'b0; pwr_ctrl_out <= 'd0; +`ifdef USE_SRAM_RO_INTERFACE sram_ro_clk <= 1'b0; sram_ro_csb <= 1'b1; sram_ro_addr <= 8'h00; +`endif end else begin if (cwstb == 1'b1) begin @@ -1096,7 +1104,8 @@ module housekeeping #( serial_xfer <= cdata[0]; end - /* To be done: Add SRAM read-only interface */ +`ifdef USE_SRAM_RO_INTERFACE + /* Optional: Add SRAM read-only interface */ 8'h14: begin sram_ro_clk <= cdata[1]; sram_ro_csb <= cdata[0]; @@ -1104,6 +1113,7 @@ module housekeeping #( 8'h15: begin sram_ro_addr <= cdata; end +`endif /* Registers 16 to 19 (SRAM data) are read-only */