[DATA] Update caravel_clocking

lef/caravel_clocking.lef

@@ -212,35 +212,40 @@ MACRO caravel_clocking
         RECT 1.525 -0.085 1.695 0.085 ;
         RECT 5.215 -0.050 5.375 0.060 ;
         RECT 6.585 -0.085 6.755 0.085 ;
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+        RECT 52.120 -0.055 52.240 0.055 ;
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+        RECT 87.085 -0.085 87.255 0.085 ;
         RECT 90.305 -0.085 90.475 0.085 ;
+        RECT 92.605 -0.085 92.775 0.085 ;
         RECT 93.985 -0.085 94.155 0.085 ;
       LAYER li1 ;
         RECT 0.000 0.085 94.300 54.485 ;
@@ -264,22 +269,22 @@ MACRO caravel_clocking
         RECT 69.800 -0.240 71.340 0.000 ;
         RECT 85.300 -0.240 86.840 0.000 ;
       LAYER met3 ;
-        RECT 12.485 55.400 95.600 56.265 ;
-        RECT 12.485 49.320 96.000 55.400 ;
-        RECT 12.485 47.920 95.600 49.320 ;
-        RECT 12.485 41.840 96.000 47.920 ;
-        RECT 12.485 40.440 95.600 41.840 ;
-        RECT 12.485 34.360 96.000 40.440 ;
-        RECT 12.485 32.960 95.600 34.360 ;
-        RECT 12.485 26.880 96.000 32.960 ;
-        RECT 12.485 25.480 95.600 26.880 ;
-        RECT 12.485 19.400 96.000 25.480 ;
-        RECT 12.485 18.000 95.600 19.400 ;
-        RECT 12.485 11.920 96.000 18.000 ;
-        RECT 12.485 10.520 95.600 11.920 ;
-        RECT 12.485 4.440 96.000 10.520 ;
-        RECT 12.485 3.040 95.600 4.440 ;
-        RECT 12.485 0.000 96.000 3.040 ;
+        RECT 15.520 55.400 95.600 56.265 ;
+        RECT 15.520 49.320 96.000 55.400 ;
+        RECT 15.520 47.920 95.600 49.320 ;
+        RECT 15.520 41.840 96.000 47.920 ;
+        RECT 15.520 40.440 95.600 41.840 ;
+        RECT 15.520 34.360 96.000 40.440 ;
+        RECT 15.520 32.960 95.600 34.360 ;
+        RECT 15.520 26.880 96.000 32.960 ;
+        RECT 15.520 25.480 95.600 26.880 ;
+        RECT 15.520 19.400 96.000 25.480 ;
+        RECT 15.520 18.000 95.600 19.400 ;
+        RECT 15.520 11.920 96.000 18.000 ;
+        RECT 15.520 10.520 95.600 11.920 ;
+        RECT 15.520 4.440 96.000 10.520 ;
+        RECT 15.520 3.040 95.600 4.440 ;
+        RECT 15.520 0.000 96.000 3.040 ;
         RECT 23.270 -0.165 24.870 0.000 ;
         RECT 38.770 -0.165 40.370 0.000 ;
         RECT 54.270 -0.165 55.870 0.000 ;

maglef/caravel_clocking.mag

@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1638662846
+timestamp 1638876628
 << nwell >>
 rect -38 10053 18898 10619
 rect -38 8965 18898 9531
@@ -18,35 +18,40 @@ rect 29 -17 63 17
 rect 305 -17 339 17
 rect 1043 -10 1075 12
 rect 1317 -17 1351 17
-rect 2513 -17 2547 17
+rect 1593 -17 1627 17
+rect 2328 -11 2352 11
+rect 2605 -17 2639 17
+rect 2697 -17 2731 17
+rect 2973 -17 3007 17
 rect 3709 -17 3743 17
-rect 4905 -17 4939 17
-rect 5272 -11 5296 11
-rect 5917 -17 5951 17
-rect 6100 -17 6134 17
-rect 6377 -17 6411 17
-rect 7112 -11 7136 11
+rect 5549 -17 5583 17
+rect 5641 -17 5675 17
+rect 6101 -17 6135 17
+rect 6432 -17 6466 17
 rect 7297 -17 7331 17
-rect 8493 -17 8527 17
-rect 9044 -11 9068 11
-rect 9412 -17 9446 17
-rect 9504 -11 9528 11
+rect 7573 -17 7607 17
+rect 7665 -17 7699 17
+rect 8548 -17 8582 17
+rect 9321 -17 9355 17
 rect 9689 -17 9723 17
-rect 10885 -17 10919 17
-rect 12356 -17 12390 17
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-rect 16497 -17 16531 17
-rect 16591 -10 16623 12
-rect 16865 -17 16899 17
-rect 17509 -17 17543 17
-rect 17876 -11 17900 11
+rect 10424 -11 10448 11
+rect 10702 -17 10736 17
+rect 11160 -17 11194 17
+rect 11253 -17 11287 17
+rect 12080 -11 12104 11
+rect 12173 -17 12207 17
+rect 13000 -17 13034 17
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+rect 15209 -17 15243 17
+rect 15669 -17 15703 17
+rect 17050 -17 17084 17
+rect 17325 -17 17359 17
+rect 17417 -17 17451 17
 rect 18061 -17 18095 17
+rect 18521 -17 18555 17
 rect 18797 -17 18831 17
 << obsli1 >>
 rect 0 -17 18860 10897
@@ -85,22 +90,22 @@ rect 19200 3680 20000 3800
 rect 19200 2184 20000 2304
 rect 19200 688 20000 808
 << obsm3 >>
-rect 2497 11080 19120 11253
-rect 2497 9864 19200 11080
-rect 2497 9584 19120 9864
-rect 2497 8368 19200 9584
-rect 2497 8088 19120 8368
-rect 2497 6872 19200 8088
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-rect 2497 2384 19200 3600
-rect 2497 2104 19120 2384
-rect 2497 888 19200 2104
-rect 2497 608 19120 888
-rect 2497 0 19200 608
+rect 3104 11080 19120 11253
+rect 3104 9864 19200 11080
+rect 3104 9584 19120 9864
+rect 3104 8368 19200 9584
+rect 3104 8088 19120 8368
+rect 3104 6872 19200 8088
+rect 3104 6592 19120 6872
+rect 3104 5376 19200 6592
+rect 3104 5096 19120 5376
+rect 3104 3880 19200 5096
+rect 3104 3600 19120 3880
+rect 3104 2384 19200 3600
+rect 3104 2104 19120 2384
+rect 3104 888 19200 2104
+rect 3104 608 19120 888
+rect 3104 0 19200 608
 rect 4654 -33 4974 0
 rect 7754 -33 8074 0
 rect 10854 -33 11174 0
@@ -189,7 +194,7 @@ string LEFclass BLOCK
 string FIXED_BBOX 0 0 20000 12000
 string LEFview TRUE
 string GDS_FILE ../gds/caravel_clocking.gds
-string GDS_END 1197054
-string GDS_START 422960
+string GDS_END 1175822
+string GDS_START 367538
 << end >>
 

openlane/caravel_clocking/base.sdc

@@ -5,20 +5,20 @@ create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90"  -period 6.66666666666
 
 ## GENERATED CLOCKS
 # divided PLL clocks
-create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _351_/Y] 
-create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _354_/Y] 
+create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _355_/Y] 
+create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _357_/Y] 
 
 #  assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
-create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _343_/X] 
-create_generated_clock -name core_ext_clk_syncd -source [get_pins _420_/Q] -divide_by 1 [get_pins _343_/X] 
+create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _347_/X] 
+create_generated_clock -name core_ext_clk_syncd -source [get_pins _444_/Q] -divide_by 1 [get_pins _347_/X] 
 
 # assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
-create_generated_clock -name core_clk -source [get_pins _343_/X]  -divide_by 1 [get_ports core_clk] 
-create_generated_clock -name core_clk_pll -source [get_pins _351_/Y]   -divide_by 1 [get_ports core_clk] 
+create_generated_clock -name core_clk -source [get_pins _347_/X]  -divide_by 1 [get_ports core_clk] 
+create_generated_clock -name core_clk_pll -source [get_pins _355_/Y]   -divide_by 1 [get_ports core_clk] 
 
 # assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
-create_generated_clock -name user_clk -source [get_pins _343_/X]  -divide_by 1 [get_ports user_clk] 
-create_generated_clock -name user_clk_pll -source [get_pins _354_/Y]   -divide_by 1 [get_ports user_clk]  
+create_generated_clock -name user_clk -source [get_pins _347_/X]  -divide_by 1 [get_ports user_clk] 
+create_generated_clock -name user_clk_pll -source [get_pins _357_/Y]   -divide_by 1 [get_ports user_clk]  
 
 # logically exclusive clocks, the generated pll clocks and the ext core clk
 set_clock_groups -logically_exclusive -group core_ext_clk -group core_ext_clk_syncd

openlane/caravel_clocking/config.tcl

@@ -56,7 +56,7 @@ set ::env(FP_PDN_HPITCH) 16.9
 set ::env(FP_PDN_VPITCH) 15.5
 
 ## Placement
-set ::env(PL_TARGET_DENSITY) 0.715
+set ::env(PL_TARGET_DENSITY) 0.74
 
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1

sdc/caravel_clocking.sdc

@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sun Dec  5 00:06:34 2021
+# Tue Dec  7 11:29:52 2021
 ###############################################################################
 current_design caravel_clocking
 ###############################################################################
@@ -18,15 +18,15 @@ create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
 set_clock_transition 0.1500 [get_clocks {pll_clk90}]
 set_clock_uncertainty 0.2500 pll_clk90
 set_propagated_clock [get_clocks {pll_clk90}]
-create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_351_/Y}]
+create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_355_/Y}]
 set_propagated_clock [get_clocks {pll_clk_divided}]
-create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_354_/Y}]
+create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_357_/Y}]
 set_propagated_clock [get_clocks {pll_clk90_divided}]
-create_generated_clock -name core_ext_clk_syncd -source [get_pins {_420_/Q}] -divide_by 1 [get_pins {_343_/X}]
+create_generated_clock -name core_ext_clk_syncd -source [get_pins {_444_/Q}] -divide_by 1 [get_pins {_347_/X}]
 set_propagated_clock [get_clocks {core_ext_clk_syncd}]
-create_generated_clock -name core_clk_pll -source [get_pins {_351_/Y}] -divide_by 1 [get_ports {core_clk}]
+create_generated_clock -name core_clk_pll -source [get_pins {_355_/Y}] -divide_by 1 [get_ports {core_clk}]
 set_propagated_clock [get_clocks {core_clk_pll}]
-create_generated_clock -name user_clk_pll -source [get_pins {_354_/Y}] -divide_by 1 [get_ports {user_clk}]
+create_generated_clock -name user_clk_pll -source [get_pins {_357_/Y}] -divide_by 1 [get_ports {user_clk}]
 set_propagated_clock [get_clocks {user_clk_pll}]
 set_clock_groups -name group1 -logically_exclusive \
  -group [get_clocks {core_ext_clk_syncd}]

signoff/caravel_clocking/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 2021.11.23_01.42.34-10-g445acc6
+openlane 2021.11.23_01.42.34-11-g0c24fcf

signoff/caravel_clocking/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
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