Modified all of the Makefiles to better handle the GL netlist simulations,

which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).

verilog/dv/caravel/mgmt_soc/caravan/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = caravan
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/gpio/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = gpio
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v

@@ -28,10 +28,6 @@
 `include "caravel_netlists.v"
 `include "spiflash.v"
 
-// NOTE:  Temporary location of management SoC wrapper is a symbolic link
-// to the caravel_pico repository verilog/rtl/mgmt_core_wrapper.v
-`include "mgmt_core_wrapper.v"
-
 module gpio_tb;
 
 	reg clock;

verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = gpio_mgmt
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/hkspi/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = hkspi
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/hkspi_power/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = hkspi_power
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/irq/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = irq
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/mem/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = mem
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/mprj_bitbang/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = mprj_bitbang
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = mprj_ctrl
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/pass_thru/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = pass_thru
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/perf/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = perf
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/pll/Makefile

@@ -20,9 +20,6 @@ RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=$(PDK_ROOT)/sky130A
@@ -35,14 +32,28 @@ SIM?=RTL
 
 PATTERN = pll
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
 	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
+else
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp check-env
 	vvp $<

verilog/dv/caravel/mgmt_soc/qspi/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = qspi
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/spi_master/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = spi_master
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/sram_exec/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = sram_exec
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/storage/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = storage
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/sysctrl/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = sysctrl
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/timer/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -30,6 +27,14 @@ SIM_DEFINES = -DFUNCTIONAL -DSIM
 
 SIM?=RTL
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 .SUFFIXES:
 
 PATTERN = timer
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/timer2/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -30,6 +27,14 @@ SIM_DEFINES = -DFUNCTIONAL -DSIM
 
 SIM?=RTL
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 .SUFFIXES:
 
 PATTERN = timer2
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/uart/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = uart
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile

@@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
 RTL_PATH = $(VERILOG_PATH)/rtl
 BEHAVIOURAL_MODELS = ../../ 
 
-# Temporary:  Path to management SoC wrapper repository
-MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
-
 FIRMWARE_PATH = ../..
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -34,6 +31,14 @@ SIM?=RTL
 
 PATTERN = user_pass_thru
 
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+	MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
 all:  ${PATTERN:=.vcd}
 
 hex:  ${PATTERN:=.hex}
@@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
 	$< -o $@ 
 else  
 	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
 	$< -o $@ 
 endif
 

verilog/gl/__user_analog_project_wrapper.v

@@ -0,0 +1,124 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    /* GPIOs.  There are 27 GPIOs, on either side of the analog.
+     * These have the following mapping to the GPIO padframe pins
+     * and memory-mapped registers, since the numbering remains the
+     * same as caravel but skips over the analog I/O:
+     *
+     * io_in/out/oeb/in_3v3 [26:14]  <--->  mprj_io[37:25]
+     * io_in/out/oeb/in_3v3 [13:0]   <--->  mprj_io[13:0]	
+     *
+     * When the GPIOs are configured by the Management SoC for
+     * user use, they have three basic bidirectional controls:
+     * in, out, and oeb (output enable, sense inverted).  For
+     * analog projects, a 3.3V copy of the signal input is
+     * available.  out and oeb must be 1.8V signals.
+     */
+
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+    /* Analog (direct connection to GPIO pad---not for high voltage or
+     * high frequency use).  The management SoC must turn off both
+     * input and output buffers on these GPIOs to allow analog access.
+     * These signals may drive a voltage up to the value of VDDIO
+     * (3.3V typical, 5.5V maximum).
+     * 
+     * Note that analog I/O is not available on the 7 lowest-numbered
+     * GPIO pads, and so the analog_io indexing is offset from the
+     * GPIO indexing by 7, as follows:
+     *
+     * gpio_analog/noesd [17:7]  <--->  mprj_io[35:25]
+     * gpio_analog/noesd [6:0]   <--->  mprj_io[13:7]	
+     *
+     */
+    
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+    /* Analog signals, direct through to pad.  These have no ESD at all,
+     * so ESD protection is the responsibility of the designer.
+     *
+     * user_analog[10:0]  <--->  mprj_io[24:14]
+     *
+     */
+    inout [`ANALOG_PADS-1:0] io_analog,
+
+    /* Additional power supply ESD clamps, one per analog pad.  The
+     * high side should be connected to a 3.3-5.5V power supply.
+     * The low side should be connected to ground.
+     *
+     * clamp_high[2:0]   <--->  mprj_io[20:18]
+     * clamp_low[2:0]    <--->  mprj_io[20:18]
+     *
+     */
+    inout [2:0] io_clamp_high,
+    inout [2:0] io_clamp_low,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+// Dummy assignment so that we can take it through the openlane flow
+assign io_out = io_in;
+
+endmodule	// user_analog_project_wrapper

verilog/gl/__user_project_wrapper.v

@@ -0,0 +1,91 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper.  The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+    parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+
+// Dummy assignments so that we can take it through the openlane flow
+`ifdef SIM
+// Needed for running GL simulation
+assign io_out = 0;
+assign io_oeb = 0;
+`else
+assign io_out = io_in;
+`endif
+
+endmodule	// user_project_wrapper

verilog/gl/caravan.v

@@ -4041,7 +4041,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
     .porb_l(porb_l),
     .vdd1v8(vccd_core),
     .vdd3v3(vddio_core),
-    .vss3v3(vssio_core)
+    .vss3v3(vssio_core),
     .vss1v8(vssd_core)
   );
   xres_buf rstb_level (

verilog/rtl/caravan_netlists.v

@@ -49,18 +49,19 @@
 	// Assume default net type to be wire because GL netlists don't have the wire
 	// definitions
 	`default_nettype wire
-	`include "gl/mgmt_core.v"
 	`include "gl/digital_pll.v"
-	`include "gl/DFFRAM.v"
+	`include "gl/caravel_clocking.v"
-	`include "gl/storage.v"
 	`include "gl/user_id_programming.v"
 	`include "gl/chip_io_alt.v"
+	`include "gl/housekeeping.v"
 	`include "gl/mprj_logic_high.v"
 	`include "gl/mprj2_logic_high.v"
 	`include "gl/mgmt_protect.v"
 	`include "gl/mgmt_protect_hv.v"
 	`include "gl/gpio_control_block.v"
 	`include "gl/gpio_defaults_block.v"
+	`include "gl/gpio_defaults_block_0403.v"
+	`include "gl/gpio_defaults_block_1803.v"
 	`include "gl/gpio_logic_high.v"
 	`include "gl/xres_buf.v"
 	`include "gl/spare_logic_block.v"

verilog/rtl/caravel_netlists.v

@@ -47,18 +47,19 @@
     `endif 
 
     `ifdef GL
-	`include "gl/mgmt_core.v"
 	`include "gl/digital_pll.v"
-	`include "gl/DFFRAM.v"
+	`include "gl/caravel_clocking.v"
-	`include "gl/storage.v"
 	`include "gl/user_id_programming.v"
 	`include "gl/chip_io.v"
+	`include "gl/housekeeping.v"
 	`include "gl/mprj_logic_high.v"
 	`include "gl/mprj2_logic_high.v"
 	`include "gl/mgmt_protect.v"
 	`include "gl/mgmt_protect_hv.v"
 	`include "gl/gpio_control_block.v"
 	`include "gl/gpio_defaults_block.v"
+	`include "gl/gpio_defaults_block_0403.v"
+	`include "gl/gpio_defaults_block_1803.v"
 	`include "gl/gpio_logic_high.v"
 	`include "gl/xres_buf.v"
 	`include "gl/spare_logic_block.v"