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+ add a size 16 buf for clockp signal in digital_pll

This commit is contained in:
kareem 2022-10-13 05:57:09 -07:00
parent e3e513bcee
commit bb2d983e03
1 changed files with 27 additions and 2 deletions
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29
verilog/rtl/digital_pll.v
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@ -43,6 +43,7 @@ module digital_pll(
output [1:0] clockp; // Two 90 degree clock phases output [1:0] clockp; // Two 90 degree clock phases
wire [1:0] clockp_buffer_in; // Input wires to clockp buffers
wire [25:0] itrim; // Internally generated trim bits wire [25:0] itrim; // Internally generated trim bits
wire [25:0] otrim; // Trim bits applied to the ring oscillator wire [25:0] otrim; // Trim bits applied to the ring oscillator
wire creset; // Controller reset wire creset; // Controller reset
@ -58,16 +59,40 @@ module digital_pll(
ring_osc2x13 ringosc ( ring_osc2x13 ringosc (
.reset(ireset), .reset(ireset),
.trim(itrim), .trim(itrim),
.clockp(clockp) .clockp(clockp_buffer_in)
); );
digital_pll_controller pll_control ( digital_pll_controller pll_control (
.reset(creset), .reset(creset),
.clock(clockp[0]), .clock(clockp_buffer_in[0]),
.osc(osc), .osc(osc),
.div(div), .div(div),
.trim(otrim) .trim(otrim)
); );
(* keep *)
sky130_fd_sc_hd__buf_16 clockp_buffer_0 (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(clockp_buffer_in[0]),
.X(clockp[0])
);
(* keep *)
sky130_fd_sc_hd__buf_16 clockp_buffer_1 (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(clockp_buffer_in[1]),
.X(clockp[1])
);
endmodule endmodule
`default_nettype wire `default_nettype wire