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Apply automatic changes to Manifest and README.rst

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RTimothyEdwards 2022-09-20 21:56:37 +00:00 committed by My GitHub Actions Bot
parent c7d01796bd
commit b9a819634d
1 changed files with 8 additions and 7 deletions
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@ -2,18 +2,19 @@
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
670031aa4d92dbf15054b698f859b01d35143aa9 verilog/rtl/caravan.v a349dd3c5fae352a0a89131bf65018650944977f verilog/rtl/caravan.v
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
22c9fc7c6e9dccd4c8511d9d6ec63765dfaedf3a verilog/rtl/caravel.v bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
a0b12a4769db4cfa0cd340194af3429d3daedb51 verilog/rtl/chip_io.v cc983a39219a9211a3e360b77d3ba6e7e8f6bea8 verilog/rtl/chip_io.v
2b0bbaa63039534db811c82d808e885a1b9c20e3 verilog/rtl/chip_io_alt.v 8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
41f899d8a8510f933e08e41d1b4ac13d84191f38 verilog/rtl/gpio_control_block.v 6e1277baf7702168702ee5d4e373180c7d0b4631 verilog/rtl/gpio_control_block.v
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
5469b880904d6dd5d1eba6f026b3582810df412c verilog/rtl/housekeeping.v 5469b880904d6dd5d1eba6f026b3582810df412c verilog/rtl/housekeeping.v
@ -23,7 +24,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v 9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
770d418646d4f4f37a08b5de8308d33eafd7bde9 verilog/rtl/pads.v 4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v 6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v 1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v