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caravel
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REVERT ME: temporarily match simple_por pin in verilog with lef

This commit is contained in:
kareem 2022-04-01 10:52:36 -07:00
parent 5d8b579b6c
commit b70c27c69f
2 changed files with 9 additions and 11 deletions
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5
verilog/rtl/caravel.v
View File

@ -236,7 +236,6 @@ module caravel (
.vccd2_pad (vccd2), // User area 2 1.8V supply .vccd2_pad (vccd2), // User area 2 1.8V supply
.vssd1_pad (vssd1), // User area 1 digital ground .vssd1_pad (vssd1), // User area 1 digital ground
.vssd2_pad (vssd2), // User area 2 digital ground .vssd2_pad (vssd2), // User area 2 digital ground
`endif
// Core Side Pins // Core Side Pins
.vddio (vddio_core), .vddio (vddio_core),
.vssio (vssio_core), .vssio (vssio_core),
@ -252,6 +251,7 @@ module caravel (
.vccd2 (vccd2_core), .vccd2 (vccd2_core),
.vssd1 (vssd1_core), .vssd1 (vssd1_core),
.vssd2 (vssd2_core), .vssd2 (vssd2_core),
`endif
.gpio(gpio), .gpio(gpio),
.mprj_io(mprj_io), .mprj_io(mprj_io),
@ -1410,8 +1410,7 @@ module caravel (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vdd3v3(vddio_core), .vdd3v3(vddio_core),
.vdd1v8(vccd_core), .vdd1v8(vccd_core),
.vss3v3(vssio_core), .vss(vssio_core),
.vss1v8(vssd_core),
`endif `endif
.porb_h(porb_h), .porb_h(porb_h),
.porb_l(porb_l), .porb_l(porb_l),

15
verilog/rtl/simple_por.v
View File

@ -20,8 +20,7 @@ module simple_por(
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
inout vdd3v3, inout vdd3v3,
inout vdd1v8, inout vdd1v8,
inout vss3v3, inout vss,
inout vss1v8,
`endif `endif
output porb_h, output porb_h,
output porb_l, output porb_l,
@ -55,9 +54,9 @@ module simple_por(
sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 ( sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.VPWR(vdd3v3), .VPWR(vdd3v3),
.VGND(vss3v3), .VGND(vss),
.VPB(vdd3v3), .VPB(vdd3v3),
.VNB(vss3v3), .VNB(vss),
`endif `endif
.A(inode), .A(inode),
.X(mid) .X(mid)
@ -66,9 +65,9 @@ module simple_por(
sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 ( sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.VPWR(vdd3v3), .VPWR(vdd3v3),
.VGND(vss3v3), .VGND(vss),
.VPB(vdd3v3), .VPB(vdd3v3),
.VNB(vss3v3), .VNB(vss),
`endif `endif
.A(mid), .A(mid),
.X(porb_h) .X(porb_h)
@ -79,8 +78,8 @@ module simple_por(
.VPWR(vdd3v3), .VPWR(vdd3v3),
.VPB(vdd3v3), .VPB(vdd3v3),
.LVPWR(vdd1v8), .LVPWR(vdd1v8),
.VNB(vss3v3), .VNB(vss),
.VGND(vss3v3), .VGND(vss),
`endif `endif
.A(porb_h), .A(porb_h),
.X(porb_l) .X(porb_l)