From b5234b269f347f97cda74e9325cd0bfd05d11808 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 17 Oct 2022 08:29:39 -0700 Subject: [PATCH] fix debug test --- verilog/dv/cocotb/tests/debug/debug.c | 34 ++++++-------------------- verilog/dv/cocotb/tests/debug/debug.py | 26 +++++++++----------- 2 files changed, 18 insertions(+), 42 deletions(-) diff --git a/verilog/dv/cocotb/tests/debug/debug.c b/verilog/dv/cocotb/tests/debug/debug.c index 3c0e16b5..b54e35ff 100644 --- a/verilog/dv/cocotb/tests/debug/debug.c +++ b/verilog/dv/cocotb/tests/debug/debug.c @@ -30,43 +30,23 @@ void main() reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; - // Set clock to 64 kbaud and enable the UART. It is important to do this - // before applying the configuration, or else the Tx line initializes as - // zero, which indicates the start of a byte to the receiver. + (*(volatile uint32_t*) CSR_DEBUG_MODE_OUT_ADDR ) = 1; // enable debug mode // Now, apply the configuration reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); + // reg_uart_enable = 1; // start of the test reg_debug_1 = 0xAA; + // very long wait - for (j = 0; j < 160; j++); - for (j = 0; j < 160; j++); - for (j = 0; j < 160; j++); + for (j = 0; j < 1600; j++); + for (j = 0; j < 1600; j++); + for (j = 0; j < 1600; j++); - // Set clock to 64 kbaud and enable the UART. It is important to do this - // before applying the configuration, or else the Tx line initializes as - // zero, which indicates the start of a byte to the receiver. - -// // these instruction work without using interrupt, they seem to be timing dependent -// reg_uart_enable = 1; -// reg_debug_irq_en = 1; -// reg_reset = 1; - - -// irq_setmask(0); -// irq_setie(1); -// irq_setmask(irq_getmask() | (1 << USER_IRQ_3_INTERRUPT)); - -// for (j = 0; j < 500; j++); - -// // reg_uart_data = 0xab; - -// // Allow transmission to complete before signalling that the program -// // has ended. -// for (j = 0; j < 160; j++); } diff --git a/verilog/dv/cocotb/tests/debug/debug.py b/verilog/dv/cocotb/tests/debug/debug.py index 09a8a479..7dbc900d 100644 --- a/verilog/dv/cocotb/tests/debug/debug.py +++ b/verilog/dv/cocotb/tests/debug/debug.py @@ -26,24 +26,26 @@ async def debug(dut): # calculate bit time clk = clock.period/1000 global bit_time_ns - bit_time_ns = round(10**5 * clk / (96)) + bit_time_ns = round(10**5 * clk / (1152)) cocotb.log.info(f"[TEST] bit time in nano second = {bit_time_ns}") - caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug + caravelEnv.drive_gpio_in((0,0),1) # IO[0] affects the uart selecting btw system and debug caravelEnv.drive_gpio_in((5,5),1) # wait for start of sending await wait_reg1(cpu,caravelEnv,0XAA) + # caravelEnv.drive_gpio_in((0,0),1) # IO[0] affects the uart selecting btw system and debug cocotb.log.info(f"[TEST] Start debug test") # send random data to address 30'h00400024 and expect to recieve the same data back it back - address = 0x00000410 + dff_address = random.randint(0x00000400, 0x00000600) data = random.getrandbits(32) - data = 0xFFFFFFFF - cocotb.log.info (f"[TEST] Executing DFF2 write address={hex(address)} data = {hex(data)}") + address = dff_address >>2 # address has to be shifted + # data = 0xFFFFFFF0 + cocotb.log.info (f"[TEST] Executing DFF2 write address={hex(dff_address)} data = {hex(data)}") await wb_write(caravelEnv,address,data) receieved_data = await wb_read(caravelEnv,address) if data != receieved_data: - cocotb.log.error(f"[TEST] DFF2 write failed expected data = {hex(data)} recieved data = {hex(receieved_data)}") + cocotb.log.error(f"[TEST] DFF2 reading failed from address {hex(address)} expected data = {hex(data)} recieved data = {hex(receieved_data)}") else: - cocotb.log.info(f"[TEST] DFF2 write succeeded") + cocotb.log.info(f"[TEST] PASS: DFF2 reading right value {hex(data)} from {hex(address)} ") async def start_of_tx(caravelEnv): @@ -66,18 +68,12 @@ async def uart_send_char(caravelEnv,char): # stop of frame caravelEnv.drive_gpio_in((5,5),1) await Timer(bit_time_ns, units='ns') - await Timer(bit_time_ns, units='ns') - # insert 4 bit delay just for debugging - await Timer(bit_time_ns, units='ns') - await Timer(bit_time_ns, units='ns') - await Timer(bit_time_ns, units='ns') - await Timer(bit_time_ns, units='ns') - + async def uart_get_char(caravelEnv): await start_of_tx(caravelEnv) char = '' for i in range (8): - char = char + caravelEnv.monitor_gpio((6,6)).binstr + char = caravelEnv.monitor_gpio((6,6)).binstr + char await Timer(bit_time_ns, units='ns') cocotb.log.info (f"[uart_get_char] recieving {char} from uart")