mirror of https://github.com/efabless/caravel.git
Merge branch 'caravel_redesign' into cocotb
This commit is contained in:
commit
a741ec4525
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
@ -356,19 +356,19 @@ MACRO gpio_control_block
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 5.900 51.760 7.500 ;
|
RECT 4.360 5.900 50.000 7.500 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 22.800 51.760 24.400 ;
|
RECT 4.360 22.800 50.000 24.400 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 39.700 51.760 41.300 ;
|
RECT 4.360 39.700 50.000 41.300 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 56.600 51.760 58.200 ;
|
RECT 4.360 56.600 50.000 58.200 ;
|
||||||
END
|
END
|
||||||
END vccd
|
END vccd
|
||||||
PIN vccd1
|
PIN vccd1
|
||||||
|
@ -384,15 +384,15 @@ MACRO gpio_control_block
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 11.140 51.760 12.740 ;
|
RECT 4.360 11.140 50.000 12.740 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 28.040 51.760 29.640 ;
|
RECT 4.360 28.040 50.000 29.640 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 44.940 51.760 46.540 ;
|
RECT 4.360 44.940 50.000 46.540 ;
|
||||||
END
|
END
|
||||||
END vccd1
|
END vccd1
|
||||||
PIN vssd
|
PIN vssd
|
||||||
|
@ -404,15 +404,15 @@ MACRO gpio_control_block
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 14.350 51.760 15.950 ;
|
RECT 4.360 14.350 50.000 15.950 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 31.250 51.760 32.850 ;
|
RECT 4.360 31.250 50.000 32.850 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 48.150 51.760 49.750 ;
|
RECT 4.360 48.150 50.000 49.750 ;
|
||||||
END
|
END
|
||||||
END vssd
|
END vssd
|
||||||
PIN vssd1
|
PIN vssd1
|
||||||
|
@ -424,15 +424,15 @@ MACRO gpio_control_block
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 19.590 51.760 21.190 ;
|
RECT 4.360 19.590 50.000 21.190 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 36.490 51.760 38.090 ;
|
RECT 4.360 36.490 50.000 38.090 ;
|
||||||
END
|
END
|
||||||
PORT
|
PORT
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 4.360 53.390 51.760 54.990 ;
|
RECT 4.360 53.390 50.000 54.990 ;
|
||||||
END
|
END
|
||||||
END vssd1
|
END vssd1
|
||||||
PIN zero
|
PIN zero
|
||||||
|
@ -718,68 +718,68 @@ MACRO gpio_control_block
|
||||||
RECT 28.250 60.720 29.710 65.000 ;
|
RECT 28.250 60.720 29.710 65.000 ;
|
||||||
RECT 30.550 60.720 32.010 65.000 ;
|
RECT 30.550 60.720 32.010 65.000 ;
|
||||||
RECT 32.850 60.720 170.000 65.000 ;
|
RECT 32.850 60.720 170.000 65.000 ;
|
||||||
RECT 4.700 0.000 170.000 60.720 ;
|
RECT 4.690 0.000 170.000 60.720 ;
|
||||||
LAYER met3 ;
|
LAYER met3 ;
|
||||||
RECT 6.280 60.840 69.600 61.705 ;
|
RECT 4.665 60.840 69.600 61.705 ;
|
||||||
RECT 6.280 60.200 70.000 60.840 ;
|
RECT 4.665 60.200 70.000 60.840 ;
|
||||||
RECT 6.280 58.800 69.600 60.200 ;
|
RECT 4.665 58.800 69.600 60.200 ;
|
||||||
RECT 6.280 58.160 70.000 58.800 ;
|
RECT 4.665 58.160 70.000 58.800 ;
|
||||||
RECT 6.280 56.760 69.600 58.160 ;
|
RECT 4.665 56.760 69.600 58.160 ;
|
||||||
RECT 6.280 56.120 70.000 56.760 ;
|
RECT 4.665 56.120 70.000 56.760 ;
|
||||||
RECT 6.280 54.720 69.600 56.120 ;
|
RECT 4.665 54.720 69.600 56.120 ;
|
||||||
RECT 6.280 54.080 70.000 54.720 ;
|
RECT 4.665 54.080 70.000 54.720 ;
|
||||||
RECT 6.280 52.680 69.600 54.080 ;
|
RECT 4.665 52.680 69.600 54.080 ;
|
||||||
RECT 6.280 52.040 70.000 52.680 ;
|
RECT 4.665 52.040 70.000 52.680 ;
|
||||||
RECT 6.280 50.640 69.600 52.040 ;
|
RECT 4.665 50.640 69.600 52.040 ;
|
||||||
RECT 6.280 50.000 70.000 50.640 ;
|
RECT 4.665 50.000 70.000 50.640 ;
|
||||||
RECT 6.280 48.600 69.600 50.000 ;
|
RECT 4.665 48.600 69.600 50.000 ;
|
||||||
RECT 6.280 47.960 70.000 48.600 ;
|
RECT 4.665 47.960 70.000 48.600 ;
|
||||||
RECT 6.280 46.560 69.600 47.960 ;
|
RECT 4.665 46.560 69.600 47.960 ;
|
||||||
RECT 6.280 45.920 70.000 46.560 ;
|
RECT 4.665 45.920 70.000 46.560 ;
|
||||||
RECT 6.280 44.520 69.600 45.920 ;
|
RECT 4.665 44.520 69.600 45.920 ;
|
||||||
RECT 6.280 43.880 70.000 44.520 ;
|
RECT 4.665 43.880 70.000 44.520 ;
|
||||||
RECT 6.280 42.480 69.600 43.880 ;
|
RECT 4.665 42.480 69.600 43.880 ;
|
||||||
RECT 6.280 41.840 70.000 42.480 ;
|
RECT 4.665 41.840 70.000 42.480 ;
|
||||||
RECT 6.280 40.440 69.600 41.840 ;
|
RECT 4.665 40.440 69.600 41.840 ;
|
||||||
RECT 6.280 39.800 70.000 40.440 ;
|
RECT 4.665 39.800 70.000 40.440 ;
|
||||||
RECT 6.280 38.400 69.600 39.800 ;
|
RECT 4.665 38.400 69.600 39.800 ;
|
||||||
RECT 6.280 37.760 70.000 38.400 ;
|
RECT 4.665 37.760 70.000 38.400 ;
|
||||||
RECT 6.280 36.360 69.600 37.760 ;
|
RECT 4.665 36.360 69.600 37.760 ;
|
||||||
RECT 6.280 35.720 70.000 36.360 ;
|
RECT 4.665 35.720 70.000 36.360 ;
|
||||||
RECT 6.280 34.320 69.600 35.720 ;
|
RECT 4.665 34.320 69.600 35.720 ;
|
||||||
RECT 6.280 33.680 70.000 34.320 ;
|
RECT 4.665 33.680 70.000 34.320 ;
|
||||||
RECT 6.280 32.280 69.600 33.680 ;
|
RECT 4.665 32.280 69.600 33.680 ;
|
||||||
RECT 6.280 31.640 70.000 32.280 ;
|
RECT 4.665 31.640 70.000 32.280 ;
|
||||||
RECT 6.280 30.240 69.600 31.640 ;
|
RECT 4.665 30.240 69.600 31.640 ;
|
||||||
RECT 6.280 29.600 70.000 30.240 ;
|
RECT 4.665 29.600 70.000 30.240 ;
|
||||||
RECT 6.280 28.200 69.600 29.600 ;
|
RECT 4.665 28.200 69.600 29.600 ;
|
||||||
RECT 6.280 27.560 70.000 28.200 ;
|
RECT 4.665 27.560 70.000 28.200 ;
|
||||||
RECT 6.280 26.160 69.600 27.560 ;
|
RECT 4.665 26.160 69.600 27.560 ;
|
||||||
RECT 6.280 25.520 70.000 26.160 ;
|
RECT 4.665 25.520 70.000 26.160 ;
|
||||||
RECT 6.280 24.120 69.600 25.520 ;
|
RECT 4.665 24.120 69.600 25.520 ;
|
||||||
RECT 6.280 23.480 70.000 24.120 ;
|
RECT 4.665 23.480 70.000 24.120 ;
|
||||||
RECT 6.280 22.080 69.600 23.480 ;
|
RECT 4.665 22.080 69.600 23.480 ;
|
||||||
RECT 6.280 21.440 70.000 22.080 ;
|
RECT 4.665 21.440 70.000 22.080 ;
|
||||||
RECT 6.280 20.040 69.600 21.440 ;
|
RECT 4.665 20.040 69.600 21.440 ;
|
||||||
RECT 6.280 19.400 70.000 20.040 ;
|
RECT 4.665 19.400 70.000 20.040 ;
|
||||||
RECT 6.280 18.000 69.600 19.400 ;
|
RECT 4.665 18.000 69.600 19.400 ;
|
||||||
RECT 6.280 17.360 70.000 18.000 ;
|
RECT 4.665 17.360 70.000 18.000 ;
|
||||||
RECT 6.280 15.960 69.600 17.360 ;
|
RECT 4.665 15.960 69.600 17.360 ;
|
||||||
RECT 6.280 15.320 70.000 15.960 ;
|
RECT 4.665 15.320 70.000 15.960 ;
|
||||||
RECT 6.280 13.920 69.600 15.320 ;
|
RECT 4.665 13.920 69.600 15.320 ;
|
||||||
RECT 6.280 13.280 70.000 13.920 ;
|
RECT 4.665 13.280 70.000 13.920 ;
|
||||||
RECT 6.280 11.880 69.600 13.280 ;
|
RECT 4.665 11.880 69.600 13.280 ;
|
||||||
RECT 6.280 11.240 70.000 11.880 ;
|
RECT 4.665 11.240 70.000 11.880 ;
|
||||||
RECT 6.280 9.840 69.600 11.240 ;
|
RECT 4.665 9.840 69.600 11.240 ;
|
||||||
RECT 6.280 9.200 70.000 9.840 ;
|
RECT 4.665 9.200 70.000 9.840 ;
|
||||||
RECT 6.280 7.800 69.600 9.200 ;
|
RECT 4.665 7.800 69.600 9.200 ;
|
||||||
RECT 6.280 7.160 70.000 7.800 ;
|
RECT 4.665 7.160 70.000 7.800 ;
|
||||||
RECT 6.280 5.760 69.600 7.160 ;
|
RECT 4.665 5.760 69.600 7.160 ;
|
||||||
RECT 6.280 5.120 70.000 5.760 ;
|
RECT 4.665 5.120 70.000 5.760 ;
|
||||||
RECT 6.280 3.720 69.600 5.120 ;
|
RECT 4.665 3.720 69.600 5.120 ;
|
||||||
RECT 6.280 3.080 70.000 3.720 ;
|
RECT 4.665 3.080 70.000 3.720 ;
|
||||||
RECT 6.280 1.680 69.600 3.080 ;
|
RECT 4.665 1.680 69.600 3.080 ;
|
||||||
RECT 6.280 0.175 70.000 1.680 ;
|
RECT 4.665 0.175 70.000 1.680 ;
|
||||||
LAYER met4 ;
|
LAYER met4 ;
|
||||||
RECT 6.280 60.480 170.000 65.000 ;
|
RECT 6.280 60.480 170.000 65.000 ;
|
||||||
RECT 6.280 2.080 12.400 60.480 ;
|
RECT 6.280 2.080 12.400 60.480 ;
|
||||||
|
@ -791,7 +791,21 @@ MACRO gpio_control_block
|
||||||
RECT 44.800 2.080 170.000 60.480 ;
|
RECT 44.800 2.080 170.000 60.480 ;
|
||||||
RECT 6.280 0.000 170.000 2.080 ;
|
RECT 6.280 0.000 170.000 2.080 ;
|
||||||
LAYER met5 ;
|
LAYER met5 ;
|
||||||
RECT 67.000 0.000 170.000 65.000 ;
|
RECT 50.000 59.800 170.000 65.000 ;
|
||||||
|
RECT 51.600 51.790 170.000 59.800 ;
|
||||||
|
RECT 50.000 51.350 170.000 51.790 ;
|
||||||
|
RECT 51.600 43.340 170.000 51.350 ;
|
||||||
|
RECT 50.000 42.900 170.000 43.340 ;
|
||||||
|
RECT 51.600 34.890 170.000 42.900 ;
|
||||||
|
RECT 50.000 34.450 170.000 34.890 ;
|
||||||
|
RECT 51.600 26.440 170.000 34.450 ;
|
||||||
|
RECT 50.000 26.000 170.000 26.440 ;
|
||||||
|
RECT 51.600 17.990 170.000 26.000 ;
|
||||||
|
RECT 50.000 17.550 170.000 17.990 ;
|
||||||
|
RECT 51.600 9.540 170.000 17.550 ;
|
||||||
|
RECT 50.000 9.100 170.000 9.540 ;
|
||||||
|
RECT 51.600 4.300 170.000 9.100 ;
|
||||||
|
RECT 50.000 0.000 170.000 4.300 ;
|
||||||
END
|
END
|
||||||
END gpio_control_block
|
END gpio_control_block
|
||||||
END LIBRARY
|
END LIBRARY
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,7 +1,7 @@
|
||||||
magic
|
magic
|
||||||
tech sky130A
|
tech sky130A
|
||||||
magscale 1 2
|
magscale 1 2
|
||||||
timestamp 1664286915
|
timestamp 1664976471
|
||||||
<< obsli1 >>
|
<< obsli1 >>
|
||||||
rect 0 13000 853 13014
|
rect 0 13000 853 13014
|
||||||
rect 0 0 33962 13000
|
rect 0 0 33962 13000
|
||||||
|
@ -35,7 +35,7 @@ rect 5190 12144 5482 13000
|
||||||
rect 5650 12144 5942 13000
|
rect 5650 12144 5942 13000
|
||||||
rect 6110 12144 6402 13000
|
rect 6110 12144 6402 13000
|
||||||
rect 6570 12144 34000 13000
|
rect 6570 12144 34000 13000
|
||||||
rect 940 0 34000 12144
|
rect 938 0 34000 12144
|
||||||
<< metal3 >>
|
<< metal3 >>
|
||||||
rect 14000 12248 34000 12368
|
rect 14000 12248 34000 12368
|
||||||
rect 14000 11840 34000 11960
|
rect 14000 11840 34000 11960
|
||||||
|
@ -68,66 +68,66 @@ rect 14000 1232 34000 1352
|
||||||
rect 14000 824 34000 944
|
rect 14000 824 34000 944
|
||||||
rect 14000 416 34000 536
|
rect 14000 416 34000 536
|
||||||
<< obsm3 >>
|
<< obsm3 >>
|
||||||
rect 1256 12168 13920 12341
|
rect 933 12168 13920 12341
|
||||||
rect 1256 12040 14000 12168
|
rect 933 12040 14000 12168
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||||||
rect 1256 11760 13920 12040
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rect 933 11760 13920 12040
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||||||
rect 1256 11632 14000 11760
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rect 933 11632 14000 11760
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rect 1256 11352 13920 11632
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rect 933 11352 13920 11632
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rect 1256 11224 14000 11352
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rect 933 11224 14000 11352
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rect 1256 10944 13920 11224
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rect 933 10944 13920 11224
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rect 1256 10816 14000 10944
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rect 1256 9312 13920 9592
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rect 1256 8904 13920 9184
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rect 933 8904 13920 9184
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rect 1256 8776 14000 8904
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rect 933 8776 14000 8904
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rect 1256 8496 13920 8776
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rect 933 8496 13920 8776
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rect 1256 8368 14000 8496
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rect 933 8368 14000 8496
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rect 1256 8088 13920 8368
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rect 933 7960 14000 8088
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rect 1256 7680 13920 7960
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rect 933 7680 13920 7960
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rect 933 7552 14000 7680
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rect 933 6864 13920 7144
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rect 933 6736 14000 6864
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rect 933 6456 13920 6736
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rect 1256 6328 14000 6456
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rect 933 6328 14000 6456
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rect 1256 6048 13920 6328
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rect 933 6048 13920 6328
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rect 1256 5920 14000 6048
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rect 933 5920 14000 6048
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rect 1256 5640 13920 5920
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rect 933 5640 13920 5920
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rect 1256 5512 14000 5640
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rect 933 5512 14000 5640
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rect 1256 5232 13920 5512
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rect 933 5232 13920 5512
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||||||
rect 1256 5104 14000 5232
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rect 933 5104 14000 5232
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rect 1256 4824 13920 5104
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rect 933 4824 13920 5104
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||||||
rect 1256 4696 14000 4824
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rect 933 4696 14000 4824
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||||||
rect 1256 4416 13920 4696
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rect 933 4416 13920 4696
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||||||
rect 1256 4288 14000 4416
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rect 933 4288 14000 4416
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||||||
rect 1256 4008 13920 4288
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rect 933 4008 13920 4288
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||||||
rect 1256 3880 14000 4008
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rect 933 3880 14000 4008
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||||||
rect 1256 3600 13920 3880
|
rect 933 3600 13920 3880
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||||||
rect 1256 3472 14000 3600
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rect 933 3472 14000 3600
|
||||||
rect 1256 3192 13920 3472
|
rect 933 3192 13920 3472
|
||||||
rect 1256 3064 14000 3192
|
rect 933 3064 14000 3192
|
||||||
rect 1256 2784 13920 3064
|
rect 933 2784 13920 3064
|
||||||
rect 1256 2656 14000 2784
|
rect 933 2656 14000 2784
|
||||||
rect 1256 2376 13920 2656
|
rect 933 2376 13920 2656
|
||||||
rect 1256 2248 14000 2376
|
rect 933 2248 14000 2376
|
||||||
rect 1256 1968 13920 2248
|
rect 933 1968 13920 2248
|
||||||
rect 1256 1840 14000 1968
|
rect 933 1840 14000 1968
|
||||||
rect 1256 1560 13920 1840
|
rect 933 1560 13920 1840
|
||||||
rect 1256 1432 14000 1560
|
rect 933 1432 14000 1560
|
||||||
rect 1256 1152 13920 1432
|
rect 933 1152 13920 1432
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||||||
rect 1256 1024 14000 1152
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rect 933 1024 14000 1152
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||||||
rect 1256 744 13920 1024
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rect 933 744 13920 1024
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||||||
rect 1256 616 14000 744
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rect 933 616 14000 744
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||||||
rect 1256 336 13920 616
|
rect 933 336 13920 616
|
||||||
rect 1256 35 14000 336
|
rect 933 35 14000 336
|
||||||
<< metal4 >>
|
<< metal4 >>
|
||||||
rect 2560 496 2880 12016
|
rect 2560 496 2880 12016
|
||||||
rect 3560 496 3880 12016
|
rect 3560 496 3880 12016
|
||||||
|
@ -146,21 +146,35 @@ rect 7960 416 8480 12096
|
||||||
rect 8960 416 34000 12096
|
rect 8960 416 34000 12096
|
||||||
rect 1256 0 34000 416
|
rect 1256 0 34000 416
|
||||||
<< metal5 >>
|
<< metal5 >>
|
||||||
rect 872 11320 10352 11640
|
rect 872 11320 10000 11640
|
||||||
rect 872 10678 10352 10998
|
rect 872 10678 10000 10998
|
||||||
rect 872 9630 10352 9950
|
rect 872 9630 10000 9950
|
||||||
rect 872 8988 10352 9308
|
rect 872 8988 10000 9308
|
||||||
rect 872 7940 10352 8260
|
rect 872 7940 10000 8260
|
||||||
rect 872 7298 10352 7618
|
rect 872 7298 10000 7618
|
||||||
rect 872 6250 10352 6570
|
rect 872 6250 10000 6570
|
||||||
rect 872 5608 10352 5928
|
rect 872 5608 10000 5928
|
||||||
rect 872 4560 10352 4880
|
rect 872 4560 10000 4880
|
||||||
rect 872 3918 10352 4238
|
rect 872 3918 10000 4238
|
||||||
rect 872 2870 10352 3190
|
rect 872 2870 10000 3190
|
||||||
rect 872 2228 10352 2548
|
rect 872 2228 10000 2548
|
||||||
rect 872 1180 10352 1500
|
rect 872 1180 10000 1500
|
||||||
<< obsm5 >>
|
<< obsm5 >>
|
||||||
rect 13400 0 34000 13000
|
rect 10000 11960 34000 13000
|
||||||
|
rect 10320 10358 34000 11960
|
||||||
|
rect 10000 10270 34000 10358
|
||||||
|
rect 10320 8668 34000 10270
|
||||||
|
rect 10000 8580 34000 8668
|
||||||
|
rect 10320 6978 34000 8580
|
||||||
|
rect 10000 6890 34000 6978
|
||||||
|
rect 10320 5288 34000 6890
|
||||||
|
rect 10000 5200 34000 5288
|
||||||
|
rect 10320 3598 34000 5200
|
||||||
|
rect 10000 3510 34000 3598
|
||||||
|
rect 10320 1908 34000 3510
|
||||||
|
rect 10000 1820 34000 1908
|
||||||
|
rect 10320 860 34000 1820
|
||||||
|
rect 10000 0 34000 860
|
||||||
<< labels >>
|
<< labels >>
|
||||||
rlabel metal2 s 938 12200 994 13000 6 gpio_defaults[0]
|
rlabel metal2 s 938 12200 994 13000 6 gpio_defaults[0]
|
||||||
port 1 nsew signal input
|
port 1 nsew signal input
|
||||||
|
@ -250,39 +264,39 @@ rlabel metal4 s 2560 496 2880 12016 6 vccd
|
||||||
port 43 nsew power bidirectional
|
port 43 nsew power bidirectional
|
||||||
rlabel metal4 s 7560 496 7880 12016 6 vccd
|
rlabel metal4 s 7560 496 7880 12016 6 vccd
|
||||||
port 43 nsew power bidirectional
|
port 43 nsew power bidirectional
|
||||||
rlabel metal5 s 872 1180 10352 1500 6 vccd
|
rlabel metal5 s 872 1180 10000 1500 6 vccd
|
||||||
port 43 nsew power bidirectional
|
port 43 nsew power bidirectional
|
||||||
rlabel metal5 s 872 4560 10352 4880 6 vccd
|
rlabel metal5 s 872 4560 10000 4880 6 vccd
|
||||||
port 43 nsew power bidirectional
|
port 43 nsew power bidirectional
|
||||||
rlabel metal5 s 872 7940 10352 8260 6 vccd
|
rlabel metal5 s 872 7940 10000 8260 6 vccd
|
||||||
port 43 nsew power bidirectional
|
port 43 nsew power bidirectional
|
||||||
rlabel metal5 s 872 11320 10352 11640 6 vccd
|
rlabel metal5 s 872 11320 10000 11640 6 vccd
|
||||||
port 43 nsew power bidirectional
|
port 43 nsew power bidirectional
|
||||||
rlabel metal4 s 3560 496 3880 12016 6 vccd1
|
rlabel metal4 s 3560 496 3880 12016 6 vccd1
|
||||||
port 44 nsew power bidirectional
|
port 44 nsew power bidirectional
|
||||||
rlabel metal4 s 8560 496 8880 12016 6 vccd1
|
rlabel metal4 s 8560 496 8880 12016 6 vccd1
|
||||||
port 44 nsew power bidirectional
|
port 44 nsew power bidirectional
|
||||||
rlabel metal5 s 872 2228 10352 2548 6 vccd1
|
rlabel metal5 s 872 2228 10000 2548 6 vccd1
|
||||||
port 44 nsew power bidirectional
|
port 44 nsew power bidirectional
|
||||||
rlabel metal5 s 872 5608 10352 5928 6 vccd1
|
rlabel metal5 s 872 5608 10000 5928 6 vccd1
|
||||||
port 44 nsew power bidirectional
|
port 44 nsew power bidirectional
|
||||||
rlabel metal5 s 872 8988 10352 9308 6 vccd1
|
rlabel metal5 s 872 8988 10000 9308 6 vccd1
|
||||||
port 44 nsew power bidirectional
|
port 44 nsew power bidirectional
|
||||||
rlabel metal4 s 5060 496 5380 12016 6 vssd
|
rlabel metal4 s 5060 496 5380 12016 6 vssd
|
||||||
port 45 nsew ground bidirectional
|
port 45 nsew ground bidirectional
|
||||||
rlabel metal5 s 872 2870 10352 3190 6 vssd
|
rlabel metal5 s 872 2870 10000 3190 6 vssd
|
||||||
port 45 nsew ground bidirectional
|
port 45 nsew ground bidirectional
|
||||||
rlabel metal5 s 872 6250 10352 6570 6 vssd
|
rlabel metal5 s 872 6250 10000 6570 6 vssd
|
||||||
port 45 nsew ground bidirectional
|
port 45 nsew ground bidirectional
|
||||||
rlabel metal5 s 872 9630 10352 9950 6 vssd
|
rlabel metal5 s 872 9630 10000 9950 6 vssd
|
||||||
port 45 nsew ground bidirectional
|
port 45 nsew ground bidirectional
|
||||||
rlabel metal4 s 6060 496 6380 12016 6 vssd1
|
rlabel metal4 s 6060 496 6380 12016 6 vssd1
|
||||||
port 46 nsew ground bidirectional
|
port 46 nsew ground bidirectional
|
||||||
rlabel metal5 s 872 3918 10352 4238 6 vssd1
|
rlabel metal5 s 872 3918 10000 4238 6 vssd1
|
||||||
port 46 nsew ground bidirectional
|
port 46 nsew ground bidirectional
|
||||||
rlabel metal5 s 872 7298 10352 7618 6 vssd1
|
rlabel metal5 s 872 7298 10000 7618 6 vssd1
|
||||||
port 46 nsew ground bidirectional
|
port 46 nsew ground bidirectional
|
||||||
rlabel metal5 s 872 10678 10352 10998 6 vssd1
|
rlabel metal5 s 872 10678 10000 10998 6 vssd1
|
||||||
port 46 nsew ground bidirectional
|
port 46 nsew ground bidirectional
|
||||||
rlabel metal3 s 14000 416 34000 536 6 zero
|
rlabel metal3 s 14000 416 34000 536 6 zero
|
||||||
port 47 nsew signal output
|
port 47 nsew signal output
|
||||||
|
@ -290,8 +304,8 @@ port 47 nsew signal output
|
||||||
string FIXED_BBOX 0 0 34000 13000
|
string FIXED_BBOX 0 0 34000 13000
|
||||||
string LEFclass BLOCK
|
string LEFclass BLOCK
|
||||||
string LEFview TRUE
|
string LEFview TRUE
|
||||||
string GDS_END 572784
|
string GDS_END 572912
|
||||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_27_06_53/results/signoff/gpio_control_block.magic.gds
|
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_05_06_26/results/signoff/gpio_control_block.magic.gds
|
||||||
string GDS_START 204218
|
string GDS_START 204218
|
||||||
<< end >>
|
<< end >>
|
||||||
|
|
||||||
|
|
2
manifest
2
manifest
|
@ -19,7 +19,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
||||||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||||
9ef209f70c9e73eac04890458a5c49b39347376e verilog/rtl/housekeeping.v
|
9ef209f70c9e73eac04890458a5c49b39347376e verilog/rtl/housekeeping.v
|
||||||
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
||||||
9cb20aace3daaae58f74b4a280053e7d1ed6b8e3 verilog/rtl/mgmt_protect.v
|
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
|
||||||
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
||||||
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
|
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
|
||||||
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
|
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
|
||||||
|
|
|
@ -97,7 +97,7 @@ set ::env(GRT_OBS) "\
|
||||||
li1 4.21500 57.40500 49.81500 64.93000,
|
li1 4.21500 57.40500 49.81500 64.93000,
|
||||||
li1 16.83000 0 49.41000 5.24000,
|
li1 16.83000 0 49.41000 5.24000,
|
||||||
li1 49.000 0 169.81000 64.84500,
|
li1 49.000 0 169.81000 64.84500,
|
||||||
met5 67 0 170 65,
|
met5 50 0 170 65,
|
||||||
met4 49 0 170 65,
|
met4 49 0 170 65,
|
||||||
met2 120 0 170 65,
|
met2 120 0 170 65,
|
||||||
met1 120 0 170 65"
|
met1 120 0 170 65"
|
||||||
|
|
|
@ -55,9 +55,9 @@ proc custom_run_placement {args} {
|
||||||
}
|
}
|
||||||
|
|
||||||
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
||||||
prep -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
|
prep -design $SCRIPT_DIR -tag $::env(TAG) -overwrite -verbose 0
|
||||||
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||||
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
exec ln -sf $SCRIPT_DIR/runs/$::env(TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||||
run_synthesis
|
run_synthesis
|
||||||
|
|
||||||
init_floorplan
|
init_floorplan
|
||||||
|
@ -69,7 +69,7 @@ tap_decap_or
|
||||||
add_route_obs
|
add_route_obs
|
||||||
run_power_grid_generation
|
run_power_grid_generation
|
||||||
|
|
||||||
set dont_use_old ::env(DONT_USE_CELLS)
|
set dont_use_old $::env(DONT_USE_CELLS)
|
||||||
global_placement_or
|
global_placement_or
|
||||||
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) sky130_fd_sc_hd__buf_1"
|
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) sky130_fd_sc_hd__buf_1"
|
||||||
run_resizer_design
|
run_resizer_design
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
###############################################################################
|
###############################################################################
|
||||||
# Created by write_sdc
|
# Created by write_sdc
|
||||||
# Tue Sep 27 13:54:44 2022
|
# Wed Oct 5 13:27:20 2022
|
||||||
###############################################################################
|
###############################################################################
|
||||||
current_design gpio_control_block
|
current_design gpio_control_block
|
||||||
###############################################################################
|
###############################################################################
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -180,7 +180,7 @@ module mgmt_protect (
|
||||||
|
|
||||||
// Protection, similar to the above, for the three user IRQ lines
|
// Protection, similar to the above, for the three user IRQ lines
|
||||||
|
|
||||||
assign user_irq_enable = user_irq_ena & mrpj_logic1[460:458];
|
assign user_irq_enable = user_irq_ena & mprj_logic1[460:458];
|
||||||
|
|
||||||
sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
|
sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
|
||||||
`ifdef USE_POWER_PINS
|
`ifdef USE_POWER_PINS
|
||||||
|
@ -233,7 +233,7 @@ module mgmt_protect (
|
||||||
// SoC dumping current into the user project area when
|
// SoC dumping current into the user project area when
|
||||||
// the user project area is powered down.
|
// the user project area is powered down.
|
||||||
|
|
||||||
assign user_reset = (~caravel_rstn) & mprj_logic1[0]);
|
assign user_reset = (~caravel_rstn) & mprj_logic1[0];
|
||||||
assign user_clock = caravel_clk & mprj_logic1[1];
|
assign user_clock = caravel_clk & mprj_logic1[1];
|
||||||
assign user_clock2 = caravel_clk2 & mprj_logic1[2];
|
assign user_clock2 = caravel_clk2 & mprj_logic1[2];
|
||||||
assign mprj_cyc_o_user = mprj_cyc_o_core & mprj_logic1[3];
|
assign mprj_cyc_o_user = mprj_cyc_o_core & mprj_logic1[3];
|
||||||
|
@ -252,7 +252,7 @@ module mgmt_protect (
|
||||||
/* Project data out enable (bar) from the managment side to the */
|
/* Project data out enable (bar) from the managment side to the */
|
||||||
/* user project area when the user project is powered down. */
|
/* user project area when the user project is powered down. */
|
||||||
|
|
||||||
assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202]);
|
assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202];
|
||||||
|
|
||||||
/* The conb cell output is a resistive connection directly to */
|
/* The conb cell output is a resistive connection directly to */
|
||||||
/* the power supply, so when returning the user1_powergood */
|
/* the power supply, so when returning the user1_powergood */
|
||||||
|
|
Loading…
Reference in New Issue