From a6e7b461283b5546d7e24f3b6bf557c60b010064 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 15:07:38 -0700 Subject: [PATCH] delete reading from uart register in uart_rx test --- verilog/dv/cocotb/tests/uart/uart.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 3d499938..9446fb4c 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -113,14 +113,14 @@ async def uart_send_char(caravelEnv,char): async def uart_check_char_recieved(caravelEnv,cpu): # check cpu recieved the correct character while True: - reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + # reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr reg1 = cpu.read_debug_reg1() cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") if reg1 == 0x1B: - cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") + cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character ") return if reg1 == 0x1E: - cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") + cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character ") return await ClockCycles(caravelEnv.clk,1) \ No newline at end of file