From a6d9dbf5351d7dd22ecc09eda430be0181027a46 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 7 Dec 2021 09:14:59 -0500 Subject: [PATCH] Corrected an inadvertant error in caravel_netlists.v that prevents gate-level simulations from running. Corrected caravan_netlists.v, which did not have the same change made yesterday to caravel_netlists.v for the DLL. --- verilog/rtl/caravan_netlists.v | 2 ++ verilog/rtl/caravel_netlists.v | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/rtl/caravan_netlists.v b/verilog/rtl/caravan_netlists.v index e0c0ae59..5760b26c 100644 --- a/verilog/rtl/caravan_netlists.v +++ b/verilog/rtl/caravan_netlists.v @@ -69,6 +69,8 @@ `include "gl/caravan.v" `else `include "digital_pll.v" + `include "digital_pll_controller.v" + `include "ring_osc2x13.v" `include "caravel_clocking.v" `include "user_id_programming.v" `include "clock_div.v" diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index 73426536..773bc124 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -48,8 +48,6 @@ `ifdef GL `include "gl/digital_pll.v" - `include "gl/digital_pll_controller.v" - `include "gl/ring_osc2x13.v" `include "gl/caravel_clocking.v" `include "gl/user_id_programming.v" `include "gl/chip_io.v"