diff --git a/verilog/gl/caravan_core.v b/verilog/gl/caravan_core.v
index 7226a536..d2884dff 100644
--- a/verilog/gl/caravan_core.v
+++ b/verilog/gl/caravan_core.v
@@ -1336524,15 +1336524,15 @@ module caravan_core (clock_core,
  sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_ECO_1 (.VGND(vssd),
     .VPWR(vccd));
 
- sky130_ef_sc_hd__decap_12 EF_decap_12[53703:0] (VGND(vssd),
+ sky130_ef_sc_hd__decap_12 EF_decap_12[53703:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd));
- sky130_ef_sc_hd__fill_4 EF_fill_4[53702:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_4 EF_fill_4[53702:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 
- sky130_ef_sc_hd__fill_8 EF_fill_8[53702:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_8 EF_fill_8[53702:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 
diff --git a/verilog/gl/caravel_core.v b/verilog/gl/caravel_core.v
index 18f4b1a5..7986f47f 100644
--- a/verilog/gl/caravel_core.v
+++ b/verilog/gl/caravel_core.v
@@ -1298269,15 +1298269,15 @@ module caravel_core (clock_core,
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd));
- sky130_ef_sc_hd__decap_12 EF_decap_12[65364:0] (VGND(vssd),
+ sky130_ef_sc_hd__decap_12 EF_decap_12[65364:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd));
- sky130_ef_sc_hd__fill_4 EF_fill_4[57192:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_4 EF_fill_4[57192:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 
- sky130_ef_sc_hd__fill_8 EF_fill_8[57192:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_8 EF_fill_8[57192:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 
diff --git a/verilog/gl/housekeeping.v b/verilog/gl/housekeeping.v
index 31226c3c..d7e04d02 100644
--- a/verilog/gl/housekeeping.v
+++ b/verilog/gl/housekeeping.v
@@ -155461,7 +155461,7 @@ module housekeeping (VGND,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
-  sky130_ef_sc_hd__fill_8 fill4[604:0] (.VGND(VGND),
+  sky130_ef_sc_hd__fill_8 fill8[604:0] (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
diff --git a/verilog/gl/housekeeping_alt.v b/verilog/gl/housekeeping_alt.v
index c1c09ecc..035b9dad 100644
--- a/verilog/gl/housekeeping_alt.v
+++ b/verilog/gl/housekeeping_alt.v
@@ -142365,7 +142365,7 @@ module housekeeping_alt (VGND,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
-  sky130_ef_sc_hd__fill_8 fill4[768:0] (.VGND(VGND),
+  sky130_ef_sc_hd__fill_8 fill8[768:0] (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));