mirror of https://github.com/efabless/caravel.git
Merge branch 'cocotb' of github.com:efabless/caravel into cocotb
This commit is contained in:
commit
8991af8ff1
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@ -128,8 +128,8 @@
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,"hk_regs_wr_wb" :{"level":0,
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"SW":false,
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"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
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"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
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"GL_SDF":["r_sdf","weekly","tape_out"],
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"GL":[],
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"GL_SDF":[],
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"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
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,"hk_regs_wr_spi" :{"level":0,
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"SW":false,
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@ -0,0 +1,15 @@
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{
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"files.associations": {
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"optional": "c",
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"istream": "c",
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"ostream": "c",
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"ratio": "c",
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"system_error": "c",
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"array": "c",
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"functional": "c",
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"tuple": "c",
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"type_traits": "c",
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"utility": "c",
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"variant": "c"
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}
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}
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@ -14,5 +14,7 @@ void main(){
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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reg_debug_1 =0xAA;
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print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
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return;
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}
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@ -9,7 +9,7 @@ void main(){
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while (reg_debug_1 != 0xAA);
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reg_hkspi_disable = 0;
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// reg_hkspi_pll_ena =0;
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reg_hkspi_pll_ena =0;
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reg_debug_1 =0xBB;
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print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
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}
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@ -23,6 +23,7 @@ async def clock_redirect(dut):
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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error_margin = 0.1
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# calculate core clock
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await cocotb.start(calculate_clk_period(dut.uut.clock,"core clock"))
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await ClockCycles(caravelEnv.clk,110)
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@ -42,7 +43,7 @@ async def clock_redirect(dut):
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await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect
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await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
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await ClockCycles(caravelEnv.clk,110)
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if user_clock != core_clock:
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if abs(user_clock - core_clock) > (error_margin*core_clock):
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cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}")
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else:
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cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
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@ -60,7 +61,7 @@ async def clock_redirect(dut):
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await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect
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await cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name))
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await ClockCycles(caravelEnv.clk,110)
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if caravel_clock != core_clock:
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if abs(caravel_clock - core_clock) > error_margin*core_clock:
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cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}")
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else:
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cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
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@ -91,7 +92,7 @@ async def calculate_clk_period(clk,name):
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@cocotb.test()
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@repot_test
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async def hk_disable(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=3598)
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caravelEnv,clock = await test_configure(dut,timeout_cycles=12409)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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@ -28,11 +28,7 @@ async def IRQ_external(dut):
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phases_passes = 0
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reg1 =0 # buffer
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reg2 = 0 #buffer
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await ClockCycles(caravelEnv.clk,10)
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await write_reg_spi(caravelEnv,0x1c,1)
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await ClockCycles(caravelEnv.clk,10)
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cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}")
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while True:
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if reg2 != cpu.read_debug_reg2():
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@ -40,6 +36,8 @@ async def IRQ_external(dut):
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if reg2 == 0xFF: # test finish
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break
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if reg2 == 0xAA: # assert mprj 7
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await write_reg_spi(caravelEnv,0x1c,1)
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cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}")
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caravelEnv.drive_gpio_in((7,7),0)
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await ClockCycles(caravelEnv.clk,10)
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caravelEnv.drive_gpio_in((7,7),1)
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@ -80,12 +80,14 @@ async def spi_master_temp(dut):
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# second val
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for i in range(8):
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b = b + dut.bin35_monitor.value.binstr
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await RisingEdge(dut.bin32_monitor)
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if i != 7: # skip last cycle wait
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await RisingEdge(dut.bin32_monitor)
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cocotb.log.info (f" [TEST] b = {b} = {int(b,2)}")
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s = int(a,2) + int(b,2)
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s_bin = bin(s)[2:].zfill(8)
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cocotb.log.info (f" [TEST] sending sum of {int(a,2)} + {int(b,2)} = {s} = {s_bin}")
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await FallingEdge(dut.bin32_monitor)
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for i in range(8):
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dut.bin34_en.value = 1
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dut.bin34.value = int(s_bin[i],2) # bin
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@ -17,6 +17,7 @@
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#include <defs.h>
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#include <csr.h>
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#include <stub.c>
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// --------------------------------------------------------
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@ -17,6 +17,7 @@
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#include <defs.h>
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#include <csr.h>
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#include <stub.c>
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// --------------------------------------------------------
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@ -154,7 +154,11 @@ async def connect_5_6(dut,caravelEnv):
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async def uart_check_char_recieved_loopback(caravelEnv,cpu):
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# check cpu recieved the correct character
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while True:
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reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
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if not Macros['GL']:
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reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
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else:
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reg_uart_data = "1001110"
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reg1 = cpu.read_debug_reg1()
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cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
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if reg1 == 0x1B:
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