Update storage testbench to work with one 2K block

verilog/dv/caravel/defs.h

@@ -31,7 +31,6 @@ extern uint32_t flashio_worker_end;
 
 // Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
 #define reg_rw_block0  (*(volatile uint32_t*)0x01000000)
-#define reg_rw_block1  (*(volatile uint32_t*)0x01100000)
 #define reg_ro_block0  (*(volatile uint32_t*)0x02000000)
 
 // UART (0x2000_0000)

verilog/dv/caravel/mgmt_soc/storage/storage.c

@@ -69,15 +69,15 @@ void main()
 	
     reg_mprj_datal = 0xAB410000;
 	
-    // Test Management R/W block1
+    // Test Management R/W block0 > 1K address
     reg_mprj_datal = 0xA0200000;
-    for (i=0; i<10; i++){
-        ram_addr = &reg_rw_block1 + i;
+    for (i=256; i<10; i++){
+        ram_addr = &reg_rw_block0 + i;
         *ram_addr = i*5000 + 10000;
     }
 	
-    for (i=0; i<10; i++){
-        ram_addr = &reg_rw_block1 + i;
+    for (i=256; i<10; i++){
+        ram_addr = &reg_rw_block0 + i;
         if ((i*5000+10000) != *ram_addr) 
 	    reg_mprj_datal = 0xAB200000;
     }

verilog/rtl/caravel_netlists.v

@@ -35,7 +35,7 @@
 	`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
 	`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
 	`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
-	`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+	`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
     `else 
 	`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
 	`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
@@ -45,7 +45,7 @@
 	`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
 	`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
 	`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-	`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+	`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
     `endif 
 
     `ifdef GL

verilog/rtl/defines.v

@@ -50,7 +50,7 @@
 
 // not really parameterized but just to easily keep track of the number
 // of ram_block across different modules
-`define RAM_BLOCKS 2
+`define RAM_BLOCKS 1
 
 // Clock divisor default value
 `define CLK_DIV 3'b010