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Changed the memory map to move the 2e and 2f wishbone domains into 

the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
This commit is contained in:
Tim Edwards 2021-10-16 17:58:36 -04:00
parent 2f74fa83ee
commit 842200b7ec
3 changed files with 33 additions and 30 deletions
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47
doc/memory_map.txt
View File

@ -2,18 +2,20 @@ Caravel memory map vs. SPI register map
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
SPI register description signal memory map address SPI register description signal memory map address
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
00 SPI status (reserved) (undefined) 2e00_0000 00 SPI status (reserved) (undefined) 2610_0000
01 Manufacturer ID (high) mfgr_id[11:8] 2e00_0006 01 Manufacturer ID (high) mfgr_id[11:8] 2610_0006
02 Manufacturer ID (low) mfgr_id[7:0] 2e00_0005 02 Manufacturer ID (low) mfgr_id[7:0] 2610_0005
03 Product ID prod_id[7:0] 2e00_0004 03 Product ID prod_id[7:0] 2610_0004
04 User project ID mask_rev[31:24] 2e00_000b 04 User project ID mask_rev[31:24] 2610_000b
05 User project ID mask_rev[23:16] 2e00_000a 05 User project ID mask_rev[23:16] 2610_000a
06 User project ID mask_rev[15:8] 2e00_0009 06 User project ID mask_rev[15:8] 2610_0009
07 User project ID mask_rev[7:0] 2e00_0008 07 User project ID mask_rev[7:0] 2610_0008
08 CPU trap state trap 2e00_000c 08 CPU trap state trap 2610_000c
09 Power monitor usr1/2_vcc/vdd_pwrgood 2f00_0000
0a Output redirect clk1/clk2/trap_output_dest 2f00_0004 09 Power monitor usr1/2_vcc/vdd_pwrgood 2620_0000
0b Input redirect irq_8/7_inputsrc 2f00_000c 0a Output redirect clk1/clk2/trap_output_dest 2620_0004
0b Input redirect irq_8/7_inputsrc 2620_000c
0c GPIO[0] configure gpio_configure[0][12:8] 2600_0025 0c GPIO[0] configure gpio_configure[0][12:8] 2600_0025
0d GPIO[0] configure gpio_configure[0][7:0] 2600_0024 0d GPIO[0] configure gpio_configure[0][7:0] 2600_0024
0e GPIO[1] configure gpio_configure[1][12:8] 2600_0029 0e GPIO[1] configure gpio_configure[1][12:8] 2600_0029
@ -97,14 +99,15 @@ SPI register description signal memory map address
5c GPIO data mgmt_gpio_in[7:0] 2600_000c 5c GPIO data mgmt_gpio_in[7:0] 2600_000c
5d Power control pwr_ctrl_out[3:0] 2600_0004 5d Power control pwr_ctrl_out[3:0] 2600_0004
5e GPIO control serial_resetn/clock/data 2600_0000 5e GPIO control serial_resetn/clock/data 2600_0000
5f PLL enables pll_dco_ena, pll_ena 2e00_000c
60 PLL bypass pll_bypass 2e00_0010 5f PLL enables pll_dco_ena, pll_ena 2610_000c
61 IRQ irq 2e00_0014 60 PLL bypass pll_bypass 2610_0010
62 Reset reset 2e00_0018 61 IRQ irq 2610_0014
63 PLL trim pll_trim[31:24] 2e00_001f 62 Reset reset 2610_0018
64 PLL trim pll_trim[23:16] 2e00_001e 63 PLL trim pll_trim[31:24] 2610_001f
65 PLL trim pll_trim[15:8] 2e00_001d 64 PLL trim pll_trim[23:16] 2610_001e
66 PLL trim pll_trim[7:0] 2e00_001c 65 PLL trim pll_trim[15:8] 2610_001d
67 PLL source pll90_sel[2:0], pll_sel[2:0] 2e00_0020 66 PLL trim pll_trim[7:0] 2610_001c
68 PLL divider pll_div[4:0] 2e00_0024 67 PLL source pll90_sel[2:0], pll_sel[2:0] 2610_0020
68 PLL divider pll_div[4:0] 2610_0024
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------

12
verilog/dv/caravel/defs.h
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@ -66,7 +66,7 @@ extern uint32_t flashio_worker_end;
// User Project Control (0x2300_0000) // User Project Control (0x2300_0000)
#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000) #define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004) #define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
#define reg_mprj_irq (*(volatile uint32_t*)0x2e000014) #define reg_mprj_irq (*(volatile uint32_t*)0x26100014)
#define reg_mprj_datal (*(volatile uint32_t*)0x2600000c) #define reg_mprj_datal (*(volatile uint32_t*)0x2600000c)
#define reg_mprj_datah (*(volatile uint32_t*)0x26000010) #define reg_mprj_datah (*(volatile uint32_t*)0x26000010)
@ -163,11 +163,11 @@ extern uint32_t flashio_worker_end;
#define SPI_MASTER_IRQ_ENABLE 0x4000 #define SPI_MASTER_IRQ_ENABLE 0x4000
#define SPI_HOUSEKEEPING_CONN 0x8000 #define SPI_HOUSEKEEPING_CONN 0x8000
// System Area (0x2F00_0000) // System Area (0x2620_0000)
#define reg_power_good (*(volatile uint32_t*)0x2F000000) #define reg_power_good (*(volatile uint32_t*)0x26200000)
#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004) #define reg_clk_out_dest (*(volatile uint32_t*)0x26200004)
#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000004) #define reg_trap_out_dest (*(volatile uint32_t*)0x26200004)
#define reg_irq_source (*(volatile uint32_t*)0x2F00000C) #define reg_irq_source (*(volatile uint32_t*)0x2620000C)
// Bit fields for reg_power_good // Bit fields for reg_power_good
#define USER1_VCCD_POWER_GOOD 0x01 #define USER1_VCCD_POWER_GOOD 0x01

4
verilog/rtl/housekeeping.v
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@ -56,8 +56,8 @@
module housekeeping #( module housekeeping #(
parameter GPIO_BASE_ADR = 32'h2600_0000, parameter GPIO_BASE_ADR = 32'h2600_0000,
parameter SPI_BASE_ADR = 32'h2e00_0000, parameter SPI_BASE_ADR = 32'h2610_0000,
parameter SYS_BASE_ADR = 32'h2f00_0000, parameter SYS_BASE_ADR = 32'h2620_0000,
parameter IO_CTRL_BITS = 13 parameter IO_CTRL_BITS = 13
) ( ) (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS