mirror of https://github.com/efabless/caravel.git
[DATA] Add spare_logic_block
This commit is contained in:
manarabdelaty
parent
543fee18e3
commit
83e150bf25
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@ -0,0 +1,969 @@
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VERSION 5.8 ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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DESIGN spare_logic_block ;
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UNITS DISTANCE MICRONS 1000 ;
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DIEAREA ( 0 0 ) ( 45000 45000 ) ;
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ROW ROW_0 unithd 5520 5440 N DO 73 BY 1 STEP 460 0 ;
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ROW ROW_1 unithd 5520 8160 FS DO 73 BY 1 STEP 460 0 ;
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ROW ROW_2 unithd 5520 10880 N DO 73 BY 1 STEP 460 0 ;
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ROW ROW_3 unithd 5520 13600 FS DO 73 BY 1 STEP 460 0 ;
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ROW ROW_4 unithd 5520 16320 N DO 73 BY 1 STEP 460 0 ;
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ROW ROW_5 unithd 5520 19040 FS DO 73 BY 1 STEP 460 0 ;
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ROW ROW_6 unithd 5520 21760 N DO 73 BY 1 STEP 460 0 ;
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ROW ROW_7 unithd 5520 24480 FS DO 73 BY 1 STEP 460 0 ;
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ROW ROW_8 unithd 5520 27200 N DO 73 BY 1 STEP 460 0 ;
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ROW ROW_9 unithd 5520 29920 FS DO 73 BY 1 STEP 460 0 ;
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ROW ROW_10 unithd 5520 32640 N DO 73 BY 1 STEP 460 0 ;
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ROW ROW_11 unithd 5520 35360 FS DO 73 BY 1 STEP 460 0 ;
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TRACKS X 230 DO 98 STEP 460 LAYER li1 ;
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TRACKS Y 170 DO 132 STEP 340 LAYER li1 ;
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TRACKS X 170 DO 132 STEP 340 LAYER met1 ;
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TRACKS Y 170 DO 132 STEP 340 LAYER met1 ;
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TRACKS X 230 DO 98 STEP 460 LAYER met2 ;
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TRACKS Y 230 DO 98 STEP 460 LAYER met2 ;
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TRACKS X 340 DO 66 STEP 680 LAYER met3 ;
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TRACKS Y 340 DO 66 STEP 680 LAYER met3 ;
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TRACKS X 460 DO 49 STEP 920 LAYER met4 ;
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TRACKS Y 460 DO 49 STEP 920 LAYER met4 ;
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TRACKS X 1700 DO 13 STEP 3400 LAYER met5 ;
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TRACKS Y 1700 DO 13 STEP 3400 LAYER met5 ;
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GCELLGRID X 0 DO 6 STEP 6900 ;
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GCELLGRID Y 0 DO 7 STEP 6900 ;
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VIAS 4 ;
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- via4_1600x1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 400 400 400 ;
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- via_1600x480 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 55 165 + ROWCOL 1 5 ;
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- via2_1600x480 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 140 100 65 + ROWCOL 1 4 ;
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- via3_1600x480 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 100 60 100 140 + ROWCOL 1 4 ;
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END VIAS
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COMPONENTS 178 ;
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- FILLER_0_15 sky130_fd_sc_hd__decap_6 + PLACED ( 12420 5440 ) N ;
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- FILLER_0_24 sky130_fd_sc_hd__decap_4 + PLACED ( 16560 5440 ) N ;
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- FILLER_0_29 sky130_fd_sc_hd__fill_2 + PLACED ( 18860 5440 ) N ;
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- FILLER_0_3 sky130_fd_sc_hd__decap_12 + PLACED ( 6900 5440 ) N ;
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- FILLER_0_34 sky130_fd_sc_hd__decap_8 + PLACED ( 21160 5440 ) N ;
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- FILLER_0_42 sky130_fd_sc_hd__fill_2 + PLACED ( 24840 5440 ) N ;
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- FILLER_0_47 sky130_fd_sc_hd__decap_8 + PLACED ( 27140 5440 ) N ;
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- FILLER_0_55 sky130_fd_sc_hd__fill_1 + PLACED ( 30820 5440 ) N ;
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- FILLER_0_57 sky130_fd_sc_hd__decap_6 + PLACED ( 31740 5440 ) N ;
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- FILLER_0_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 5440 ) N ;
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- FILLER_10_14 sky130_fd_sc_hd__decap_4 + PLACED ( 11960 32640 ) N ;
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- FILLER_10_21 sky130_fd_sc_hd__decap_6 + PLACED ( 15180 32640 ) N ;
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- FILLER_10_27 sky130_fd_sc_hd__fill_1 + PLACED ( 17940 32640 ) N ;
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- FILLER_10_3 sky130_fd_sc_hd__fill_2 + PLACED ( 6900 32640 ) N ;
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- FILLER_10_34 sky130_fd_sc_hd__decap_12 + PLACED ( 21160 32640 ) N ;
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- FILLER_10_46 sky130_fd_sc_hd__decap_3 + PLACED ( 26680 32640 ) N ;
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- FILLER_10_52 sky130_fd_sc_hd__decap_4 + PLACED ( 29440 32640 ) N ;
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- FILLER_10_59 sky130_fd_sc_hd__decap_4 + PLACED ( 32660 32640 ) N ;
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- FILLER_10_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 32640 ) N ;
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- FILLER_11_15 sky130_fd_sc_hd__decap_12 + PLACED ( 12420 35360 ) FS ;
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- FILLER_11_27 sky130_fd_sc_hd__fill_1 + PLACED ( 17940 35360 ) FS ;
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- FILLER_11_29 sky130_fd_sc_hd__decap_12 + PLACED ( 18860 35360 ) FS ;
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- FILLER_11_3 sky130_fd_sc_hd__decap_12 + PLACED ( 6900 35360 ) FS ;
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- FILLER_11_41 sky130_fd_sc_hd__decap_12 + PLACED ( 24380 35360 ) FS ;
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- FILLER_11_53 sky130_fd_sc_hd__decap_3 + PLACED ( 29900 35360 ) FS ;
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- FILLER_11_57 sky130_fd_sc_hd__decap_6 + PLACED ( 31740 35360 ) FS ;
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- FILLER_11_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 35360 ) FS ;
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- FILLER_1_3 sky130_fd_sc_hd__fill_2 + PLACED ( 6900 8160 ) FS ;
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- FILLER_1_38 sky130_fd_sc_hd__decap_6 + PLACED ( 23000 8160 ) FS ;
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- FILLER_1_44 sky130_fd_sc_hd__fill_1 + PLACED ( 25760 8160 ) FS ;
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- FILLER_1_48 sky130_fd_sc_hd__decap_8 + PLACED ( 27600 8160 ) FS ;
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- FILLER_1_62 sky130_fd_sc_hd__decap_8 + PLACED ( 34040 8160 ) FS ;
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- FILLER_1_8 sky130_fd_sc_hd__decap_4 + PLACED ( 9200 8160 ) FS ;
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- FILLER_2_15 sky130_fd_sc_hd__decap_4 + PLACED ( 12420 10880 ) N ;
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- FILLER_2_22 sky130_fd_sc_hd__decap_6 + PLACED ( 15640 10880 ) N ;
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- FILLER_2_29 sky130_fd_sc_hd__decap_12 + PLACED ( 18860 10880 ) N ;
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- FILLER_2_3 sky130_fd_sc_hd__fill_2 + PLACED ( 6900 10880 ) N ;
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- FILLER_2_41 sky130_fd_sc_hd__decap_3 + PLACED ( 24380 10880 ) N ;
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- FILLER_2_47 sky130_fd_sc_hd__decap_4 + PLACED ( 27140 10880 ) N ;
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- FILLER_2_54 sky130_fd_sc_hd__decap_8 + PLACED ( 30360 10880 ) N ;
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- FILLER_2_62 sky130_fd_sc_hd__fill_1 + PLACED ( 34040 10880 ) N ;
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- FILLER_2_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 10880 ) N ;
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- FILLER_2_8 sky130_fd_sc_hd__decap_4 + PLACED ( 9200 10880 ) N ;
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- FILLER_3_3 sky130_fd_sc_hd__decap_6 + PLACED ( 6900 13600 ) FS ;
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- FILLER_3_35 sky130_fd_sc_hd__decap_12 + PLACED ( 21620 13600 ) FS ;
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- FILLER_3_47 sky130_fd_sc_hd__decap_8 + PLACED ( 27140 13600 ) FS ;
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- FILLER_3_55 sky130_fd_sc_hd__fill_1 + PLACED ( 30820 13600 ) FS ;
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- FILLER_3_57 sky130_fd_sc_hd__decap_6 + PLACED ( 31740 13600 ) FS ;
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- FILLER_3_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 13600 ) FS ;
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- FILLER_4_20 sky130_fd_sc_hd__decap_8 + PLACED ( 14720 16320 ) N ;
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- FILLER_4_29 sky130_fd_sc_hd__decap_12 + PLACED ( 18860 16320 ) N ;
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- FILLER_4_3 sky130_fd_sc_hd__fill_2 + PLACED ( 6900 16320 ) N ;
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- FILLER_4_41 sky130_fd_sc_hd__decap_12 + PLACED ( 24380 16320 ) N ;
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- FILLER_4_53 sky130_fd_sc_hd__decap_4 + PLACED ( 29900 16320 ) N ;
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- FILLER_4_57 sky130_fd_sc_hd__fill_1 + PLACED ( 31740 16320 ) N ;
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- FILLER_4_61 sky130_fd_sc_hd__decap_8 + PLACED ( 33580 16320 ) N ;
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- FILLER_4_69 sky130_fd_sc_hd__fill_1 + PLACED ( 37260 16320 ) N ;
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- FILLER_4_8 sky130_fd_sc_hd__decap_12 + PLACED ( 9200 16320 ) N ;
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- FILLER_5_12 sky130_fd_sc_hd__decap_4 + PLACED ( 11040 19040 ) FS ;
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- FILLER_5_19 sky130_fd_sc_hd__decap_12 + PLACED ( 14260 19040 ) FS ;
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- FILLER_5_31 sky130_fd_sc_hd__decap_12 + PLACED ( 19780 19040 ) FS ;
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- FILLER_5_43 sky130_fd_sc_hd__decap_6 + PLACED ( 25300 19040 ) FS ;
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- FILLER_5_52 sky130_fd_sc_hd__decap_4 + PLACED ( 29440 19040 ) FS ;
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- FILLER_5_57 sky130_fd_sc_hd__decap_4 + PLACED ( 31740 19040 ) FS ;
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- FILLER_5_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 19040 ) FS ;
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- FILLER_6_10 sky130_fd_sc_hd__decap_4 + PLACED ( 10120 21760 ) N ;
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- FILLER_6_17 sky130_fd_sc_hd__decap_8 + PLACED ( 13340 21760 ) N ;
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- FILLER_6_25 sky130_fd_sc_hd__decap_3 + PLACED ( 17020 21760 ) N ;
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- FILLER_6_29 sky130_fd_sc_hd__decap_12 + PLACED ( 18860 21760 ) N ;
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- FILLER_6_3 sky130_fd_sc_hd__decap_4 + PLACED ( 6900 21760 ) N ;
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- FILLER_6_41 sky130_fd_sc_hd__decap_12 + PLACED ( 24380 21760 ) N ;
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- FILLER_6_53 sky130_fd_sc_hd__decap_3 + PLACED ( 29900 21760 ) N ;
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- FILLER_6_59 sky130_fd_sc_hd__decap_4 + PLACED ( 32660 21760 ) N ;
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- FILLER_6_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 21760 ) N ;
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- FILLER_7_15 sky130_fd_sc_hd__decap_12 + PLACED ( 12420 24480 ) FS ;
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- FILLER_7_27 sky130_fd_sc_hd__decap_12 + PLACED ( 17940 24480 ) FS ;
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- FILLER_7_3 sky130_fd_sc_hd__decap_12 + PLACED ( 6900 24480 ) FS ;
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- FILLER_7_39 sky130_fd_sc_hd__decap_12 + PLACED ( 23460 24480 ) FS ;
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- FILLER_7_51 sky130_fd_sc_hd__decap_4 + PLACED ( 28980 24480 ) FS ;
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- FILLER_7_55 sky130_fd_sc_hd__fill_1 + PLACED ( 30820 24480 ) FS ;
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- FILLER_7_57 sky130_fd_sc_hd__fill_1 + PLACED ( 31740 24480 ) FS ;
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- FILLER_7_61 sky130_fd_sc_hd__decap_8 + PLACED ( 33580 24480 ) FS ;
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- FILLER_7_69 sky130_fd_sc_hd__fill_1 + PLACED ( 37260 24480 ) FS ;
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- FILLER_8_20 sky130_fd_sc_hd__decap_8 + PLACED ( 14720 27200 ) N ;
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- FILLER_8_29 sky130_fd_sc_hd__decap_12 + PLACED ( 18860 27200 ) N ;
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- FILLER_8_3 sky130_fd_sc_hd__fill_2 + PLACED ( 6900 27200 ) N ;
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- FILLER_8_41 sky130_fd_sc_hd__decap_12 + PLACED ( 24380 27200 ) N ;
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- FILLER_8_53 sky130_fd_sc_hd__decap_4 + PLACED ( 29900 27200 ) N ;
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- FILLER_8_66 sky130_fd_sc_hd__decap_4 + PLACED ( 35880 27200 ) N ;
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- FILLER_8_8 sky130_fd_sc_hd__decap_12 + PLACED ( 9200 27200 ) N ;
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- FILLER_9_16 sky130_fd_sc_hd__decap_4 + PLACED ( 12880 29920 ) FS ;
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- FILLER_9_20 sky130_fd_sc_hd__fill_1 + PLACED ( 14720 29920 ) FS ;
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- FILLER_9_24 sky130_fd_sc_hd__decap_12 + PLACED ( 16560 29920 ) FS ;
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- FILLER_9_3 sky130_fd_sc_hd__fill_1 + PLACED ( 6900 29920 ) FS ;
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- FILLER_9_36 sky130_fd_sc_hd__decap_12 + PLACED ( 22080 29920 ) FS ;
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- FILLER_9_48 sky130_fd_sc_hd__decap_8 + PLACED ( 27600 29920 ) FS ;
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- FILLER_9_57 sky130_fd_sc_hd__decap_3 + PLACED ( 31740 29920 ) FS ;
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- FILLER_9_63 sky130_fd_sc_hd__decap_6 + PLACED ( 34500 29920 ) FS ;
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- FILLER_9_69 sky130_fd_sc_hd__fill_1 + PLACED ( 37260 29920 ) FS ;
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- FILLER_9_9 sky130_fd_sc_hd__decap_4 + PLACED ( 9660 29920 ) FS ;
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- PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 5440 ) N ;
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- PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 5440 ) FN ;
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- PHY_10 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 19040 ) FS ;
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- PHY_11 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 19040 ) S ;
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- PHY_12 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 21760 ) N ;
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- PHY_13 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 21760 ) FN ;
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- PHY_14 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 24480 ) FS ;
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- PHY_15 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 24480 ) S ;
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- PHY_16 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 27200 ) N ;
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- PHY_17 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 27200 ) FN ;
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- PHY_18 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 29920 ) FS ;
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- PHY_19 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 29920 ) S ;
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- PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 8160 ) FS ;
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- PHY_20 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 32640 ) N ;
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- PHY_21 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 32640 ) FN ;
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- PHY_22 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 35360 ) FS ;
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- PHY_23 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 35360 ) S ;
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- PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 8160 ) S ;
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- PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 10880 ) N ;
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- PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 10880 ) FN ;
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- PHY_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 13600 ) FS ;
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- PHY_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 13600 ) S ;
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- PHY_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 16320 ) N ;
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- PHY_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 37720 16320 ) FN ;
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- TAP_24 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 5440 ) N ;
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- TAP_25 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 5440 ) N ;
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- TAP_26 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 8160 ) FS ;
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- TAP_27 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 10880 ) N ;
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- TAP_28 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 13600 ) FS ;
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- TAP_29 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 16320 ) N ;
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- TAP_30 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 19040 ) FS ;
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- TAP_31 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 21760 ) N ;
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- TAP_32 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 24480 ) FS ;
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- TAP_33 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 27200 ) N ;
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- TAP_34 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 29920 ) FS ;
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- TAP_35 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 32640 ) N ;
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- TAP_36 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 35360 ) FS ;
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- TAP_37 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 31280 35360 ) FS ;
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- spare_logic_biginv sky130_fd_sc_hd__inv_8 + PLACED ( 7820 32640 ) N ;
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- spare_logic_const\[0\] sky130_fd_sc_hd__conb_1 + PLACED ( 32200 16320 ) FN ;
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- spare_logic_const\[10\] sky130_fd_sc_hd__conb_1 + PLACED ( 11500 29920 ) S ;
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- spare_logic_const\[11\] sky130_fd_sc_hd__conb_1 + PLACED ( 34500 21760 ) FN ;
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- spare_logic_const\[12\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 27200 ) FN ;
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- spare_logic_const\[13\] sky130_fd_sc_hd__conb_1 + PLACED ( 34500 32640 ) FN ;
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- spare_logic_const\[14\] sky130_fd_sc_hd__conb_1 + PLACED ( 8740 21760 ) FN ;
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- spare_logic_const\[15\] sky130_fd_sc_hd__conb_1 + PLACED ( 32200 24480 ) S ;
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- spare_logic_const\[16\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 16320 ) FN ;
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- spare_logic_const\[17\] sky130_fd_sc_hd__conb_1 + PLACED ( 31280 21760 ) N ;
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- spare_logic_const\[18\] sky130_fd_sc_hd__conb_1 + PLACED ( 11960 21760 ) FN ;
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- spare_logic_const\[19\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 10880 ) FN ;
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- spare_logic_const\[1\] sky130_fd_sc_hd__conb_1 + PLACED ( 34500 5440 ) N ;
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- spare_logic_const\[20\] sky130_fd_sc_hd__conb_1 + PLACED ( 26220 8160 ) S ;
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- spare_logic_const\[21\] sky130_fd_sc_hd__conb_1 + PLACED ( 11040 10880 ) FN ;
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- spare_logic_const\[22\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 8160 ) S ;
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- spare_logic_const\[23\] sky130_fd_sc_hd__conb_1 + PLACED ( 14260 10880 ) FN ;
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- spare_logic_const\[24\] sky130_fd_sc_hd__conb_1 + PLACED ( 15180 5440 ) N ;
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- spare_logic_const\[25\] sky130_fd_sc_hd__conb_1 + PLACED ( 25760 10880 ) FN ;
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- spare_logic_const\[26\] sky130_fd_sc_hd__conb_1 + PLACED ( 19780 5440 ) FN ;
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- spare_logic_const\[2\] sky130_fd_sc_hd__conb_1 + PLACED ( 31280 32640 ) N ;
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- spare_logic_const\[3\] sky130_fd_sc_hd__conb_1 + PLACED ( 33120 29920 ) S ;
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- spare_logic_const\[4\] sky130_fd_sc_hd__conb_1 + PLACED ( 13800 32640 ) FN ;
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- spare_logic_const\[5\] sky130_fd_sc_hd__conb_1 + PLACED ( 15180 29920 ) FS ;
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- spare_logic_const\[6\] sky130_fd_sc_hd__conb_1 + PLACED ( 28980 10880 ) FN ;
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- spare_logic_const\[7\] sky130_fd_sc_hd__conb_1 + PLACED ( 12880 19040 ) S ;
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- spare_logic_const\[8\] sky130_fd_sc_hd__conb_1 + PLACED ( 25760 5440 ) FN ;
|
||||
- spare_logic_const\[9\] sky130_fd_sc_hd__conb_1 + PLACED ( 28060 19040 ) FS ;
|
||||
- spare_logic_flop\[0\] sky130_fd_sc_hd__dfbbp_1 + PLACED ( 9660 13600 ) FS ;
|
||||
- spare_logic_flop\[1\] sky130_fd_sc_hd__dfbbp_1 + PLACED ( 11040 8160 ) FS ;
|
||||
- spare_logic_inv\[0\] sky130_fd_sc_hd__inv_2 + PLACED ( 34500 10880 ) N ;
|
||||
- spare_logic_inv\[1\] sky130_fd_sc_hd__inv_2 + PLACED ( 34500 13600 ) S ;
|
||||
- spare_logic_inv\[2\] sky130_fd_sc_hd__inv_2 + PLACED ( 34500 35360 ) FS ;
|
||||
- spare_logic_inv\[3\] sky130_fd_sc_hd__inv_2 + PLACED ( 28060 32640 ) FN ;
|
||||
- spare_logic_mux\[0\] sky130_fd_sc_hd__mux2_2 + PLACED ( 31740 27200 ) FN ;
|
||||
- spare_logic_mux\[1\] sky130_fd_sc_hd__mux2_2 + PLACED ( 6900 19040 ) S ;
|
||||
- spare_logic_nand\[0\] sky130_fd_sc_hd__nand2_2 + PLACED ( 18860 32640 ) N ;
|
||||
- spare_logic_nand\[1\] sky130_fd_sc_hd__nand2_2 + PLACED ( 31740 8160 ) FS ;
|
||||
- spare_logic_nor\[0\] sky130_fd_sc_hd__nor2_2 + PLACED ( 33580 19040 ) S ;
|
||||
- spare_logic_nor\[1\] sky130_fd_sc_hd__nor2_2 + PLACED ( 7360 29920 ) S ;
|
||||
END COMPONENTS
|
||||
PINS 44 ;
|
||||
- spare_xfq[0] + NET spare_xfq[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 10540 ) N ;
|
||||
- spare_xfq[1] + NET spare_xfq[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 32430 2000 ) N ;
|
||||
- spare_xfqn[0] + NET spare_xfqn[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 22770 43000 ) N ;
|
||||
- spare_xfqn[1] + NET spare_xfqn[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 34340 ) N ;
|
||||
- spare_xi[0] + NET spare_xi[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 42090 2000 ) N ;
|
||||
- spare_xi[1] + NET spare_xi[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 340 ) N ;
|
||||
- spare_xi[2] + NET spare_xi[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 27540 ) N ;
|
||||
- spare_xi[3] + NET spare_xi[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 230 43000 ) N ;
|
||||
- spare_xib + NET spare_xib + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 37740 ) N ;
|
||||
- spare_xmx[0] + NET spare_xmx[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 35650 43000 ) N ;
|
||||
- spare_xmx[1] + NET spare_xmx[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 25990 2000 ) N ;
|
||||
- spare_xna[0] + NET spare_xna[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 34340 ) N ;
|
||||
- spare_xna[1] + NET spare_xna[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 7140 ) N ;
|
||||
- spare_xno[0] + NET spare_xno[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 6670 2000 ) N ;
|
||||
- spare_xno[1] + NET spare_xno[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 30940 ) N ;
|
||||
- spare_xz[0] + NET spare_xz[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 20740 ) N ;
|
||||
- spare_xz[10] + NET spare_xz[10] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 25990 43000 ) N ;
|
||||
- spare_xz[11] + NET spare_xz[11] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 38870 43000 ) N ;
|
||||
- spare_xz[12] + NET spare_xz[12] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 24140 ) N ;
|
||||
- spare_xz[13] + NET spare_xz[13] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 37740 ) N ;
|
||||
- spare_xz[14] + NET spare_xz[14] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 9890 43000 ) N ;
|
||||
- spare_xz[15] + NET spare_xz[15] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 230 2000 ) N ;
|
||||
- spare_xz[16] + NET spare_xz[16] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 7140 ) N ;
|
||||
- spare_xz[17] + NET spare_xz[17] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 24140 ) N ;
|
||||
- spare_xz[18] + NET spare_xz[18] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 3450 43000 ) N ;
|
||||
- spare_xz[19] + NET spare_xz[19] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 3740 ) N ;
|
||||
- spare_xz[1] + NET spare_xz[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 38870 2000 ) N ;
|
||||
- spare_xz[20] + NET spare_xz[20] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 29210 43000 ) N ;
|
||||
- spare_xz[21] + NET spare_xz[21] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 10540 ) N ;
|
||||
- spare_xz[22] + NET spare_xz[22] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 3450 2000 ) N ;
|
||||
- spare_xz[23] + NET spare_xz[23] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 13110 2000 ) N ;
|
||||
- spare_xz[24] + NET spare_xz[24] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 16330 2000 ) N ;
|
||||
- spare_xz[25] + NET spare_xz[25] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 13940 ) N ;
|
||||
- spare_xz[26] + NET spare_xz[26] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 19550 2000 ) N ;
|
||||
- spare_xz[2] + NET spare_xz[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 41140 ) N ;
|
||||
- spare_xz[3] + NET spare_xz[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 42090 43000 ) N ;
|
||||
- spare_xz[4] + NET spare_xz[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 13110 43000 ) N ;
|
||||
- spare_xz[5] + NET spare_xz[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 16330 43000 ) N ;
|
||||
- spare_xz[6] + NET spare_xz[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 29210 2000 ) N ;
|
||||
- spare_xz[7] + NET spare_xz[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 17340 ) N ;
|
||||
- spare_xz[8] + NET spare_xz[8] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 2000 44540 ) N ;
|
||||
- spare_xz[9] + NET spare_xz[9] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
|
||||
+ PLACED ( 43000 20740 ) N ;
|
||||
- vccd + NET vccd + SPECIAL + DIRECTION INPUT + USE POWER
|
||||
+ PORT
|
||||
+ LAYER met4 ( -800 -16560 ) ( 800 16560 )
|
||||
+ LAYER met4 ( -20800 -16560 ) ( -19200 16560 )
|
||||
+ LAYER met5 ( -21000 4640 ) ( 12580 6240 )
|
||||
+ LAYER met5 ( -21000 -15360 ) ( 12580 -13760 )
|
||||
+ FIXED ( 26520 21760 ) N ;
|
||||
- vssd + NET vssd + SPECIAL + DIRECTION INPUT + USE GROUND
|
||||
+ PORT
|
||||
+ LAYER met4 ( -800 -16560 ) ( 800 16560 )
|
||||
+ LAYER met4 ( -20800 -16560 ) ( -19200 16560 )
|
||||
+ LAYER met5 ( -31000 -5360 ) ( 2580 -3760 )
|
||||
+ FIXED ( 36520 21760 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- vccd ( PIN vccd ) ( * VPB ) ( * VPWR ) + USE POWER
|
||||
+ ROUTED met3 0 + SHAPE STRIPE ( 26520 35360 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 26520 35360 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 26520 35360 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 6520 35360 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 6520 35360 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 6520 35360 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 26520 29920 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 26520 29920 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 26520 29920 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 6520 29920 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 6520 29920 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 6520 29920 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 26520 24480 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 26520 24480 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 26520 24480 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 6520 24480 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 6520 24480 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 6520 24480 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 26520 19040 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 26520 19040 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 26520 19040 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 6520 19040 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 6520 19040 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 6520 19040 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 26520 13600 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 26520 13600 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 26520 13600 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 6520 13600 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 6520 13600 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 6520 13600 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 26520 8160 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 26520 8160 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 26520 8160 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 6520 8160 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 6520 8160 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 6520 8160 ) via_1600x480
|
||||
NEW met4 0 + SHAPE STRIPE ( 26520 27200 ) via4_1600x1600
|
||||
NEW met4 0 + SHAPE STRIPE ( 6520 27200 ) via4_1600x1600
|
||||
NEW met4 0 + SHAPE STRIPE ( 26520 7200 ) via4_1600x1600
|
||||
NEW met4 0 + SHAPE STRIPE ( 6520 7200 ) via4_1600x1600
|
||||
NEW met5 1600 + SHAPE STRIPE ( 5520 27200 ) ( 39100 27200 )
|
||||
NEW met5 1600 + SHAPE STRIPE ( 5520 7200 ) ( 39100 7200 )
|
||||
NEW met4 1600 + SHAPE STRIPE ( 26520 5200 ) ( 26520 38320 )
|
||||
NEW met4 1600 + SHAPE STRIPE ( 6520 5200 ) ( 6520 38320 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 35360 ) ( 39100 35360 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 29920 ) ( 39100 29920 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 24480 ) ( 39100 24480 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 19040 ) ( 39100 19040 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 13600 ) ( 39100 13600 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 8160 ) ( 39100 8160 ) ;
|
||||
- vssd ( PIN vssd ) ( * VNB ) ( * VGND ) + USE GROUND
|
||||
+ ROUTED met3 0 + SHAPE STRIPE ( 36520 38080 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 38080 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 38080 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 38080 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 38080 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 38080 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 36520 32640 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 32640 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 32640 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 32640 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 32640 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 32640 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 36520 27200 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 27200 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 27200 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 27200 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 27200 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 27200 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 36520 21760 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 21760 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 21760 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 21760 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 21760 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 21760 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 36520 16320 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 16320 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 16320 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 16320 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 16320 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 16320 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 36520 10880 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 10880 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 10880 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 10880 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 10880 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 10880 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 36520 5440 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 36520 5440 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 36520 5440 ) via_1600x480
|
||||
NEW met3 0 + SHAPE STRIPE ( 16520 5440 ) via3_1600x480
|
||||
NEW met2 0 + SHAPE STRIPE ( 16520 5440 ) via2_1600x480
|
||||
NEW met1 0 + SHAPE STRIPE ( 16520 5440 ) via_1600x480
|
||||
NEW met4 0 + SHAPE STRIPE ( 36520 17200 ) via4_1600x1600
|
||||
NEW met4 0 + SHAPE STRIPE ( 16520 17200 ) via4_1600x1600
|
||||
NEW met5 1600 + SHAPE STRIPE ( 5520 17200 ) ( 39100 17200 )
|
||||
NEW met4 1600 + SHAPE STRIPE ( 36520 5200 ) ( 36520 38320 )
|
||||
NEW met4 1600 + SHAPE STRIPE ( 16520 5200 ) ( 16520 38320 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 38080 ) ( 39100 38080 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 32640 ) ( 39100 32640 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 27200 ) ( 39100 27200 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 21760 ) ( 39100 21760 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 16320 ) ( 39100 16320 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 10880 ) ( 39100 10880 )
|
||||
NEW met1 480 + SHAPE FOLLOWPIN ( 5520 5440 ) ( 39100 5440 ) ;
|
||||
END SPECIALNETS
|
||||
NETS 69 ;
|
||||
- spare_logic1\[0\] ( spare_logic_const\[0\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[10\] ( spare_logic_const\[10\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[11\] ( spare_logic_const\[11\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[12\] ( spare_logic_const\[12\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[13\] ( spare_logic_const\[13\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[14\] ( spare_logic_const\[14\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[15\] ( spare_logic_const\[15\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[16\] ( spare_logic_const\[16\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[17\] ( spare_logic_const\[17\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[18\] ( spare_logic_const\[18\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[19\] ( spare_logic_const\[19\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[1\] ( spare_logic_const\[1\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[20\] ( spare_logic_const\[20\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[21\] ( spare_logic_const\[21\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[22\] ( spare_logic_const\[22\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[23\] ( spare_logic_const\[23\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[24\] ( spare_logic_const\[24\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[25\] ( spare_logic_const\[25\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[26\] ( spare_logic_const\[26\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[2\] ( spare_logic_const\[2\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[3\] ( spare_logic_const\[3\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[4\] ( spare_logic_const\[4\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[5\] ( spare_logic_const\[5\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[6\] ( spare_logic_const\[6\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[7\] ( spare_logic_const\[7\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[8\] ( spare_logic_const\[8\] HI ) + USE SIGNAL ;
|
||||
- spare_logic1\[9\] ( spare_logic_const\[9\] HI ) + USE SIGNAL ;
|
||||
- spare_xfq[0] ( PIN spare_xfq[0] ) ( spare_logic_flop\[0\] Q ) + USE SIGNAL
|
||||
+ ROUTED met3 ( 3220 10540 0 ) ( 10580 * )
|
||||
NEW met3 ( 10580 9860 ) ( * 10540 )
|
||||
NEW met3 ( 10580 9860 ) ( 20470 * )
|
||||
NEW met2 ( 20470 9860 ) ( 20930 * )
|
||||
NEW met2 ( 20930 9860 ) ( * 14110 )
|
||||
NEW met1 ( 20930 14110 ) ( 21390 * )
|
||||
NEW met2 ( 20470 9860 ) M2M3_PR_M
|
||||
NEW met1 ( 20930 14110 ) M1M2_PR
|
||||
NEW li1 ( 21390 14110 ) L1M1_PR_MR ;
|
||||
- spare_xfq[1] ( PIN spare_xfq[1] ) ( spare_logic_flop\[1\] Q ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 32430 3740 0 ) ( * 9010 )
|
||||
NEW met1 ( 22770 9010 ) ( 32430 * )
|
||||
NEW met1 ( 32430 9010 ) M1M2_PR
|
||||
NEW li1 ( 22770 9010 ) L1M1_PR_MR ;
|
||||
- spare_xfqn[0] ( PIN spare_xfqn[0] ) ( spare_logic_flop\[0\] Q_N ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 20010 15810 ) ( 22770 * )
|
||||
NEW met2 ( 22770 15810 ) ( * 41140 0 )
|
||||
NEW li1 ( 20010 15810 ) L1M1_PR_MR
|
||||
NEW met1 ( 22770 15810 ) M1M2_PR ;
|
||||
- spare_xfqn[1] ( PIN spare_xfqn[1] ) ( spare_logic_flop\[1\] Q_N ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 21390 9010 ) ( 21850 * )
|
||||
NEW met2 ( 21850 9010 ) ( * 33660 )
|
||||
NEW met3 ( 19780 33660 ) ( 21850 * )
|
||||
NEW met3 ( 19780 33660 ) ( * 34340 )
|
||||
NEW met3 ( 3220 34340 0 ) ( 19780 * )
|
||||
NEW li1 ( 21390 9010 ) L1M1_PR_MR
|
||||
NEW met1 ( 21850 9010 ) M1M2_PR
|
||||
NEW met2 ( 21850 33660 ) M2M3_PR_M ;
|
||||
- spare_xi[0] ( PIN spare_xi[0] ) ( spare_logic_inv\[0\] Y ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 42090 3740 0 ) ( * 11390 )
|
||||
NEW met1 ( 35190 11390 ) ( 42090 * )
|
||||
NEW met1 ( 42090 11390 ) M1M2_PR
|
||||
NEW li1 ( 35190 11390 ) L1M1_PR_MR ;
|
||||
- spare_xi[1] ( PIN spare_xi[1] ) ( spare_logic_inv\[1\] Y ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 35190 14110 ) ( 39790 * )
|
||||
NEW li1 ( 39790 510 ) ( * 14110 )
|
||||
NEW met2 ( 39790 340 ) ( * 510 )
|
||||
NEW met3 ( 39790 340 ) ( 41860 * 0 )
|
||||
NEW li1 ( 35190 14110 ) L1M1_PR_MR
|
||||
NEW li1 ( 39790 14110 ) L1M1_PR_MR
|
||||
NEW li1 ( 39790 510 ) L1M1_PR_MR
|
||||
NEW met1 ( 39790 510 ) M1M2_PR
|
||||
NEW met2 ( 39790 340 ) M2M3_PR_M
|
||||
NEW met1 ( 39790 510 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xi[2] ( PIN spare_xi[2] ) ( spare_logic_inv\[2\] Y ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 39790 27370 ) ( * 27540 )
|
||||
NEW met3 ( 39790 27540 ) ( 41860 * 0 )
|
||||
NEW met1 ( 35190 35870 ) ( 39790 * )
|
||||
NEW li1 ( 39790 27370 ) ( * 35870 )
|
||||
NEW li1 ( 39790 27370 ) L1M1_PR_MR
|
||||
NEW met1 ( 39790 27370 ) M1M2_PR
|
||||
NEW met2 ( 39790 27540 ) M2M3_PR_M
|
||||
NEW li1 ( 39790 35870 ) L1M1_PR_MR
|
||||
NEW li1 ( 35190 35870 ) L1M1_PR_MR
|
||||
NEW met1 ( 39790 27370 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xi[3] ( PIN spare_xi[3] ) ( spare_logic_inv\[3\] Y ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 28750 26690 ) ( * 33150 )
|
||||
NEW met1 ( 230 26690 ) ( 28750 * )
|
||||
NEW met2 ( 230 26690 ) ( * 41140 0 )
|
||||
NEW li1 ( 28750 33150 ) L1M1_PR_MR
|
||||
NEW met1 ( 28750 33150 ) M1M2_PR
|
||||
NEW met1 ( 28750 26690 ) M1M2_PR
|
||||
NEW met1 ( 230 26690 ) M1M2_PR
|
||||
NEW met1 ( 28750 33150 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xib ( PIN spare_xib ) ( spare_logic_biginv Y ) + USE SIGNAL
|
||||
+ ROUTED met3 ( 3220 37740 0 ) ( 8050 * )
|
||||
NEW met2 ( 8050 34170 ) ( * 37740 )
|
||||
NEW li1 ( 8050 34170 ) L1M1_PR_MR
|
||||
NEW met1 ( 8050 34170 ) M1M2_PR
|
||||
NEW met2 ( 8050 37740 ) M2M3_PR_M
|
||||
NEW met1 ( 8050 34170 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xmx[0] ( PIN spare_xmx[0] ) ( spare_logic_mux\[0\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 35190 39100 ) ( 35650 * )
|
||||
NEW met2 ( 35650 39100 ) ( * 41140 0 )
|
||||
NEW met2 ( 35190 29410 ) ( * 39100 )
|
||||
NEW li1 ( 35190 29410 ) L1M1_PR_MR
|
||||
NEW met1 ( 35190 29410 ) M1M2_PR
|
||||
NEW met1 ( 35190 29410 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xmx[1] ( PIN spare_xmx[1] ) ( spare_logic_mux\[1\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 25990 3740 0 ) ( * 7140 )
|
||||
NEW met2 ( 25070 7140 ) ( 25990 * )
|
||||
NEW met2 ( 25070 7140 ) ( * 19550 )
|
||||
NEW met1 ( 10350 19550 ) ( 25070 * )
|
||||
NEW met1 ( 25070 19550 ) M1M2_PR
|
||||
NEW li1 ( 10350 19550 ) L1M1_PR_MR ;
|
||||
- spare_xna[0] ( PIN spare_xna[0] ) ( spare_logic_nand\[0\] Y ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 20930 34170 ) ( * 34340 )
|
||||
NEW met3 ( 20930 34340 ) ( 41860 * 0 )
|
||||
NEW li1 ( 20930 34170 ) L1M1_PR_MR
|
||||
NEW met1 ( 20930 34170 ) M1M2_PR
|
||||
NEW met2 ( 20930 34340 ) M2M3_PR_M
|
||||
NEW met1 ( 20930 34170 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xna[1] ( PIN spare_xna[1] ) ( spare_logic_nand\[1\] Y ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 33810 7140 ) ( * 9350 )
|
||||
NEW met3 ( 33810 7140 ) ( 41860 * 0 )
|
||||
NEW met2 ( 33810 7140 ) M2M3_PR_M
|
||||
NEW li1 ( 33810 9350 ) L1M1_PR_MR
|
||||
NEW met1 ( 33810 9350 ) M1M2_PR
|
||||
NEW met1 ( 33810 9350 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xno[0] ( PIN spare_xno[0] ) ( spare_logic_nor\[0\] Y ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 6670 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 6210 4420 ) ( 6670 * )
|
||||
NEW met2 ( 6210 3740 ) ( * 4420 )
|
||||
NEW met2 ( 5290 3740 ) ( 6210 * )
|
||||
NEW met2 ( 5290 3740 ) ( * 19890 )
|
||||
NEW met1 ( 5290 19890 ) ( 34270 * )
|
||||
NEW met1 ( 5290 19890 ) M1M2_PR
|
||||
NEW li1 ( 34270 19890 ) L1M1_PR_MR ;
|
||||
- spare_xno[1] ( PIN spare_xno[1] ) ( spare_logic_nor\[1\] Y ) + USE SIGNAL
|
||||
+ ROUTED met3 ( 3220 30940 0 ) ( 7590 * )
|
||||
NEW met2 ( 7590 30940 ) ( * 31110 )
|
||||
NEW met2 ( 7590 30940 ) M2M3_PR_M
|
||||
NEW li1 ( 7590 31110 ) L1M1_PR_MR
|
||||
NEW met1 ( 7590 31110 ) M1M2_PR
|
||||
NEW met1 ( 7590 31110 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xz[0] ( PIN spare_xz[0] ) ( spare_logic_inv\[0\] A ) ( spare_logic_const\[0\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 32430 18530 ) ( * 20910 )
|
||||
NEW met1 ( 20470 20910 ) ( 32430 * )
|
||||
NEW met2 ( 20470 20740 ) ( * 20910 )
|
||||
NEW met3 ( 3220 20740 0 ) ( 20470 * )
|
||||
NEW met2 ( 32430 12070 ) ( * 18530 )
|
||||
NEW met1 ( 32430 12070 ) ( 34730 * )
|
||||
NEW li1 ( 32430 18530 ) L1M1_PR_MR
|
||||
NEW met1 ( 32430 18530 ) M1M2_PR
|
||||
NEW met1 ( 32430 20910 ) M1M2_PR
|
||||
NEW met1 ( 20470 20910 ) M1M2_PR
|
||||
NEW met2 ( 20470 20740 ) M2M3_PR_M
|
||||
NEW met1 ( 32430 12070 ) M1M2_PR
|
||||
NEW li1 ( 34730 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 32430 18530 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xz[10] ( PIN spare_xz[10] ) ( spare_logic_nor\[1\] A ) ( spare_logic_const\[10\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 11730 31110 ) ( 24150 * )
|
||||
NEW met1 ( 9430 31110 ) ( * 31450 )
|
||||
NEW met1 ( 9430 31110 ) ( 11730 * )
|
||||
NEW met2 ( 24150 41140 ) ( 25530 * )
|
||||
NEW met2 ( 25530 40460 ) ( * 41140 )
|
||||
NEW met2 ( 25530 40460 ) ( 25990 * )
|
||||
NEW met2 ( 25990 40460 ) ( * 41140 0 )
|
||||
NEW met2 ( 24150 31110 ) ( * 41140 )
|
||||
NEW li1 ( 11730 31110 ) L1M1_PR_MR
|
||||
NEW met1 ( 24150 31110 ) M1M2_PR
|
||||
NEW li1 ( 9430 31450 ) L1M1_PR_MR ;
|
||||
- spare_xz[11] ( PIN spare_xz[11] ) ( spare_logic_nor\[0\] B ) ( spare_logic_const\[11\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 34270 20570 ) ( * 20910 )
|
||||
NEW met1 ( 34730 23970 ) ( 38870 * )
|
||||
NEW met2 ( 34730 20910 ) ( * 23970 )
|
||||
NEW met1 ( 34270 20910 ) ( 34730 * )
|
||||
NEW met2 ( 38870 23970 ) ( * 41140 0 )
|
||||
NEW li1 ( 34270 20570 ) L1M1_PR_MR
|
||||
NEW li1 ( 34730 23970 ) L1M1_PR_MR
|
||||
NEW met1 ( 38870 23970 ) M1M2_PR
|
||||
NEW met1 ( 34730 20910 ) M1M2_PR
|
||||
NEW met1 ( 34730 23970 ) M1M2_PR
|
||||
NEW met1 ( 34730 23970 ) RECT ( 0 -70 595 70 ) ;
|
||||
- spare_xz[12] ( PIN spare_xz[12] ) ( spare_logic_nor\[1\] B ) ( spare_logic_const\[12\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 8050 25500 ) ( * 28390 )
|
||||
NEW met3 ( 5060 25500 ) ( 8050 * )
|
||||
NEW met3 ( 5060 24140 ) ( * 25500 )
|
||||
NEW met3 ( 3220 24140 0 ) ( 5060 * )
|
||||
NEW met2 ( 8050 28390 ) ( * 31450 )
|
||||
NEW li1 ( 8050 28390 ) L1M1_PR_MR
|
||||
NEW met1 ( 8050 28390 ) M1M2_PR
|
||||
NEW met2 ( 8050 25500 ) M2M3_PR_M
|
||||
NEW li1 ( 8050 31450 ) L1M1_PR_MR
|
||||
NEW met1 ( 8050 31450 ) M1M2_PR
|
||||
NEW met1 ( 8050 28390 ) RECT ( -355 -70 0 70 )
|
||||
NEW met1 ( 8050 31450 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xz[13] ( PIN spare_xz[13] ) ( spare_logic_mux\[0\] A0 ) ( spare_logic_const\[13\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 34270 28390 ) ( * 34170 )
|
||||
NEW met1 ( 33810 28390 ) ( 34270 * )
|
||||
NEW met2 ( 34270 34170 ) ( * 37060 )
|
||||
NEW met1 ( 34270 34170 ) ( 34730 * )
|
||||
NEW met3 ( 38180 37060 ) ( * 37740 )
|
||||
NEW met3 ( 38180 37740 ) ( 41860 * 0 )
|
||||
NEW met3 ( 34270 37060 ) ( 38180 * )
|
||||
NEW met1 ( 34270 34170 ) M1M2_PR
|
||||
NEW met1 ( 34270 28390 ) M1M2_PR
|
||||
NEW li1 ( 33810 28390 ) L1M1_PR_MR
|
||||
NEW met2 ( 34270 37060 ) M2M3_PR_M
|
||||
NEW li1 ( 34730 34170 ) L1M1_PR_MR ;
|
||||
- spare_xz[14] ( PIN spare_xz[14] ) ( spare_logic_mux\[1\] A0 ) ( spare_logic_const\[14\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 8970 23970 ) ( 9890 * )
|
||||
NEW met1 ( 8970 20570 ) ( 9890 * )
|
||||
NEW met2 ( 9890 20570 ) ( * 23970 )
|
||||
NEW met2 ( 9890 23970 ) ( * 41140 0 )
|
||||
NEW li1 ( 8970 23970 ) L1M1_PR_MR
|
||||
NEW met1 ( 9890 23970 ) M1M2_PR
|
||||
NEW li1 ( 8970 20570 ) L1M1_PR_MR
|
||||
NEW met1 ( 9890 20570 ) M1M2_PR ;
|
||||
- spare_xz[15] ( PIN spare_xz[15] ) ( spare_logic_mux\[0\] A1 ) ( spare_logic_const\[15\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 31970 24990 ) ( 32430 * )
|
||||
NEW met2 ( 31970 17850 ) ( * 24990 )
|
||||
NEW met1 ( 230 17850 ) ( 31970 * )
|
||||
NEW met2 ( 230 3740 0 ) ( * 17850 )
|
||||
NEW met1 ( 31970 27710 ) ( 32890 * )
|
||||
NEW met2 ( 31970 24990 ) ( * 27710 )
|
||||
NEW li1 ( 32430 24990 ) L1M1_PR_MR
|
||||
NEW met1 ( 31970 24990 ) M1M2_PR
|
||||
NEW met1 ( 31970 17850 ) M1M2_PR
|
||||
NEW met1 ( 230 17850 ) M1M2_PR
|
||||
NEW li1 ( 32890 27710 ) L1M1_PR_MR
|
||||
NEW met1 ( 31970 27710 ) M1M2_PR ;
|
||||
- spare_xz[16] ( PIN spare_xz[16] ) ( spare_logic_mux\[1\] A1 ) ( spare_logic_const\[16\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 8050 17510 ) ( 14490 * )
|
||||
NEW met2 ( 14490 7140 ) ( * 17510 )
|
||||
NEW met3 ( 3220 7140 0 ) ( 14490 * )
|
||||
NEW met1 ( 8050 20910 ) ( 14490 * )
|
||||
NEW met2 ( 14490 17510 ) ( * 20910 )
|
||||
NEW li1 ( 8050 17510 ) L1M1_PR_MR
|
||||
NEW met1 ( 14490 17510 ) M1M2_PR
|
||||
NEW met2 ( 14490 7140 ) M2M3_PR_M
|
||||
NEW li1 ( 8050 20910 ) L1M1_PR_MR
|
||||
NEW met1 ( 14490 20910 ) M1M2_PR ;
|
||||
- spare_xz[17] ( PIN spare_xz[17] ) ( spare_logic_mux\[0\] S ) ( spare_logic_const\[17\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 32430 23970 ) ( * 28050 )
|
||||
NEW met3 ( 32430 24140 ) ( 41860 * 0 )
|
||||
NEW li1 ( 32430 23970 ) L1M1_PR_MR
|
||||
NEW met1 ( 32430 23970 ) M1M2_PR
|
||||
NEW li1 ( 32430 28050 ) L1M1_PR_MR
|
||||
NEW met1 ( 32430 28050 ) M1M2_PR
|
||||
NEW met2 ( 32430 24140 ) M2M3_PR_M
|
||||
NEW met1 ( 32430 23970 ) RECT ( -355 -70 0 70 )
|
||||
NEW met1 ( 32430 28050 ) RECT ( -355 -70 0 70 )
|
||||
NEW met2 ( 32430 24140 ) RECT ( -70 -485 70 0 ) ;
|
||||
- spare_xz[18] ( PIN spare_xz[18] ) ( spare_logic_mux\[1\] S ) ( spare_logic_const\[18\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 3450 20910 ) ( 7590 * )
|
||||
NEW met1 ( 7590 22950 ) ( 12190 * )
|
||||
NEW met2 ( 7590 20910 ) ( * 22950 )
|
||||
NEW met2 ( 3450 20910 ) ( * 41140 0 )
|
||||
NEW li1 ( 7590 20910 ) L1M1_PR_MR
|
||||
NEW met1 ( 3450 20910 ) M1M2_PR
|
||||
NEW li1 ( 12190 22950 ) L1M1_PR_MR
|
||||
NEW met1 ( 7590 22950 ) M1M2_PR
|
||||
NEW met1 ( 7590 20910 ) M1M2_PR
|
||||
NEW met1 ( 7590 20910 ) RECT ( -595 -70 0 70 ) ;
|
||||
- spare_xz[19] ( PIN spare_xz[19] ) ( spare_logic_flop\[0\] D ) ( spare_logic_const\[19\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 8050 3740 ) ( * 12070 )
|
||||
NEW met3 ( 3220 3740 0 ) ( 8050 * )
|
||||
NEW met1 ( 8050 15130 ) ( 11730 * )
|
||||
NEW met2 ( 8050 12070 ) ( * 15130 )
|
||||
NEW li1 ( 8050 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 8050 12070 ) M1M2_PR
|
||||
NEW met2 ( 8050 3740 ) M2M3_PR_M
|
||||
NEW li1 ( 11730 15130 ) L1M1_PR_MR
|
||||
NEW met1 ( 8050 15130 ) M1M2_PR
|
||||
NEW met1 ( 8050 12070 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xz[1] ( PIN spare_xz[1] ) ( spare_logic_inv\[1\] A ) ( spare_logic_const\[1\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 35650 6970 ) ( 38870 * )
|
||||
NEW met2 ( 38870 3740 0 ) ( * 6970 )
|
||||
NEW met1 ( 35650 15130 ) ( 38870 * )
|
||||
NEW met2 ( 38870 6970 ) ( * 15130 )
|
||||
NEW li1 ( 35650 6970 ) L1M1_PR_MR
|
||||
NEW met1 ( 38870 6970 ) M1M2_PR
|
||||
NEW li1 ( 35650 15130 ) L1M1_PR_MR
|
||||
NEW met1 ( 38870 15130 ) M1M2_PR ;
|
||||
- spare_xz[20] ( PIN spare_xz[20] ) ( spare_logic_flop\[1\] D ) ( spare_logic_const\[20\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 24610 9350 ) ( 26450 * )
|
||||
NEW met2 ( 24610 9350 ) ( * 21250 )
|
||||
NEW met1 ( 24610 21250 ) ( 29210 * )
|
||||
NEW met1 ( 11730 9690 ) ( 13110 * )
|
||||
NEW met1 ( 11730 9690 ) ( * 10370 )
|
||||
NEW met1 ( 11730 10370 ) ( 24610 * )
|
||||
NEW met2 ( 29210 21250 ) ( * 41140 0 )
|
||||
NEW li1 ( 26450 9350 ) L1M1_PR_MR
|
||||
NEW met1 ( 24610 9350 ) M1M2_PR
|
||||
NEW met1 ( 24610 21250 ) M1M2_PR
|
||||
NEW met1 ( 29210 21250 ) M1M2_PR
|
||||
NEW li1 ( 13110 9690 ) L1M1_PR_MR
|
||||
NEW met1 ( 24610 10370 ) M1M2_PR
|
||||
NEW met2 ( 24610 10370 ) RECT ( -70 -485 70 0 ) ;
|
||||
- spare_xz[21] ( PIN spare_xz[21] ) ( spare_logic_flop\[0\] CLK ) ( spare_logic_const\[21\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 11270 12410 ) ( 21390 * )
|
||||
NEW met2 ( 21390 11900 ) ( * 12410 )
|
||||
NEW met2 ( 9890 12410 ) ( * 14790 )
|
||||
NEW met1 ( 9890 12410 ) ( 11270 * )
|
||||
NEW met3 ( 38180 10540 ) ( * 11900 )
|
||||
NEW met3 ( 38180 10540 ) ( 41860 * 0 )
|
||||
NEW met3 ( 21390 11900 ) ( 38180 * )
|
||||
NEW li1 ( 11270 12410 ) L1M1_PR_MR
|
||||
NEW met1 ( 21390 12410 ) M1M2_PR
|
||||
NEW met2 ( 21390 11900 ) M2M3_PR_M
|
||||
NEW li1 ( 9890 14790 ) L1M1_PR_MR
|
||||
NEW met1 ( 9890 14790 ) M1M2_PR
|
||||
NEW met1 ( 9890 12410 ) M1M2_PR
|
||||
NEW met1 ( 9890 14790 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xz[22] ( PIN spare_xz[22] ) ( spare_logic_flop\[1\] CLK ) ( spare_logic_const\[22\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 3450 8670 ) ( 8050 * )
|
||||
NEW met2 ( 3450 3740 0 ) ( * 8670 )
|
||||
NEW met1 ( 8050 9350 ) ( 11270 * )
|
||||
NEW met1 ( 8050 8670 ) ( * 9350 )
|
||||
NEW li1 ( 8050 8670 ) L1M1_PR_MR
|
||||
NEW met1 ( 3450 8670 ) M1M2_PR
|
||||
NEW li1 ( 11270 9350 ) L1M1_PR_MR ;
|
||||
- spare_xz[23] ( PIN spare_xz[23] ) ( spare_logic_flop\[0\] SET_B ) ( spare_logic_const\[23\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 14030 12070 ) ( 14490 * )
|
||||
NEW met2 ( 14030 11900 ) ( * 12070 )
|
||||
NEW met2 ( 13110 11900 ) ( 14030 * )
|
||||
NEW met2 ( 13110 3740 0 ) ( * 11900 )
|
||||
NEW met2 ( 14030 12070 ) ( * 15470 )
|
||||
NEW li1 ( 14490 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 14030 12070 ) M1M2_PR
|
||||
NEW met1 ( 14030 15470 ) M1M2_PR ;
|
||||
- spare_xz[24] ( PIN spare_xz[24] ) ( spare_logic_flop\[1\] SET_B ) ( spare_logic_const\[24\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 16330 7650 ) ( * 10030 )
|
||||
NEW met2 ( 16330 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 15410 4420 ) ( 16330 * )
|
||||
NEW met2 ( 15410 4420 ) ( * 6460 )
|
||||
NEW met2 ( 15410 6460 ) ( 16330 * )
|
||||
NEW met2 ( 16330 6460 ) ( * 7650 )
|
||||
NEW li1 ( 16330 7650 ) L1M1_PR_MR
|
||||
NEW met1 ( 16330 7650 ) M1M2_PR
|
||||
NEW met1 ( 16330 10030 ) M1M2_PR
|
||||
NEW met1 ( 16330 7650 ) RECT ( -355 -70 0 70 ) ;
|
||||
- spare_xz[25] ( PIN spare_xz[25] ) ( spare_logic_flop\[0\] RESET_B ) ( spare_logic_const\[25\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 25530 13090 ) ( 25990 * )
|
||||
NEW met2 ( 25530 13090 ) ( * 14620 )
|
||||
NEW met1 ( 19090 15130 ) ( 25530 * )
|
||||
NEW met2 ( 25530 14620 ) ( * 15130 )
|
||||
NEW met3 ( 25530 14620 ) ( 34500 * )
|
||||
NEW met3 ( 34500 13940 ) ( * 14620 )
|
||||
NEW met3 ( 34500 13940 ) ( 41860 * 0 )
|
||||
NEW li1 ( 25990 13090 ) L1M1_PR_MR
|
||||
NEW met1 ( 25530 13090 ) M1M2_PR
|
||||
NEW met2 ( 25530 14620 ) M2M3_PR_M
|
||||
NEW li1 ( 19090 15130 ) L1M1_PR_MR
|
||||
NEW met1 ( 25530 15130 ) M1M2_PR ;
|
||||
- spare_xz[26] ( PIN spare_xz[26] ) ( spare_logic_flop\[1\] RESET_B ) ( spare_logic_const\[26\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 19550 6970 ) ( 20010 * )
|
||||
NEW met2 ( 19550 3740 0 ) ( * 6970 )
|
||||
NEW met1 ( 19550 9690 ) ( 20470 * )
|
||||
NEW met2 ( 19550 6970 ) ( * 9690 )
|
||||
NEW li1 ( 20010 6970 ) L1M1_PR_MR
|
||||
NEW met1 ( 19550 6970 ) M1M2_PR
|
||||
NEW li1 ( 20470 9690 ) L1M1_PR_MR
|
||||
NEW met1 ( 19550 9690 ) M1M2_PR ;
|
||||
- spare_xz[2] ( PIN spare_xz[2] ) ( spare_logic_inv\[2\] A ) ( spare_logic_const\[2\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 32430 34850 ) ( * 36890 )
|
||||
NEW li1 ( 39790 36890 ) ( * 40970 )
|
||||
NEW met2 ( 39790 40970 ) ( * 41140 )
|
||||
NEW met3 ( 39790 41140 ) ( 41860 * 0 )
|
||||
NEW met1 ( 32430 36890 ) ( 39790 * )
|
||||
NEW li1 ( 32430 34850 ) L1M1_PR_MR
|
||||
NEW met1 ( 32430 34850 ) M1M2_PR
|
||||
NEW met1 ( 32430 36890 ) M1M2_PR
|
||||
NEW li1 ( 39790 36890 ) L1M1_PR_MR
|
||||
NEW li1 ( 39790 40970 ) L1M1_PR_MR
|
||||
NEW met1 ( 39790 40970 ) M1M2_PR
|
||||
NEW met2 ( 39790 41140 ) M2M3_PR_M
|
||||
NEW li1 ( 34730 36890 ) L1M1_PR_MR
|
||||
NEW met1 ( 32430 34850 ) RECT ( -355 -70 0 70 )
|
||||
NEW met1 ( 39790 40970 ) RECT ( -355 -70 0 70 )
|
||||
NEW met1 ( 34730 36890 ) RECT ( 0 -70 595 70 ) ;
|
||||
- spare_xz[3] ( PIN spare_xz[3] ) ( spare_logic_inv\[3\] A ) ( spare_logic_const\[3\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 34730 31450 ) ( * 33490 )
|
||||
NEW met1 ( 34730 33490 ) ( * 33830 )
|
||||
NEW met1 ( 33350 31450 ) ( 34730 * )
|
||||
NEW met1 ( 29210 33830 ) ( 42090 * )
|
||||
NEW met2 ( 42090 33830 ) ( * 41140 0 )
|
||||
NEW li1 ( 33350 31450 ) L1M1_PR_MR
|
||||
NEW li1 ( 29210 33830 ) L1M1_PR_MR
|
||||
NEW met1 ( 42090 33830 ) M1M2_PR
|
||||
NEW met1 ( 34730 31450 ) M1M2_PR
|
||||
NEW met1 ( 34730 33490 ) M1M2_PR ;
|
||||
- spare_xz[4] ( PIN spare_xz[4] ) ( spare_logic_const\[4\] LO ) ( spare_logic_biginv A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 11270 33830 ) ( 14030 * )
|
||||
NEW met2 ( 13110 33830 ) ( * 41140 0 )
|
||||
NEW li1 ( 14030 33830 ) L1M1_PR_MR
|
||||
NEW li1 ( 11270 33830 ) L1M1_PR_MR
|
||||
NEW met1 ( 13110 33830 ) M1M2_PR
|
||||
NEW met1 ( 13110 33830 ) RECT ( -595 -70 0 70 ) ;
|
||||
- spare_xz[5] ( PIN spare_xz[5] ) ( spare_logic_nand\[0\] A ) ( spare_logic_const\[5\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 15410 31450 ) ( 16330 * )
|
||||
NEW met1 ( 20010 33830 ) ( * 34170 )
|
||||
NEW met1 ( 15410 34170 ) ( 20010 * )
|
||||
NEW met2 ( 15410 39100 ) ( 16330 * )
|
||||
NEW met2 ( 16330 39100 ) ( * 41140 0 )
|
||||
NEW met2 ( 15410 31450 ) ( * 39100 )
|
||||
NEW li1 ( 16330 31450 ) L1M1_PR_MR
|
||||
NEW met1 ( 15410 31450 ) M1M2_PR
|
||||
NEW li1 ( 20010 33830 ) L1M1_PR_MR
|
||||
NEW met1 ( 15410 34170 ) M1M2_PR
|
||||
NEW met2 ( 15410 34170 ) RECT ( -70 -485 70 0 ) ;
|
||||
- spare_xz[6] ( PIN spare_xz[6] ) ( spare_logic_nand\[1\] A ) ( spare_logic_const\[6\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 29210 3740 0 ) ( * 12070 )
|
||||
NEW met1 ( 32890 9690 ) ( * 10030 )
|
||||
NEW met1 ( 29210 10030 ) ( 32890 * )
|
||||
NEW li1 ( 29210 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 29210 12070 ) M1M2_PR
|
||||
NEW li1 ( 32890 9690 ) L1M1_PR_MR
|
||||
NEW met1 ( 29210 10030 ) M1M2_PR
|
||||
NEW met1 ( 29210 12070 ) RECT ( -355 -70 0 70 )
|
||||
NEW met2 ( 29210 10030 ) RECT ( -70 -485 70 0 ) ;
|
||||
- spare_xz[7] ( PIN spare_xz[7] ) ( spare_logic_nand\[0\] B ) ( spare_logic_const\[7\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 13110 20570 ) ( 19090 * )
|
||||
NEW met2 ( 19090 20570 ) ( * 33830 )
|
||||
NEW met3 ( 3220 17340 0 ) ( 14030 * )
|
||||
NEW met2 ( 14030 17340 ) ( * 20570 )
|
||||
NEW li1 ( 13110 20570 ) L1M1_PR_MR
|
||||
NEW met1 ( 19090 20570 ) M1M2_PR
|
||||
NEW li1 ( 19090 33830 ) L1M1_PR_MR
|
||||
NEW met1 ( 19090 33830 ) M1M2_PR
|
||||
NEW met2 ( 14030 17340 ) M2M3_PR_M
|
||||
NEW met1 ( 14030 20570 ) M1M2_PR
|
||||
NEW met1 ( 19090 33830 ) RECT ( -355 -70 0 70 )
|
||||
NEW met1 ( 14030 20570 ) RECT ( -595 -70 0 70 ) ;
|
||||
- spare_xz[8] ( PIN spare_xz[8] ) ( spare_logic_nand\[1\] B ) ( spare_logic_const\[8\] LO ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 22310 7650 ) ( 25990 * )
|
||||
NEW met1 ( 22310 9690 ) ( 31970 * )
|
||||
NEW met2 ( 22310 7650 ) ( * 34500 )
|
||||
NEW met3 ( 3220 44540 0 ) ( 20470 * )
|
||||
NEW met2 ( 20470 44540 ) ( 21390 * )
|
||||
NEW met2 ( 21390 34500 ) ( * 44540 )
|
||||
NEW met2 ( 21390 34500 ) ( 22310 * )
|
||||
NEW li1 ( 25990 7650 ) L1M1_PR_MR
|
||||
NEW met1 ( 22310 7650 ) M1M2_PR
|
||||
NEW li1 ( 31970 9690 ) L1M1_PR_MR
|
||||
NEW met1 ( 22310 9690 ) M1M2_PR
|
||||
NEW met2 ( 20470 44540 ) M2M3_PR_M
|
||||
NEW met2 ( 22310 9690 ) RECT ( -70 -485 70 0 ) ;
|
||||
- spare_xz[9] ( PIN spare_xz[9] ) ( spare_logic_nor\[0\] A ) ( spare_logic_const\[9\] LO ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 35650 20570 ) ( * 20740 )
|
||||
NEW met3 ( 35650 20740 ) ( 41860 * 0 )
|
||||
NEW met1 ( 35650 20230 ) ( * 20570 )
|
||||
NEW met1 ( 29210 20230 ) ( 35650 * )
|
||||
NEW li1 ( 29210 20230 ) L1M1_PR_MR
|
||||
NEW li1 ( 35650 20570 ) L1M1_PR_MR
|
||||
NEW met1 ( 35650 20570 ) M1M2_PR
|
||||
NEW met2 ( 35650 20740 ) M2M3_PR_M
|
||||
NEW met1 ( 35650 20570 ) RECT ( -355 -70 0 70 ) ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
Binary file not shown.
|
|
@ -0,0 +1,440 @@
|
|||
VERSION 5.7 ;
|
||||
NOWIREEXTENSIONATPIN ON ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
MACRO spare_logic_block
|
||||
CLASS BLOCK ;
|
||||
FOREIGN spare_logic_block ;
|
||||
ORIGIN 0.000 0.000 ;
|
||||
SIZE 45.000 BY 45.000 ;
|
||||
PIN spare_xfq[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 10.240 4.000 10.840 ;
|
||||
END
|
||||
END spare_xfq[0]
|
||||
PIN spare_xfq[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 32.290 0.000 32.570 4.000 ;
|
||||
END
|
||||
END spare_xfq[1]
|
||||
PIN spare_xfqn[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 22.630 41.000 22.910 45.000 ;
|
||||
END
|
||||
END spare_xfqn[0]
|
||||
PIN spare_xfqn[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 34.040 4.000 34.640 ;
|
||||
END
|
||||
END spare_xfqn[1]
|
||||
PIN spare_xi[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 41.950 0.000 42.230 4.000 ;
|
||||
END
|
||||
END spare_xi[0]
|
||||
PIN spare_xi[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 0.040 45.000 0.640 ;
|
||||
END
|
||||
END spare_xi[1]
|
||||
PIN spare_xi[2]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 27.240 45.000 27.840 ;
|
||||
END
|
||||
END spare_xi[2]
|
||||
PIN spare_xi[3]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 0.090 41.000 0.370 45.000 ;
|
||||
END
|
||||
END spare_xi[3]
|
||||
PIN spare_xib
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 37.440 4.000 38.040 ;
|
||||
END
|
||||
END spare_xib
|
||||
PIN spare_xmx[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 35.510 41.000 35.790 45.000 ;
|
||||
END
|
||||
END spare_xmx[0]
|
||||
PIN spare_xmx[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 25.850 0.000 26.130 4.000 ;
|
||||
END
|
||||
END spare_xmx[1]
|
||||
PIN spare_xna[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 34.040 45.000 34.640 ;
|
||||
END
|
||||
END spare_xna[0]
|
||||
PIN spare_xna[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 6.840 45.000 7.440 ;
|
||||
END
|
||||
END spare_xna[1]
|
||||
PIN spare_xno[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 6.530 0.000 6.810 4.000 ;
|
||||
END
|
||||
END spare_xno[0]
|
||||
PIN spare_xno[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 30.640 4.000 31.240 ;
|
||||
END
|
||||
END spare_xno[1]
|
||||
PIN spare_xz[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 20.440 4.000 21.040 ;
|
||||
END
|
||||
END spare_xz[0]
|
||||
PIN spare_xz[10]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 25.850 41.000 26.130 45.000 ;
|
||||
END
|
||||
END spare_xz[10]
|
||||
PIN spare_xz[11]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 38.730 41.000 39.010 45.000 ;
|
||||
END
|
||||
END spare_xz[11]
|
||||
PIN spare_xz[12]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 23.840 4.000 24.440 ;
|
||||
END
|
||||
END spare_xz[12]
|
||||
PIN spare_xz[13]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 37.440 45.000 38.040 ;
|
||||
END
|
||||
END spare_xz[13]
|
||||
PIN spare_xz[14]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 9.750 41.000 10.030 45.000 ;
|
||||
END
|
||||
END spare_xz[14]
|
||||
PIN spare_xz[15]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 0.090 0.000 0.370 4.000 ;
|
||||
END
|
||||
END spare_xz[15]
|
||||
PIN spare_xz[16]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 6.840 4.000 7.440 ;
|
||||
END
|
||||
END spare_xz[16]
|
||||
PIN spare_xz[17]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 23.840 45.000 24.440 ;
|
||||
END
|
||||
END spare_xz[17]
|
||||
PIN spare_xz[18]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 3.310 41.000 3.590 45.000 ;
|
||||
END
|
||||
END spare_xz[18]
|
||||
PIN spare_xz[19]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 3.440 4.000 4.040 ;
|
||||
END
|
||||
END spare_xz[19]
|
||||
PIN spare_xz[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 38.730 0.000 39.010 4.000 ;
|
||||
END
|
||||
END spare_xz[1]
|
||||
PIN spare_xz[20]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 29.070 41.000 29.350 45.000 ;
|
||||
END
|
||||
END spare_xz[20]
|
||||
PIN spare_xz[21]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 10.240 45.000 10.840 ;
|
||||
END
|
||||
END spare_xz[21]
|
||||
PIN spare_xz[22]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 3.310 0.000 3.590 4.000 ;
|
||||
END
|
||||
END spare_xz[22]
|
||||
PIN spare_xz[23]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 12.970 0.000 13.250 4.000 ;
|
||||
END
|
||||
END spare_xz[23]
|
||||
PIN spare_xz[24]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 16.190 0.000 16.470 4.000 ;
|
||||
END
|
||||
END spare_xz[24]
|
||||
PIN spare_xz[25]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 13.640 45.000 14.240 ;
|
||||
END
|
||||
END spare_xz[25]
|
||||
PIN spare_xz[26]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 19.410 0.000 19.690 4.000 ;
|
||||
END
|
||||
END spare_xz[26]
|
||||
PIN spare_xz[2]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 40.840 45.000 41.440 ;
|
||||
END
|
||||
END spare_xz[2]
|
||||
PIN spare_xz[3]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 41.950 41.000 42.230 45.000 ;
|
||||
END
|
||||
END spare_xz[3]
|
||||
PIN spare_xz[4]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 12.970 41.000 13.250 45.000 ;
|
||||
END
|
||||
END spare_xz[4]
|
||||
PIN spare_xz[5]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 16.190 41.000 16.470 45.000 ;
|
||||
END
|
||||
END spare_xz[5]
|
||||
PIN spare_xz[6]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 29.070 0.000 29.350 4.000 ;
|
||||
END
|
||||
END spare_xz[6]
|
||||
PIN spare_xz[7]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 17.040 4.000 17.640 ;
|
||||
END
|
||||
END spare_xz[7]
|
||||
PIN spare_xz[8]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 0.000 44.240 4.000 44.840 ;
|
||||
END
|
||||
END spare_xz[8]
|
||||
PIN spare_xz[9]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 41.000 20.440 45.000 21.040 ;
|
||||
END
|
||||
END spare_xz[9]
|
||||
PIN vccd
|
||||
DIRECTION INPUT ;
|
||||
USE POWER ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 5.520 6.400 39.100 8.000 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 5.520 26.400 39.100 28.000 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 5.720 5.200 7.320 38.320 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 25.720 5.200 27.320 38.320 ;
|
||||
END
|
||||
END vccd
|
||||
PIN vssd
|
||||
DIRECTION INPUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 5.520 16.400 39.100 18.000 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 15.720 5.200 17.320 38.320 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 35.720 5.200 37.320 38.320 ;
|
||||
END
|
||||
END vssd
|
||||
OBS
|
||||
LAYER li1 ;
|
||||
RECT 5.520 0.425 39.875 41.055 ;
|
||||
LAYER met1 ;
|
||||
RECT 0.070 0.380 42.250 41.100 ;
|
||||
LAYER met2 ;
|
||||
RECT 0.650 40.720 3.030 44.725 ;
|
||||
RECT 3.870 40.720 9.470 44.725 ;
|
||||
RECT 10.310 40.720 12.690 44.725 ;
|
||||
RECT 13.530 40.720 15.910 44.725 ;
|
||||
RECT 16.750 40.720 22.350 44.725 ;
|
||||
RECT 23.190 40.720 25.570 44.725 ;
|
||||
RECT 26.410 40.720 28.790 44.725 ;
|
||||
RECT 29.630 40.720 35.230 44.725 ;
|
||||
RECT 36.070 40.720 38.450 44.725 ;
|
||||
RECT 39.290 40.720 41.670 44.725 ;
|
||||
RECT 0.100 4.280 42.220 40.720 ;
|
||||
RECT 0.650 0.155 3.030 4.280 ;
|
||||
RECT 3.870 0.155 6.250 4.280 ;
|
||||
RECT 7.090 0.155 12.690 4.280 ;
|
||||
RECT 13.530 0.155 15.910 4.280 ;
|
||||
RECT 16.750 0.155 19.130 4.280 ;
|
||||
RECT 19.970 0.155 25.570 4.280 ;
|
||||
RECT 26.410 0.155 28.790 4.280 ;
|
||||
RECT 29.630 0.155 32.010 4.280 ;
|
||||
RECT 32.850 0.155 38.450 4.280 ;
|
||||
RECT 39.290 0.155 41.670 4.280 ;
|
||||
LAYER met3 ;
|
||||
RECT 4.400 43.840 41.000 44.705 ;
|
||||
RECT 4.000 41.840 41.000 43.840 ;
|
||||
RECT 4.000 40.440 40.600 41.840 ;
|
||||
RECT 4.000 38.440 41.000 40.440 ;
|
||||
RECT 4.400 37.040 40.600 38.440 ;
|
||||
RECT 4.000 35.040 41.000 37.040 ;
|
||||
RECT 4.400 33.640 40.600 35.040 ;
|
||||
RECT 4.000 31.640 41.000 33.640 ;
|
||||
RECT 4.400 30.240 41.000 31.640 ;
|
||||
RECT 4.000 28.240 41.000 30.240 ;
|
||||
RECT 4.000 26.840 40.600 28.240 ;
|
||||
RECT 4.000 24.840 41.000 26.840 ;
|
||||
RECT 4.400 23.440 40.600 24.840 ;
|
||||
RECT 4.000 21.440 41.000 23.440 ;
|
||||
RECT 4.400 20.040 40.600 21.440 ;
|
||||
RECT 4.000 18.040 41.000 20.040 ;
|
||||
RECT 4.400 16.640 41.000 18.040 ;
|
||||
RECT 4.000 14.640 41.000 16.640 ;
|
||||
RECT 4.000 13.240 40.600 14.640 ;
|
||||
RECT 4.000 11.240 41.000 13.240 ;
|
||||
RECT 4.400 9.840 40.600 11.240 ;
|
||||
RECT 4.000 7.840 41.000 9.840 ;
|
||||
RECT 4.400 6.440 40.600 7.840 ;
|
||||
RECT 4.000 4.440 41.000 6.440 ;
|
||||
RECT 4.400 3.040 41.000 4.440 ;
|
||||
RECT 4.000 1.040 41.000 3.040 ;
|
||||
RECT 4.000 0.175 40.600 1.040 ;
|
||||
END
|
||||
END spare_logic_block
|
||||
END LIBRARY
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,219 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1637778834
|
||||
<< obsli1 >>
|
||||
rect 1104 85 7975 8211
|
||||
<< obsm1 >>
|
||||
rect 14 76 8450 8220
|
||||
<< metal2 >>
|
||||
rect 18 8200 74 9000
|
||||
rect 662 8200 718 9000
|
||||
rect 1950 8200 2006 9000
|
||||
rect 2594 8200 2650 9000
|
||||
rect 3238 8200 3294 9000
|
||||
rect 4526 8200 4582 9000
|
||||
rect 5170 8200 5226 9000
|
||||
rect 5814 8200 5870 9000
|
||||
rect 7102 8200 7158 9000
|
||||
rect 7746 8200 7802 9000
|
||||
rect 8390 8200 8446 9000
|
||||
rect 18 0 74 800
|
||||
rect 662 0 718 800
|
||||
rect 1306 0 1362 800
|
||||
rect 2594 0 2650 800
|
||||
rect 3238 0 3294 800
|
||||
rect 3882 0 3938 800
|
||||
rect 5170 0 5226 800
|
||||
rect 5814 0 5870 800
|
||||
rect 6458 0 6514 800
|
||||
rect 7746 0 7802 800
|
||||
rect 8390 0 8446 800
|
||||
<< obsm2 >>
|
||||
rect 130 8144 606 8945
|
||||
rect 774 8144 1894 8945
|
||||
rect 2062 8144 2538 8945
|
||||
rect 2706 8144 3182 8945
|
||||
rect 3350 8144 4470 8945
|
||||
rect 4638 8144 5114 8945
|
||||
rect 5282 8144 5758 8945
|
||||
rect 5926 8144 7046 8945
|
||||
rect 7214 8144 7690 8945
|
||||
rect 7858 8144 8334 8945
|
||||
rect 20 856 8444 8144
|
||||
rect 130 31 606 856
|
||||
rect 774 31 1250 856
|
||||
rect 1418 31 2538 856
|
||||
rect 2706 31 3182 856
|
||||
rect 3350 31 3826 856
|
||||
rect 3994 31 5114 856
|
||||
rect 5282 31 5758 856
|
||||
rect 5926 31 6402 856
|
||||
rect 6570 31 7690 856
|
||||
rect 7858 31 8334 856
|
||||
<< metal3 >>
|
||||
rect 0 8848 800 8968
|
||||
rect 8200 8168 9000 8288
|
||||
rect 0 7488 800 7608
|
||||
rect 8200 7488 9000 7608
|
||||
rect 0 6808 800 6928
|
||||
rect 8200 6808 9000 6928
|
||||
rect 0 6128 800 6248
|
||||
rect 8200 5448 9000 5568
|
||||
rect 0 4768 800 4888
|
||||
rect 8200 4768 9000 4888
|
||||
rect 0 4088 800 4208
|
||||
rect 8200 4088 9000 4208
|
||||
rect 0 3408 800 3528
|
||||
rect 8200 2728 9000 2848
|
||||
rect 0 2048 800 2168
|
||||
rect 8200 2048 9000 2168
|
||||
rect 0 1368 800 1488
|
||||
rect 8200 1368 9000 1488
|
||||
rect 0 688 800 808
|
||||
rect 8200 8 9000 128
|
||||
<< obsm3 >>
|
||||
rect 880 8768 8200 8941
|
||||
rect 800 8368 8200 8768
|
||||
rect 800 8088 8120 8368
|
||||
rect 800 7688 8200 8088
|
||||
rect 880 7408 8120 7688
|
||||
rect 800 7008 8200 7408
|
||||
rect 880 6728 8120 7008
|
||||
rect 800 6328 8200 6728
|
||||
rect 880 6048 8200 6328
|
||||
rect 800 5648 8200 6048
|
||||
rect 800 5368 8120 5648
|
||||
rect 800 4968 8200 5368
|
||||
rect 880 4688 8120 4968
|
||||
rect 800 4288 8200 4688
|
||||
rect 880 4008 8120 4288
|
||||
rect 800 3608 8200 4008
|
||||
rect 880 3328 8200 3608
|
||||
rect 800 2928 8200 3328
|
||||
rect 800 2648 8120 2928
|
||||
rect 800 2248 8200 2648
|
||||
rect 880 1968 8120 2248
|
||||
rect 800 1568 8200 1968
|
||||
rect 880 1288 8120 1568
|
||||
rect 800 888 8200 1288
|
||||
rect 880 608 8200 888
|
||||
rect 800 208 8200 608
|
||||
rect 800 35 8120 208
|
||||
<< metal4 >>
|
||||
rect 1144 1040 1464 7664
|
||||
rect 3144 1040 3464 7664
|
||||
rect 5144 1040 5464 7664
|
||||
rect 7144 1040 7464 7664
|
||||
<< metal5 >>
|
||||
rect 1104 5280 7820 5600
|
||||
rect 1104 3280 7820 3600
|
||||
rect 1104 1280 7820 1600
|
||||
<< labels >>
|
||||
rlabel metal3 s 0 2048 800 2168 6 spare_xfq[0]
|
||||
port 1 nsew signal output
|
||||
rlabel metal2 s 6458 0 6514 800 6 spare_xfq[1]
|
||||
port 2 nsew signal output
|
||||
rlabel metal2 s 4526 8200 4582 9000 6 spare_xfqn[0]
|
||||
port 3 nsew signal output
|
||||
rlabel metal3 s 0 6808 800 6928 6 spare_xfqn[1]
|
||||
port 4 nsew signal output
|
||||
rlabel metal2 s 8390 0 8446 800 6 spare_xi[0]
|
||||
port 5 nsew signal output
|
||||
rlabel metal3 s 8200 8 9000 128 6 spare_xi[1]
|
||||
port 6 nsew signal output
|
||||
rlabel metal3 s 8200 5448 9000 5568 6 spare_xi[2]
|
||||
port 7 nsew signal output
|
||||
rlabel metal2 s 18 8200 74 9000 6 spare_xi[3]
|
||||
port 8 nsew signal output
|
||||
rlabel metal3 s 0 7488 800 7608 6 spare_xib
|
||||
port 9 nsew signal output
|
||||
rlabel metal2 s 7102 8200 7158 9000 6 spare_xmx[0]
|
||||
port 10 nsew signal output
|
||||
rlabel metal2 s 5170 0 5226 800 6 spare_xmx[1]
|
||||
port 11 nsew signal output
|
||||
rlabel metal3 s 8200 6808 9000 6928 6 spare_xna[0]
|
||||
port 12 nsew signal output
|
||||
rlabel metal3 s 8200 1368 9000 1488 6 spare_xna[1]
|
||||
port 13 nsew signal output
|
||||
rlabel metal2 s 1306 0 1362 800 6 spare_xno[0]
|
||||
port 14 nsew signal output
|
||||
rlabel metal3 s 0 6128 800 6248 6 spare_xno[1]
|
||||
port 15 nsew signal output
|
||||
rlabel metal3 s 0 4088 800 4208 6 spare_xz[0]
|
||||
port 16 nsew signal output
|
||||
rlabel metal2 s 5170 8200 5226 9000 6 spare_xz[10]
|
||||
port 17 nsew signal output
|
||||
rlabel metal2 s 7746 8200 7802 9000 6 spare_xz[11]
|
||||
port 18 nsew signal output
|
||||
rlabel metal3 s 0 4768 800 4888 6 spare_xz[12]
|
||||
port 19 nsew signal output
|
||||
rlabel metal3 s 8200 7488 9000 7608 6 spare_xz[13]
|
||||
port 20 nsew signal output
|
||||
rlabel metal2 s 1950 8200 2006 9000 6 spare_xz[14]
|
||||
port 21 nsew signal output
|
||||
rlabel metal2 s 18 0 74 800 6 spare_xz[15]
|
||||
port 22 nsew signal output
|
||||
rlabel metal3 s 0 1368 800 1488 6 spare_xz[16]
|
||||
port 23 nsew signal output
|
||||
rlabel metal3 s 8200 4768 9000 4888 6 spare_xz[17]
|
||||
port 24 nsew signal output
|
||||
rlabel metal2 s 662 8200 718 9000 6 spare_xz[18]
|
||||
port 25 nsew signal output
|
||||
rlabel metal3 s 0 688 800 808 6 spare_xz[19]
|
||||
port 26 nsew signal output
|
||||
rlabel metal2 s 7746 0 7802 800 6 spare_xz[1]
|
||||
port 27 nsew signal output
|
||||
rlabel metal2 s 5814 8200 5870 9000 6 spare_xz[20]
|
||||
port 28 nsew signal output
|
||||
rlabel metal3 s 8200 2048 9000 2168 6 spare_xz[21]
|
||||
port 29 nsew signal output
|
||||
rlabel metal2 s 662 0 718 800 6 spare_xz[22]
|
||||
port 30 nsew signal output
|
||||
rlabel metal2 s 2594 0 2650 800 6 spare_xz[23]
|
||||
port 31 nsew signal output
|
||||
rlabel metal2 s 3238 0 3294 800 6 spare_xz[24]
|
||||
port 32 nsew signal output
|
||||
rlabel metal3 s 8200 2728 9000 2848 6 spare_xz[25]
|
||||
port 33 nsew signal output
|
||||
rlabel metal2 s 3882 0 3938 800 6 spare_xz[26]
|
||||
port 34 nsew signal output
|
||||
rlabel metal3 s 8200 8168 9000 8288 6 spare_xz[2]
|
||||
port 35 nsew signal output
|
||||
rlabel metal2 s 8390 8200 8446 9000 6 spare_xz[3]
|
||||
port 36 nsew signal output
|
||||
rlabel metal2 s 2594 8200 2650 9000 6 spare_xz[4]
|
||||
port 37 nsew signal output
|
||||
rlabel metal2 s 3238 8200 3294 9000 6 spare_xz[5]
|
||||
port 38 nsew signal output
|
||||
rlabel metal2 s 5814 0 5870 800 6 spare_xz[6]
|
||||
port 39 nsew signal output
|
||||
rlabel metal3 s 0 3408 800 3528 6 spare_xz[7]
|
||||
port 40 nsew signal output
|
||||
rlabel metal3 s 0 8848 800 8968 6 spare_xz[8]
|
||||
port 41 nsew signal output
|
||||
rlabel metal3 s 8200 4088 9000 4208 6 spare_xz[9]
|
||||
port 42 nsew signal output
|
||||
rlabel metal5 s 1104 1280 7820 1600 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s 1104 5280 7820 5600 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 1144 1040 1464 7664 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 5144 1040 5464 7664 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s 1104 3280 7820 3600 6 vssd
|
||||
port 44 nsew ground input
|
||||
rlabel metal4 s 3144 1040 3464 7664 6 vssd
|
||||
port 44 nsew ground input
|
||||
rlabel metal4 s 7144 1040 7464 7664 6 vssd
|
||||
port 44 nsew ground input
|
||||
<< properties >>
|
||||
string LEFclass BLOCK
|
||||
string FIXED_BBOX 0 0 9000 9000
|
||||
string LEFview TRUE
|
||||
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/spare_logic_block/runs/spare_logic_block/results/magic/spare_logic_block.gds
|
||||
string GDS_END 175312
|
||||
string GDS_START 71630
|
||||
<< end >>
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# This is an analog design. It will be designed by hand.
|
||||
# This is a placeholder to get things going.
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) spare_logic_block
|
||||
|
||||
set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/spare_logic_block.v
|
||||
|
||||
set ::env(VERILOG_FILES_BLACKBOX) $script_dir/../../verilog/stubs/sky130_fd_sc_hd__tapvpwrvgnd_1.v
|
||||
|
||||
set ::env(CLOCK_PORT) ""
|
||||
set ::env(CLOCK_TREE_SYNTH) 0
|
||||
|
||||
## Synthesis
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
set ::env(DIE_AREA) "0 0 45 45"
|
||||
|
||||
set ::env(TOP_MARGIN_MULT) "2"
|
||||
set ::env(BOTTOM_MARGIN_MULT) "2"
|
||||
set ::env(LEFT_MARGIN_MULT) "12"
|
||||
set ::env(RIGHT_MARGIN_MULT) "12"
|
||||
|
||||
## PDN
|
||||
set ::env(FP_PDN_AUTO_ADJUST) 0
|
||||
set ::env(FP_PDN_VOFFSET) 1
|
||||
set ::env(FP_PDN_HOFFSET) 2
|
||||
set ::env(FP_PDN_VPITCH) 20
|
||||
set ::env(FP_PDN_HPITCH) 20
|
||||
|
||||
set ::env(VDD_NETS) "vccd"
|
||||
set ::env(GND_NETS) "vssd"
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.45
|
||||
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
## Routing
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#N
|
||||
spare_xz.*
|
||||
|
||||
#S
|
||||
spare_xi.*
|
||||
spare_xna.*
|
||||
|
||||
#E
|
||||
spare_xno.*
|
||||
spare_xmx.*
|
||||
|
||||
#W
|
||||
spare_xfq.*
|
||||
|
|
@ -0,0 +1 @@
|
|||
openlane 2021.11.23_01.42.34
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
openlane cbb562bd43c5c410b1b498604803c3dd88a44856
|
||||
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
|
||||
open_pdks c5730b574461889c82858b08d12ba42423d9c2cb
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/home/ma/ef/caravel_openframe/openlane/spare_logic_block,spare_logic_block,spare_logic_block,flow_completed,0h0m57s,-1,39506.17283950618,0.002025,19753.08641975309,24.3,466.03,40,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1021,172,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,977964.0,12.24,11.05,8.12,0.0,0.0,0.0,10,96,10,96,0,0,0,40,0,0,0,0,0,0,0,4,-1,-1,-1,24,14,0,38,90.9090909090909,11.0,10.0,AREA 0,5,50,1,20,20,0.45,0.0,sky130_fd_sc_hd,4,3
|
||||
|
|
|
@ -0,0 +1,280 @@
|
|||
* NGSPICE file created from spare_logic_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nor2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nor2_2 A B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbp_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbp_1 CLK D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__mux2_2 A0 A1 S VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nand2_2 A B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_8 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
.subckt spare_logic_block spare_xfq[0] spare_xfq[1] spare_xfqn[0] spare_xfqn[1] spare_xi[0]
|
||||
+ spare_xi[1] spare_xi[2] spare_xi[3] spare_xib spare_xmx[0] spare_xmx[1] spare_xna[0]
|
||||
+ spare_xna[1] spare_xno[0] spare_xno[1] spare_xz[0] spare_xz[10] spare_xz[11] spare_xz[12]
|
||||
+ spare_xz[13] spare_xz[14] spare_xz[15] spare_xz[16] spare_xz[17] spare_xz[18] spare_xz[19]
|
||||
+ spare_xz[1] spare_xz[20] spare_xz[21] spare_xz[22] spare_xz[23] spare_xz[24] spare_xz[25]
|
||||
+ spare_xz[26] spare_xz[2] spare_xz[3] spare_xz[4] spare_xz[5] spare_xz[6] spare_xz[7]
|
||||
+ spare_xz[8] spare_xz[9] vccd vssd
|
||||
XFILLER_0_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
Xspare_logic_const\[8\] vssd vssd vccd vccd spare_logic_const\[8\]/HI spare_xz[8]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_3_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_3_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_0_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
Xspare_logic_nor\[0\] spare_xz[9] spare_xz[11] vssd vssd vccd vccd spare_xno[0] sky130_fd_sc_hd__nor2_2
|
||||
Xspare_logic_const\[22\] vssd vssd vccd vccd spare_logic_const\[22\]/HI spare_xz[22]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_3_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_9_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_0_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_3_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_6_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[15\] vssd vssd vccd vccd spare_logic_const\[15\]/HI spare_xz[15]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_6_59 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_11_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[6\] vssd vssd vccd vccd spare_logic_const\[6\]/HI spare_xz[6]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
Xspare_logic_const\[20\] vssd vssd vccd vccd spare_logic_const\[20\]/HI spare_xz[20]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_1_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_0_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_6_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[13\] vssd vssd vccd vccd spare_logic_const\[13\]/HI spare_xz[13]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_61 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_1_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_7_61 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_6_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[4\] vssd vssd vccd vccd spare_logic_const\[4\]/HI spare_xz[4]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_7_51 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_4_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_flop\[0\] spare_xz[21] spare_xz[19] spare_xz[25] spare_xz[23] vssd vssd
|
||||
+ vccd vccd spare_xfq[0] spare_xfqn[0] sky130_fd_sc_hd__dfbbp_1
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_mux\[1\] spare_xz[14] spare_xz[16] spare_xz[18] vssd vssd vccd vccd spare_xmx[1]
|
||||
+ sky130_fd_sc_hd__mux2_2
|
||||
Xspare_logic_const\[11\] vssd vssd vccd vccd spare_logic_const\[11\]/HI spare_xz[11]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_4_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[2\] vssd vssd vccd vccd spare_logic_const\[2\]/HI spare_xz[2]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_1_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_1_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[3\] spare_xz[3] vssd vssd vccd vccd spare_xi[3] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_10_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_7_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_10_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_4_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[0\] vssd vssd vccd vccd spare_logic_const\[0\]/HI spare_xz[0]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_7_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[1\] spare_xz[1] vssd vssd vccd vccd spare_xi[1] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_4_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_46 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_1_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_7_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[25\] vssd vssd vccd vccd spare_logic_const\[25\]/HI spare_xz[25]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_1_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
Xspare_logic_nand\[1\] spare_xz[6] spare_xz[8] vssd vssd vccd vccd spare_xna[1] sky130_fd_sc_hd__nand2_2
|
||||
XFILLER_6_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_7_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[18\] vssd vssd vccd vccd spare_logic_const\[18\]/HI spare_xz[18]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_10_59 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_7_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[9\] vssd vssd vccd vccd spare_logic_const\[9\]/HI spare_xz[9]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_8_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xspare_logic_nor\[1\] spare_xz[10] spare_xz[12] vssd vssd vccd vccd spare_xno[1] sky130_fd_sc_hd__nor2_2
|
||||
XFILLER_7_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[23\] vssd vssd vccd vccd spare_logic_const\[23\]/HI spare_xz[23]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_4_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_30 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_62 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xspare_logic_const\[16\] vssd vssd vccd vccd spare_logic_const\[16\]/HI spare_xz[16]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XTAP_31 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_32 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xspare_logic_const\[7\] vssd vssd vccd vccd spare_logic_const\[7\]/HI spare_xz[7]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_biginv spare_xz[4] vssd vssd vccd vccd spare_xib sky130_fd_sc_hd__inv_8
|
||||
XFILLER_8_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[21\] vssd vssd vccd vccd spare_logic_const\[21\]/HI spare_xz[21]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XTAP_33 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_54 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_11_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_2_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_8_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_8_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XTAP_34 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_43 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
Xspare_logic_const\[14\] vssd vssd vccd vccd spare_logic_const\[14\]/HI spare_xz[14]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_11_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_2_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_5_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_35 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xspare_logic_const\[5\] vssd vssd vccd vccd spare_logic_const\[5\]/HI spare_xz[5]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XTAP_24 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_4_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_8_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_36 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_25 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_11_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_flop\[1\] spare_xz[22] spare_xz[20] spare_xz[26] spare_xz[24] vssd vssd
|
||||
+ vccd vccd spare_xfq[1] spare_xfqn[1] sky130_fd_sc_hd__dfbbp_1
|
||||
XFILLER_5_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_37 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[12\] vssd vssd vccd vccd spare_logic_const\[12\]/HI spare_xz[12]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XTAP_26 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_27 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_11_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[3\] vssd vssd vccd vccd spare_logic_const\[3\]/HI spare_xz[3]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_2_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_28 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xspare_logic_mux\[0\] spare_xz[13] spare_xz[15] spare_xz[17] vssd vssd vccd vccd spare_xmx[0]
|
||||
+ sky130_fd_sc_hd__mux2_2
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_29 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_11_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[10\] vssd vssd vccd vccd spare_logic_const\[10\]/HI spare_xz[10]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_11_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_2_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[1\] vssd vssd vccd vccd spare_logic_const\[1\]/HI spare_xz[1]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[2\] spare_xz[2] vssd vssd vccd vccd spare_xi[2] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_8_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[26\] vssd vssd vccd vccd spare_logic_const\[26\]/HI spare_xz[26]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_11_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_7_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_0_42 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[19\] vssd vssd vccd vccd spare_logic_const\[19\]/HI spare_xz[19]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_63 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[0\] spare_xz[0] vssd vssd vccd vccd spare_xi[0] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_9_20 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_const\[24\] vssd vssd vccd vccd spare_logic_const\[24\]/HI spare_xz[24]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_6_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_nand\[0\] spare_xz[5] spare_xz[7] vssd vssd vccd vccd spare_xna[0] sky130_fd_sc_hd__nand2_2
|
||||
XFILLER_3_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_0_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_6_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_const\[17\] vssd vssd vccd vccd spare_logic_const\[17\]/HI spare_xz[17]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
.ends
|
||||
|
||||
|
|
@ -0,0 +1,830 @@
|
|||
module spare_logic_block (spare_xib,
|
||||
vccd,
|
||||
vssd,
|
||||
spare_xfq,
|
||||
spare_xfqn,
|
||||
spare_xi,
|
||||
spare_xmx,
|
||||
spare_xna,
|
||||
spare_xno,
|
||||
spare_xz);
|
||||
output spare_xib;
|
||||
input vccd;
|
||||
input vssd;
|
||||
output [1:0] spare_xfq;
|
||||
output [1:0] spare_xfqn;
|
||||
output [3:0] spare_xi;
|
||||
output [1:0] spare_xmx;
|
||||
output [1:0] spare_xna;
|
||||
output [1:0] spare_xno;
|
||||
output [26:0] spare_xz;
|
||||
|
||||
wire \spare_logic1[0] ;
|
||||
wire \spare_logic1[10] ;
|
||||
wire \spare_logic1[11] ;
|
||||
wire \spare_logic1[12] ;
|
||||
wire \spare_logic1[13] ;
|
||||
wire \spare_logic1[14] ;
|
||||
wire \spare_logic1[15] ;
|
||||
wire \spare_logic1[16] ;
|
||||
wire \spare_logic1[17] ;
|
||||
wire \spare_logic1[18] ;
|
||||
wire \spare_logic1[19] ;
|
||||
wire \spare_logic1[1] ;
|
||||
wire \spare_logic1[20] ;
|
||||
wire \spare_logic1[21] ;
|
||||
wire \spare_logic1[22] ;
|
||||
wire \spare_logic1[23] ;
|
||||
wire \spare_logic1[24] ;
|
||||
wire \spare_logic1[25] ;
|
||||
wire \spare_logic1[26] ;
|
||||
wire \spare_logic1[2] ;
|
||||
wire \spare_logic1[3] ;
|
||||
wire \spare_logic1[4] ;
|
||||
wire \spare_logic1[5] ;
|
||||
wire \spare_logic1[6] ;
|
||||
wire \spare_logic1[7] ;
|
||||
wire \spare_logic1[8] ;
|
||||
wire \spare_logic1[9] ;
|
||||
|
||||
sky130_fd_sc_hd__decap_6 FILLER_0_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_24 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_0_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_0_34 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_42 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_0_47 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_0_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_10_14 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_10_21 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_10_27 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_10_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_10_34 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_10_46 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_10_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_10_59 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_10_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_11_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_27 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_11_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_11_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_11_41 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_11_53 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_11_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_11_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_1_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_1_38 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_44 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_1_48 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_1_62 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_8 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_2_22 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_2_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_2_41 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_47 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_2_54 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_2_62 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_8 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_3_35 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_3_47 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_55 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_3_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_20 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_4_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_4_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_4_41 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_53 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_61 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_69 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_4_8 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_5_12 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_5_19 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_5_31 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_5_43 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_5_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_5_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_5_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_6_10 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_6_17 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_6_25 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_6_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_6_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_6_41 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_6_53 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_6_59 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_6_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_7_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_7_27 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_7_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_7_39 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_7_51 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_7_55 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_7_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_7_61 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_7_69 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_8_20 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_8_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_8_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_8_41 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_8_53 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_8_66 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_8_8 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_9_16 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_20 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_9_24 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_9_36 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_9_48 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_9_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_9_63 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_69 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_9_9 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_24 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_25 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_26 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_27 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_28 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_29 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_30 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_31 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_32 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_33 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_34 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_35 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_36 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_37 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__inv_8 spare_logic_biginv (.A(spare_xz[4]),
|
||||
.Y(spare_xib),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[0] (.HI(\spare_logic1[0] ),
|
||||
.LO(spare_xz[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[10] (.HI(\spare_logic1[10] ),
|
||||
.LO(spare_xz[10]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[11] (.HI(\spare_logic1[11] ),
|
||||
.LO(spare_xz[11]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[12] (.HI(\spare_logic1[12] ),
|
||||
.LO(spare_xz[12]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[13] (.HI(\spare_logic1[13] ),
|
||||
.LO(spare_xz[13]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[14] (.HI(\spare_logic1[14] ),
|
||||
.LO(spare_xz[14]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[15] (.HI(\spare_logic1[15] ),
|
||||
.LO(spare_xz[15]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[16] (.HI(\spare_logic1[16] ),
|
||||
.LO(spare_xz[16]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[17] (.HI(\spare_logic1[17] ),
|
||||
.LO(spare_xz[17]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[18] (.HI(\spare_logic1[18] ),
|
||||
.LO(spare_xz[18]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[19] (.HI(\spare_logic1[19] ),
|
||||
.LO(spare_xz[19]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[1] (.HI(\spare_logic1[1] ),
|
||||
.LO(spare_xz[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[20] (.HI(\spare_logic1[20] ),
|
||||
.LO(spare_xz[20]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[21] (.HI(\spare_logic1[21] ),
|
||||
.LO(spare_xz[21]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[22] (.HI(\spare_logic1[22] ),
|
||||
.LO(spare_xz[22]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[23] (.HI(\spare_logic1[23] ),
|
||||
.LO(spare_xz[23]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[24] (.HI(\spare_logic1[24] ),
|
||||
.LO(spare_xz[24]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[25] (.HI(\spare_logic1[25] ),
|
||||
.LO(spare_xz[25]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[26] (.HI(\spare_logic1[26] ),
|
||||
.LO(spare_xz[26]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[2] (.HI(\spare_logic1[2] ),
|
||||
.LO(spare_xz[2]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[3] (.HI(\spare_logic1[3] ),
|
||||
.LO(spare_xz[3]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[4] (.HI(\spare_logic1[4] ),
|
||||
.LO(spare_xz[4]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[5] (.HI(\spare_logic1[5] ),
|
||||
.LO(spare_xz[5]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[6] (.HI(\spare_logic1[6] ),
|
||||
.LO(spare_xz[6]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[7] (.HI(\spare_logic1[7] ),
|
||||
.LO(spare_xz[7]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[8] (.HI(\spare_logic1[8] ),
|
||||
.LO(spare_xz[8]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__conb_1 \spare_logic_const[9] (.HI(\spare_logic1[9] ),
|
||||
.LO(spare_xz[9]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__dfbbp_1 \spare_logic_flop[0] (.D(spare_xz[19]),
|
||||
.Q(spare_xfq[0]),
|
||||
.Q_N(spare_xfqn[0]),
|
||||
.RESET_B(spare_xz[25]),
|
||||
.SET_B(spare_xz[23]),
|
||||
.CLK(spare_xz[21]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__dfbbp_1 \spare_logic_flop[1] (.D(spare_xz[20]),
|
||||
.Q(spare_xfq[1]),
|
||||
.Q_N(spare_xfqn[1]),
|
||||
.RESET_B(spare_xz[26]),
|
||||
.SET_B(spare_xz[24]),
|
||||
.CLK(spare_xz[22]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__inv_2 \spare_logic_inv[0] (.A(spare_xz[0]),
|
||||
.Y(spare_xi[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__inv_2 \spare_logic_inv[1] (.A(spare_xz[1]),
|
||||
.Y(spare_xi[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__inv_2 \spare_logic_inv[2] (.A(spare_xz[2]),
|
||||
.Y(spare_xi[2]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__inv_2 \spare_logic_inv[3] (.A(spare_xz[3]),
|
||||
.Y(spare_xi[3]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__mux2_2 \spare_logic_mux[0] (.A0(spare_xz[13]),
|
||||
.A1(spare_xz[15]),
|
||||
.S(spare_xz[17]),
|
||||
.X(spare_xmx[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__mux2_2 \spare_logic_mux[1] (.A0(spare_xz[14]),
|
||||
.A1(spare_xz[16]),
|
||||
.S(spare_xz[18]),
|
||||
.X(spare_xmx[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__nand2_2 \spare_logic_nand[0] (.A(spare_xz[5]),
|
||||
.B(spare_xz[7]),
|
||||
.Y(spare_xna[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__nand2_2 \spare_logic_nand[1] (.A(spare_xz[6]),
|
||||
.B(spare_xz[8]),
|
||||
.Y(spare_xna[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__nor2_2 \spare_logic_nor[0] (.A(spare_xz[9]),
|
||||
.B(spare_xz[11]),
|
||||
.Y(spare_xno[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__nor2_2 \spare_logic_nor[1] (.A(spare_xz[10]),
|
||||
.B(spare_xz[12]),
|
||||
.Y(spare_xno[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
`default_nettype none
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020 The SkyWater PDK Authors
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* https://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
(* blackbox *)
|
||||
module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue