From 7b271a7808a81f51a21e1be78fff54a4596c1964 Mon Sep 17 00:00:00 2001 From: "R. Timothy Edwards" Date: Fri, 7 Oct 2022 12:28:13 -0400 Subject: [PATCH] Effectively reverted the change to add spare logic blocks near each (#157) * Effectively reverted the change to add spare logic blocks near each of the GPIO control blocks by changing the definition of NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks) for both caravel and caravan top level RTL verilog modules. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards --- manifest | 4 ++-- verilog/rtl/caravan.v | 3 ++- verilog/rtl/caravel.v | 3 ++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/manifest b/manifest index 6aa88057..0943d8f4 100644 --- a/manifest +++ b/manifest @@ -2,10 +2,10 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -220d7b7f62f07b3fbe88ea87699bf7cb24336ce5 verilog/rtl/caravan.v +f93c57988b0044d2bff4470a84b5eddc158f2094 verilog/rtl/caravan.v 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -2f166c83511062c0366af3f30870aab2ccfe1b25 verilog/rtl/caravel.v +b4b8fecbdc56c5d8acca9b904415f30e3159d1d5 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 99dc0946..58f353fe 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -1422,7 +1422,8 @@ module caravan ( ); /* Spare logic for metal mask fixes */ - `define NUM_SPARE_BLOCKS (`MPRJ_DIG_PADS+4) + // `define NUM_SPARE_BLOCKS (`MPRJ_DIG_PADS+4) + `define NUM_SPARE_BLOCKS 4 wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc; wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc; diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 9a00a234..a6477271 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -1474,7 +1474,8 @@ module caravel ( ); /* Spare logic for metal mask fixes */ - `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4) + // `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4) + `define NUM_SPARE_BLOCKS 4 wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc; wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;