mirror of https://github.com/efabless/caravel.git
update caravan STA logs
This commit is contained in:
Passant
parent
f17c51d73a
commit
7585faca28
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@ -61,13 +61,15 @@ if {\
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# -filter is supported by PT but not in the read_sdc
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# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
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# apply the constraint to hd cells at the ss corner on caravel/caravan
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if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
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set max_tran 1.5
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puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
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puts "For HD cells in the hierarchy of $::env(DESIGN)"
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set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
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set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
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}
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if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
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if { $::env(PROC_CORNER) == "s" } {
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set max_tran 1.5
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puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
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puts "For HD cells in the hierarchy of $::env(DESIGN)"
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set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
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set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
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}
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}
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}
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# Reading parasitics based on the RC corner specified
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@ -15756,9 +15758,9 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
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Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
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Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50' read successfully
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ff_1.95v_-40C.lib'
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ff_1.95v_-40C.lib'
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Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
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@ -15790,27 +15792,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
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Loading db file '/tmp/_pt1ryPnFoJ/1.db'
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Loading db file '/tmp/_pt1ruv9AsJ/1.db'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_-40C.lib'
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Loading db file '/tmp/_pt1ro9YQuB/1.db'
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Loading db file '/tmp/_pt1robnl5I/1.db'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_lowhv_5.5v_lv_1.95v_-40C.lib'
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Loading db file '/tmp/_pt1re6W1QL/1.db'
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Loading db file '/tmp/_pt1rwR5r00/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1ryo6lK2/1.db'
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Loading db file '/tmp/_pt1reCIotp/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1ro43sTR/1.db'
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Loading db file '/tmp/_pt1rQMaHam/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1ryiRyW7/1.db'
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Loading db file '/tmp/_pt1ry2cELJ/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1ri0G3Jv/1.db'
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Loading db file '/tmp/_pt1rYqnT8e/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1r0QG9iX/1.db'
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Loading db file '/tmp/_pt1rM8nqjO/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1raPzaEs/1.db'
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Loading db file '/tmp/_pt1r8RGcgr/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1rO7fAK1/1.db'
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Loading db file '/tmp/_pt1rofPZ07/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1rwGClCE/1.db'
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Loading db file '/tmp/_pt1rE24mAS/1.db'
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Linking design caravan...
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Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
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Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
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@ -16120,14 +16122,14 @@ Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeep
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Information: Inferring 1 clock-gating checks. (PTE-017)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16142,8 +16144,8 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28666_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28666_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28671_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28671_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28672_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28671_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28672_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28648_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28648_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16209,10 +16211,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1805/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1942/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1942/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1951/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1935/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1951/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1951/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1935/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1951/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1985/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1985/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1988/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16236,7 +16238,7 @@ Information: Number of nets evaluated in the previous iteration: 59945. (XTALK-1
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Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/max/caravan.ff.sdf
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Design : caravan
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Version: T-2022.03-SP3
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Date : Mon Oct 31 14:25:26 2022
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Date : Mon Oct 31 15:12:13 2022
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****************************************
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Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
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@ -16260,14 +16262,6 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_32040_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_32040_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__inv_8) soc/_13759_/A-->Y (min rising & falling negative_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16277,6 +16271,14 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16291,14 +16293,6 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_32040_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_32040_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__inv_8) soc/_13759_/A-->Y (max rising & falling negative_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16308,12 +16302,20 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.ff.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.ff_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.ff_test.db'
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
|
|
@ -16325,9 +16327,9 @@ RC-009 Warning 764 602
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 6 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2815.26 MB
|
||||
CPU usage for this session: 219 seconds
|
||||
Elapsed time for this session: 82 seconds
|
||||
Maximum memory usage for this session: 2805.27 MB
|
||||
CPU usage for this session: 210 seconds
|
||||
Elapsed time for this session: 79 seconds
|
||||
Diagnostics summary: 69 errors, 307 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -5133,25 +5135,25 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rNGb1Jg/1.db'
|
||||
Loading db file '/tmp/_pt1rEnCrpG/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ss_3.00v_100C.lib'
|
||||
Loading db file '/tmp/_pt1rjzRjNz/1.db'
|
||||
Loading db file '/tmp/_pt1rU5L1CW/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rZevlt7/1.db'
|
||||
Loading db file '/tmp/_pt1rolkGHr/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rljhMeK/1.db'
|
||||
Loading db file '/tmp/_pt1rSqj1S1/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rpGeMgr/1.db'
|
||||
Loading db file '/tmp/_pt1r6XfAjG/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rPneljc/1.db'
|
||||
Loading db file '/tmp/_pt1ryDVQJo/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rn5BJ70/1.db'
|
||||
Loading db file '/tmp/_pt1rCIzXUa/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rZR5AHT/1.db'
|
||||
Loading db file '/tmp/_pt1rIFWZQ0/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rZil12P/1.db'
|
||||
Loading db file '/tmp/_pt1roEVPyU/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rvS5MaQ/1.db'
|
||||
Loading db file '/tmp/_pt1rmkQC2R/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5458,21 +5460,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ss_1.40v_100C/sky130_fd_sc_hd__buf_12) soc/fanout1256/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ss_1.40v_100C/sky130_fd_sc_hd__buf_12) soc/fanout1256/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5483,7 +5485,7 @@ Information: Number of nets evaluated in the previous iteration: 59816. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/max/caravan.ss.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:21:30 2022
|
||||
Date : Mon Oct 31 15:08:19 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5510,7 +5512,7 @@ PARA-040 Warning 330243 329843
|
|||
LNK-043 Information 190193 190093
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2791.79 MB
|
||||
Maximum memory usage for this session: 2803.47 MB
|
||||
CPU usage for this session: 214 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 149 warnings, 124 informationals
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -5434,9 +5436,9 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5468,27 +5470,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rZumHxz/1.db'
|
||||
Loading db file '/tmp/_pt1rilSMDA/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rPYDkqy/1.db'
|
||||
Loading db file '/tmp/_pt1rELnyzy/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_lowhv_3.3v_lv_1.8v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rNU72PM/1.db'
|
||||
Loading db file '/tmp/_pt1r84fVZL/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rluViU6/1.db'
|
||||
Loading db file '/tmp/_pt1rKkR064/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rdGaFUu/1.db'
|
||||
Loading db file '/tmp/_pt1rQg0Gas/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rTyNEdX/1.db'
|
||||
Loading db file '/tmp/_pt1rEEv5uT/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rfisezt/1.db'
|
||||
Loading db file '/tmp/_pt1ruu87Qo/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rXpnPH3/1.db'
|
||||
Loading db file '/tmp/_pt1rWDzVZX/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rrv9JCH/1.db'
|
||||
Loading db file '/tmp/_pt1r4UVbUA/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rj0Q9kp/1.db'
|
||||
Loading db file '/tmp/_pt1rme3vBh/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1r9Az7Pa/1.db'
|
||||
Loading db file '/tmp/_pt1rElWl51/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5791,21 +5793,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5854,8 +5856,8 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1687/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1687/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1691/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1691/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1691/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1693/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1693/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5904,8 +5906,8 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1429/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1429/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
Information: Starting crosstalk aware timing iteration 2. (XTALK-001)
|
||||
|
|
@ -5914,7 +5916,7 @@ Information: Number of nets evaluated in the previous iteration: 59873. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/max/caravan.tt.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:17:46 2022
|
||||
Date : Mon Oct 31 15:04:35 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5936,14 +5938,14 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5956,20 +5958,20 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.tt.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.tt_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.tt_test.db'
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
|
|
@ -5981,7 +5983,7 @@ RC-009 Warning 426 286
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 6 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2824.04 MB
|
||||
Maximum memory usage for this session: 2809.49 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 285 warnings, 123 informationals
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -15756,8 +15758,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ff_1.95v_-40C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ff_1.95v_-40C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
|
|
@ -15790,27 +15792,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rkYD8gl/1.db'
|
||||
Loading db file '/tmp/_pt1rULyLka/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1re0zn1W/1.db'
|
||||
Loading db file '/tmp/_pt1rtZYvTf/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_lowhv_5.5v_lv_1.95v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rSFqTRR/1.db'
|
||||
Loading db file '/tmp/_pt1rIe3MPD/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rCYoQyT/1.db'
|
||||
Loading db file '/tmp/_pt1rh6vkk8/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rIVaUvv/1.db'
|
||||
Loading db file '/tmp/_pt1repR14a/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rMeJQzA/1.db'
|
||||
Loading db file '/tmp/_pt1rNSehJE/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rEwjciO/1.db'
|
||||
Loading db file '/tmp/_pt1rqtLr9f/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1riFULa6/1.db'
|
||||
Loading db file '/tmp/_pt1rPzvQmV/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rmHbjYr/1.db'
|
||||
Loading db file '/tmp/_pt1rO6rOoE/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1riRgcAR/1.db'
|
||||
Loading db file '/tmp/_pt1rbeYMgr/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1ricANZk/1.db'
|
||||
Loading db file '/tmp/_pt1rMhxnXh/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -16113,21 +16115,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16184,7 +16186,7 @@ Information: Number of nets evaluated in the previous iteration: 59920. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/min/caravan.ff.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:26:48 2022
|
||||
Date : Mon Oct 31 15:13:33 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -16218,9 +16220,9 @@ PARA-040 Warning 314319 313919
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2810.65 MB
|
||||
CPU usage for this session: 210 seconds
|
||||
Elapsed time for this session: 80 seconds
|
||||
Maximum memory usage for this session: 2812.17 MB
|
||||
CPU usage for this session: 208 seconds
|
||||
Elapsed time for this session: 78 seconds
|
||||
Diagnostics summary: 69 errors, 201 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -5099,9 +5101,9 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5133,25 +5135,25 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rJtALan/1.db'
|
||||
Loading db file '/tmp/_pt1reMpAam/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ss_3.00v_100C.lib'
|
||||
Loading db file '/tmp/_pt1rssQlYR/1.db'
|
||||
Loading db file '/tmp/_pt1rkWksWL/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rBcUNtB/1.db'
|
||||
Loading db file '/tmp/_pt1rKkzKqq/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rMu7e4p/1.db'
|
||||
Loading db file '/tmp/_pt1r4ujp19/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rbwmmWi/1.db'
|
||||
Loading db file '/tmp/_pt1rYxPhSX/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rATlWPf/1.db'
|
||||
Loading db file '/tmp/_pt1rKAdBJP/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rTAQiwg/1.db'
|
||||
Loading db file '/tmp/_pt1rGsXxmL/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1riW64Xk/1.db'
|
||||
Loading db file '/tmp/_pt1r6erDJK/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rHVREbt/1.db'
|
||||
Loading db file '/tmp/_pt1radDcRN/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rwgTebF/1.db'
|
||||
Loading db file '/tmp/_pt1rOnE2IU/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5458,21 +5460,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
Information: Starting crosstalk aware timing iteration 2. (XTALK-001)
|
||||
|
|
@ -5481,7 +5483,7 @@ Information: Number of nets evaluated in the previous iteration: 59811. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/min/caravan.ss.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:22:44 2022
|
||||
Date : Mon Oct 31 15:09:33 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5508,8 +5510,8 @@ PARA-040 Warning 314319 313919
|
|||
LNK-043 Information 190193 190093
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2803.89 MB
|
||||
CPU usage for this session: 212 seconds
|
||||
Maximum memory usage for this session: 2814.51 MB
|
||||
CPU usage for this session: 214 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 147 warnings, 124 informationals
|
||||
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -5435,8 +5437,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5468,27 +5470,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rDnnDbB/1.db'
|
||||
Loading db file '/tmp/_pt1rXg66Uu/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rQH8Z9K/1.db'
|
||||
Loading db file '/tmp/_pt1rWFivoE/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_lowhv_3.3v_lv_1.8v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rhqgsCa/1.db'
|
||||
Loading db file '/tmp/_pt1r3jnDs3/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rcrpoLF/1.db'
|
||||
Loading db file '/tmp/_pt1rQy6Lby/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rX4tySe/1.db'
|
||||
Loading db file '/tmp/_pt1rp7kaR6/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rQDi4hS/1.db'
|
||||
Loading db file '/tmp/_pt1ryzmvPJ/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rDxu5Jz/1.db'
|
||||
Loading db file '/tmp/_pt1rVyC4Nq/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1r20HB0k/1.db'
|
||||
Loading db file '/tmp/_pt1rm2aczb/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rVp1u49/1.db'
|
||||
Loading db file '/tmp/_pt1rNhI46Z/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1r2FZ7V2/1.db'
|
||||
Loading db file '/tmp/_pt1rm3NusS/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rvkQFzZ/1.db'
|
||||
Loading db file '/tmp/_pt1rBTekAO/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5791,18 +5793,18 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
|
|
@ -5820,7 +5822,7 @@ Information: Number of nets evaluated in the previous iteration: 59861. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/min/caravan.tt.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:19:00 2022
|
||||
Date : Mon Oct 31 15:05:49 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5882,9 +5884,9 @@ PARA-040 Warning 314319 313919
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2808.28 MB
|
||||
Maximum memory usage for this session: 2818.84 MB
|
||||
CPU usage for this session: 208 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Elapsed time for this session: 72 seconds
|
||||
Diagnostics summary: 69 errors, 187 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -15790,27 +15792,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rVUmlvH/1.db'
|
||||
Loading db file '/tmp/_pt1rDNmnFV/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rRMkhEm/1.db'
|
||||
Loading db file '/tmp/_pt1rrpdbJx/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_lowhv_5.5v_lv_1.95v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rPxjp1j/1.db'
|
||||
Loading db file '/tmp/_pt1rFFhD4r/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rdm3RVn/1.db'
|
||||
Loading db file '/tmp/_pt1rvZUTXs/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rJzc71Z/1.db'
|
||||
Loading db file '/tmp/_pt1r7YC3u2/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rv5Wn02/1.db'
|
||||
Loading db file '/tmp/_pt1rnYwC52/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rbeoDJd/1.db'
|
||||
Loading db file '/tmp/_pt1rBrSDpb/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1r7Lpzfs/1.db'
|
||||
Loading db file '/tmp/_pt1rjJGSvn/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rvuSCxK/1.db'
|
||||
Loading db file '/tmp/_pt1rHYMvnD/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1r9hWgB6/1.db'
|
||||
Loading db file '/tmp/_pt1rdhzT1W/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1r39vPrw/1.db'
|
||||
Loading db file '/tmp/_pt1rZaulsk/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -16113,21 +16115,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16236,7 +16238,7 @@ Information: Number of nets evaluated in the previous iteration: 59972. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/nom/caravan.ff.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:24:02 2022
|
||||
Date : Mon Oct 31 15:10:52 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -16305,9 +16307,9 @@ RC-009 Warning 277 135
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 6 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2795.19 MB
|
||||
CPU usage for this session: 209 seconds
|
||||
Elapsed time for this session: 79 seconds
|
||||
Maximum memory usage for this session: 2811.21 MB
|
||||
CPU usage for this session: 212 seconds
|
||||
Elapsed time for this session: 80 seconds
|
||||
Diagnostics summary: 69 errors, 287 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -5099,8 +5101,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
|
|
@ -5133,25 +5135,25 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rVpn8im/1.db'
|
||||
Loading db file '/tmp/_pt1rCYLdrB/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ss_3.00v_100C.lib'
|
||||
Loading db file '/tmp/_pt1rsbyvNC/1.db'
|
||||
Loading db file '/tmp/_pt1rToFvYN/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1r5A6j57/1.db'
|
||||
Loading db file '/tmp/_pt1ri3wW8e/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rm2f2sI/1.db'
|
||||
Loading db file '/tmp/_pt1rnW14mL/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rfOFH8m/1.db'
|
||||
Loading db file '/tmp/_pt1rwEWJPl/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1r82gUO5/1.db'
|
||||
Loading db file '/tmp/_pt1rJdyph0/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rxfTEgS/1.db'
|
||||
Loading db file '/tmp/_pt1ra7V8tI/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rmDrmuI/1.db'
|
||||
Loading db file '/tmp/_pt1rHn4Ktu/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1r91j0vC/1.db'
|
||||
Loading db file '/tmp/_pt1rUNvDhk/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rAgaFkA/1.db'
|
||||
Loading db file '/tmp/_pt1rhTGkTd/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5458,21 +5460,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
Information: Starting crosstalk aware timing iteration 2. (XTALK-001)
|
||||
|
|
@ -5481,7 +5483,7 @@ Information: Number of nets evaluated in the previous iteration: 59840. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/nom/caravan.ss.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:20:15 2022
|
||||
Date : Mon Oct 31 15:07:04 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5508,8 +5510,8 @@ PARA-040 Warning 321678 320929
|
|||
LNK-043 Information 190193 190093
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2825.96 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Maximum memory usage for this session: 2789.80 MB
|
||||
CPU usage for this session: 212 seconds
|
||||
Elapsed time for this session: 72 seconds
|
||||
Diagnostics summary: 69 errors, 147 warnings, 124 informationals
|
||||
|
||||
|
|
|
|||
|
|
@ -61,13 +61,15 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Reading parasitics based on the RC corner specified
|
||||
|
|
@ -5435,8 +5437,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5468,27 +5470,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rvSiYMa/1.db'
|
||||
Loading db file '/tmp/_pt1rUFrKpZ/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rKQPZe5/1.db'
|
||||
Loading db file '/tmp/_pt1rsw870N/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_lowhv_3.3v_lv_1.8v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rjxO5tf/1.db'
|
||||
Loading db file '/tmp/_pt1rKDA1cS/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rGdnLsv/1.db'
|
||||
Loading db file '/tmp/_pt1rgwre61/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rFkwdqP/1.db'
|
||||
Loading db file '/tmp/_pt1r4udcWf/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rwjYREd/1.db'
|
||||
Loading db file '/tmp/_pt1rgt3H2x/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rbwBbVF/1.db'
|
||||
Loading db file '/tmp/_pt1r4Hjv8T/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rudor5b/1.db'
|
||||
Loading db file '/tmp/_pt1rSfGH0j/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rhDCk7L/1.db'
|
||||
Loading db file '/tmp/_pt1rk4QEON/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rSU1T5p/1.db'
|
||||
Loading db file '/tmp/_pt1rKv5Ysl/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rBnT1V7/1.db'
|
||||
Loading db file '/tmp/_pt1rgXa4RW/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5791,21 +5793,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5874,7 +5876,7 @@ Information: Number of nets evaluated in the previous iteration: 59894. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/nom/caravan.tt.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Mon Oct 31 14:16:32 2022
|
||||
Date : Mon Oct 31 15:03:21 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5901,11 +5903,11 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
||||
Information: Elapsed time for model extraction: 3 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.tt.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.tt_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.tt_test.db'
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
|
|
@ -5916,8 +5918,8 @@ PARA-040 Warning 321678 320929
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2810.65 MB
|
||||
CPU usage for this session: 209 seconds
|
||||
Maximum memory usage for this session: 2800.46 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 221 warnings, 123 informationals
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue