From 7276623d3cd2b909e83a79f24968b5b547fcef86 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Wed, 5 Oct 2022 10:02:24 -0400 Subject: [PATCH] Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01). --- mag/caravan.mag | 2 +- mag/caravel.mag | 2 +- scripts/gen_gpio_defaults.py | 2 +- scripts/run_caravan_lvs_full.sh | 2 +- verilog/dv/caravel/defs.h | 8 +-- verilog/gl/caravan.v | 2 +- verilog/gl/caravel.v | 2 +- ...lock_0c01.v => gpio_defaults_block_0801.v} | 4 +- verilog/rtl/caravan.v | 26 ++++---- verilog/rtl/caravan_netlists.v | 1 + verilog/rtl/caravel.v | 26 ++++---- verilog/rtl/caravel_netlists.v | 1 + verilog/rtl/gpio_control_block.v | 43 ++++++++----- verilog/rtl/housekeeping.v | 64 +++++++------------ 14 files changed, 86 insertions(+), 99 deletions(-) rename verilog/gl/{gpio_defaults_block_0c01.v => gpio_defaults_block_0801.v} (98%) diff --git a/mag/caravan.mag b/mag/caravan.mag index dee363c2..5b2fd534 100644 --- a/mag/caravan.mag +++ b/mag/caravan.mag @@ -59054,7 +59054,7 @@ use gpio_defaults_block_0403 gpio_defaults_block_2 timestamp 1638587925 transform -1 0 709467 0 1 224200 box -38 0 6018 2224 -use gpio_defaults_block_0c01 gpio_defaults_block_3 +use gpio_defaults_block_0801 gpio_defaults_block_3 timestamp 1638587925 transform -1 0 709467 0 1 269400 box -38 0 6018 2224 diff --git a/mag/caravel.mag b/mag/caravel.mag index 17bec0c0..fb2cc8bc 100644 --- a/mag/caravel.mag +++ b/mag/caravel.mag @@ -73894,7 +73894,7 @@ use gpio_defaults_block_0403 gpio_defaults_block_2 timestamp 1638587925 transform -1 0 709467 0 1 224200 box -38 0 6018 2224 -use gpio_defaults_block_0c01 gpio_defaults_block_3 +use gpio_defaults_block_0801 gpio_defaults_block_3 timestamp 1638587925 transform -1 0 709467 0 1 269400 box -38 0 6018 2224 diff --git a/scripts/gen_gpio_defaults.py b/scripts/gen_gpio_defaults.py index bf96ce84..28e55d28 100755 --- a/scripts/gen_gpio_defaults.py +++ b/scripts/gen_gpio_defaults.py @@ -172,7 +172,7 @@ if __name__ == '__main__': kvpairs["`USER_CONFIG_GPIO_0_INIT"] = "13'h1803" kvpairs["`USER_CONFIG_GPIO_1_INIT"] = "13'h1803" kvpairs["`USER_CONFIG_GPIO_2_INIT"] = "13'h0403" - kvpairs["`USER_CONFIG_GPIO_3_INIT"] = "13'h0c01" + kvpairs["`USER_CONFIG_GPIO_3_INIT"] = "13'h0801" kvpairs["`USER_CONFIG_GPIO_4_INIT"] = "13'h0403" # Generate zero and one coordinates for each via diff --git a/scripts/run_caravan_lvs_full.sh b/scripts/run_caravan_lvs_full.sh index 4f61d569..c7111990 100755 --- a/scripts/run_caravan_lvs_full.sh +++ b/scripts/run_caravan_lvs_full.sh @@ -78,7 +78,7 @@ readnet verilog ../verilog/gl/digital_pll.v \$circuit2 readnet verilog ../verilog/gl/gpio_control_block.v \$circuit2 readnet verilog ../verilog/gl/gpio_defaults_block.v \$circuit2 readnet verilog ../verilog/gl/gpio_defaults_block_1803.v \$circuit2 -readnet verilog ../verilog/gl/gpio_defaults_block_0c01.v \$circuit2 +readnet verilog ../verilog/gl/gpio_defaults_block_0801.v \$circuit2 readnet verilog ../verilog/gl/gpio_defaults_block_0403.v \$circuit2 readnet verilog ../verilog/gl/gpio_logic_high.v \$circuit2 readnet verilog ../verilog/gl/housekeeping.v \$circuit2 diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h index 3ed82a49..bebab837 100644 --- a/verilog/dv/caravel/defs.h +++ b/verilog/dv/caravel/defs.h @@ -216,15 +216,15 @@ extern uint32_t flashio_worker_end; // Useful GPIO mode values #define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403 -#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0801 -#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c01 +#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0c01 +#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0801 #define GPIO_MODE_MGMT_STD_OUTPUT 0x1809 #define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801 #define GPIO_MODE_MGMT_STD_ANALOG 0x000b #define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402 -#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0800 -#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c00 +#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0c00 +#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0800 #define GPIO_MODE_USER_STD_OUTPUT 0x1808 #define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800 #define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802 diff --git a/verilog/gl/caravan.v b/verilog/gl/caravan.v index 3b9d3606..c944de16 100644 --- a/verilog/gl/caravan.v +++ b/verilog/gl/caravan.v @@ -3862,7 +3862,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd .VPWR(vccd_core), .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] }) ); - gpio_defaults_block_0c01 gpio_defaults_block_3 ( + gpio_defaults_block_0801 gpio_defaults_block_3 ( .VGND(vssd_core), .VPWR(vccd_core), .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] }) diff --git a/verilog/gl/caravel.v b/verilog/gl/caravel.v index 7402bb6f..68a8e0fa 100644 --- a/verilog/gl/caravel.v +++ b/verilog/gl/caravel.v @@ -4608,7 +4608,7 @@ module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd .VPWR(vccd_core), .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] }) ); - gpio_defaults_block_0c01 gpio_defaults_block_3 ( + gpio_defaults_block_0801 gpio_defaults_block_3 ( .VGND(vssd_core), .VPWR(vccd_core), .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] }) diff --git a/verilog/gl/gpio_defaults_block_0c01.v b/verilog/gl/gpio_defaults_block_0801.v similarity index 98% rename from verilog/gl/gpio_defaults_block_0c01.v rename to verilog/gl/gpio_defaults_block_0801.v index 0bcca4a4..379ba1c9 100644 --- a/verilog/gl/gpio_defaults_block_0c01.v +++ b/verilog/gl/gpio_defaults_block_0801.v @@ -1,4 +1,4 @@ -module gpio_defaults_block_0403 (VGND, +module gpio_defaults_block_0801 (VGND, VPWR, gpio_defaults); input VGND; @@ -254,7 +254,7 @@ module gpio_defaults_block_0403 (VGND, assign gpio_defaults[7] = \gpio_defaults_low[7] ; assign gpio_defaults[8] = \gpio_defaults_low[8] ; assign gpio_defaults[9] = \gpio_defaults_low[9] ; - assign gpio_defaults[10] = \gpio_defaults_high[10] ; + assign gpio_defaults[10] = \gpio_defaults_low[10] ; assign gpio_defaults[11] = \gpio_defaults_high[11] ; assign gpio_defaults[12] = \gpio_defaults_low[12] ; endmodule diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 3df4beaf..1616eb7c 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -208,10 +208,10 @@ module caravan ( // ser_tx = mprj_io[6] (output) // irq = mprj_io[7] (input) - wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */ - wire [`MPRJ_IO_PADS-1:0] mgmt_io_nc; /* no-connects */ - wire [4:0] mgmt_io_out; /* three-pin interface out */ - wire [4:0] mgmt_io_oeb; /* three-pin output enable */ + wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data in */ + wire [`MPRJ_IO_PADS-1:0] mgmt_io_out; /* one- and three-pin data out */ + wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb; /* output enable, used only by */ + /* three-pin interfaces */ wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */ wire clock_core; @@ -761,10 +761,8 @@ module caravan ( .serial_data_2(mprj_io_loader_data_2), .mgmt_gpio_in(mgmt_io_in), - .mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2], - mgmt_io_out[1:0]}), - .mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0], - mgmt_io_oeb[1:0]}), + .mgmt_gpio_out(mgmt_io_out), + .mgmt_gpio_oeb(mgmt_io_oeb), .pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */ @@ -850,7 +848,7 @@ module caravan ( // CSB is configured to be a weak pull-up gpio_defaults_block #( - .GPIO_CONFIG_INIT(13'h0c01) + .GPIO_CONFIG_INIT(13'h0801) ) gpio_defaults_block_3 ( `ifdef USE_POWER_PINS .VPWR(vccd_core), @@ -1183,7 +1181,7 @@ module caravan ( .serial_load_out(gpio_load_1[7:2]), .mgmt_gpio_in(mgmt_io_in[7:2]), - .mgmt_gpio_out(mgmt_io_in[7:2]), + .mgmt_gpio_out(mgmt_io_out[7:2]), .mgmt_gpio_oeb(one_loop1[5:0]), .one(one_loop1[5:0]), @@ -1235,7 +1233,7 @@ module caravan ( .serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]), .mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]), - .mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]), + .mgmt_gpio_out(mgmt_io_out[`DIG1_TOP:8]), .mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]), .one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]), @@ -1288,8 +1286,8 @@ module caravan ( .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]), .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP):(`DIG2_TOP-2)]), - .mgmt_gpio_out(mgmt_io_out[4:2]), - .mgmt_gpio_oeb(mgmt_io_oeb[4:2]), + .mgmt_gpio_out(mgmt_io_out[(`DIG2_TOP):(`DIG2_TOP-2)]), + .mgmt_gpio_oeb(mgmt_io_oeb[(`DIG2_TOP):(`DIG2_TOP-2)]), .one(), .zero(), @@ -1342,7 +1340,7 @@ module caravan ( .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]), .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]), - .mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]), + .mgmt_gpio_out(mgmt_io_out[(`DIG2_TOP-3):`DIG2_BOT]), .mgmt_gpio_oeb(one_loop2), .one(one_loop2), diff --git a/verilog/rtl/caravan_netlists.v b/verilog/rtl/caravan_netlists.v index 8dc8a7eb..2acb15f3 100644 --- a/verilog/rtl/caravan_netlists.v +++ b/verilog/rtl/caravan_netlists.v @@ -62,6 +62,7 @@ `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" `include "gl/gpio_defaults_block_1803.v" + `include "gl/gpio_defaults_block_0801.v" `include "gl/gpio_logic_high.v" `include "gl/xres_buf.v" `include "gl/spare_logic_block.v" diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index f6ce11e4..ce382a97 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -173,10 +173,10 @@ module caravel ( // ser_tx = mprj_io[6] (output) // irq = mprj_io[7] (input) - wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */ - wire [`MPRJ_IO_PADS-5:0] mgmt_io_nc; /* no-connects */ - wire [4:0] mgmt_io_out; /* three-pin interface out */ - wire [4:0] mgmt_io_oeb; /* three-pin output enable */ + wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data in */ + wire [`MPRJ_IO_PADS-1:0] mgmt_io_out; /* one- and three-pin data out */ + wire [`MPRJ_IO_PADS-5:0] mgmt_io_oeb; /* output enable, used only by */ + /* the three-pin interfaces */ wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */ wire clock_core; @@ -703,10 +703,8 @@ module caravel ( .serial_data_2(mprj_io_loader_data_2), .mgmt_gpio_in(mgmt_io_in), - .mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2], - mgmt_io_out[1:0]}), - .mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0], - mgmt_io_oeb[1:0]}), + .mgmt_gpio_out(mgmt_io_out), + .mgmt_gpio_oeb(mgmt_io_oeb), .pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */ @@ -792,7 +790,7 @@ module caravel ( // CSB pin is set as an internal pull-up gpio_defaults_block #( - .GPIO_CONFIG_INIT(13'h0c01) + .GPIO_CONFIG_INIT(13'h0801) ) gpio_defaults_block_3 ( `ifdef USE_POWER_PINS .VPWR(vccd_core), @@ -1236,7 +1234,7 @@ module caravel ( .serial_load_out(gpio_load_1[7:2]), .mgmt_gpio_in(mgmt_io_in[7:2]), - .mgmt_gpio_out(mgmt_io_in[7:2]), + .mgmt_gpio_out(mgmt_io_out[7:2]), .mgmt_gpio_oeb(one_loop1[7:2]), .one(one_loop1[7:2]), @@ -1289,7 +1287,7 @@ module caravel ( .serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]), .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]), - .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]), + .mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS_1-1):8]), .mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]), .one(one_loop1[(`MPRJ_IO_PADS_1-1):8]), @@ -1342,8 +1340,8 @@ module caravel ( .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]), .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]), - .mgmt_gpio_out(mgmt_io_out[4:2]), - .mgmt_gpio_oeb(mgmt_io_oeb[4:2]), + .mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]), + .mgmt_gpio_oeb(mgmt_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]), .one(), .zero(), @@ -1396,7 +1394,7 @@ module caravel ( .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]), .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), - .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), + .mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), .mgmt_gpio_oeb(one_loop2), .one(one_loop2), diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index c967700e..d48ce2c4 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -60,6 +60,7 @@ `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" `include "gl/gpio_defaults_block_1803.v" + `include "gl/gpio_defaults_block_0801.v" `include "gl/gpio_logic_high.v" `include "gl/xres_buf.v" `include "gl/spare_logic_block.v" diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index 639d734a..b77f081f 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -44,6 +44,9 @@ * so that the serial data bit out from the module only changes on * the clock half cycle. This avoids the need to fine-tune the clock * skew between GPIO blocks. + * + * Modified 10/05/2022 by Tim Edwards + * *--------------------------------------------------------------------- */ @@ -140,11 +143,12 @@ module gpio_control_block #( wire pad_gpio_outenb; wire pad_gpio_out; wire pad_gpio_in; + wire one_unbuf; + wire zero_unbuf; wire one; wire zero; wire user_gpio_in; - wire gpio_in_unbuf; wire gpio_logic1; reg serial_data_out; @@ -223,11 +227,21 @@ module gpio_control_block #( /* Implement pad control behavior depending on state of mgmt_ena */ - assign gpio_in_unbuf = pad_gpio_in; - assign mgmt_gpio_in = (gpio_inenb == 1'b0 && gpio_outenb == 1'b1) ? - pad_gpio_in : 1'bz; + /* The pad value always goes back to the housekeeping module */ + + assign mgmt_gpio_in = pad_gpio_in; + + /* For 2-wire interfaces, the mgmt_gpio_oeb line is tied high at */ + /* the control block. In this case, the output enable state is */ + /* determined by the OEB configuration bit. */ + assign pad_gpio_outenb = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ? gpio_outenb : 1'b0) : user_gpio_oeb; + + /* For 2-wire interfaces, if the pad is configured for pull-up or */ + /* pull-down, drive the output value locally to achieve the */ + /* expected pull. */ + assign pad_gpio_out = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ? ((gpio_dm[2:1] == 2'b01) ? ~gpio_dm[0] : mgmt_gpio_out) : mgmt_gpio_out) : user_gpio_out; @@ -242,17 +256,9 @@ module gpio_control_block #( .gpio_logic1(gpio_logic1) ); - sky130_fd_sc_hd__einvp_8 gpio_in_buf ( -`ifdef USE_POWER_PINS - .VPWR(vccd), - .VGND(vssd), - .VPB(vccd), - .VNB(vssd), -`endif - .Z(user_gpio_in), - .A(~gpio_in_unbuf), - .TE(gpio_logic1) - ); + /* If user project area is powered down, zero the pad input value */ + /* going to the user project. */ + assign user_gpio_in = pad_gpio_in & gpio_logic1; sky130_fd_sc_hd__conb_1 const_source ( `ifdef USE_POWER_PINS @@ -261,9 +267,12 @@ module gpio_control_block #( .VPB(vccd), .VNB(vssd), `endif - .HI(one), - .LO(zero) + .HI(one_unbuf), + .LO(zero_unbuf) ); + assign zero = zero_unbuf; + assign one = one_unbuf; + endmodule `default_nettype wire diff --git a/verilog/rtl/housekeeping.v b/verilog/rtl/housekeeping.v index 999cc1e1..4358f3bf 100644 --- a/verilog/rtl/housekeeping.v +++ b/verilog/rtl/housekeeping.v @@ -253,7 +253,7 @@ module housekeeping #( wire [31:0] sram_ro_data; // Housekeeping side 3-wire interface to GPIOs (see below) - wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out_pre; + wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out; // Pass-through mode handling. Signals may only be applied when the // core processor is in reset. @@ -264,26 +264,6 @@ module housekeeping #( wire wb_rst_i; assign wb_rst_i = ~wb_rstn_i; - // Handle the management-side control of the GPIO pins. All but the - // first and last three GPIOs (0, 1 and 35 to 37) are one-pin interfaces with - // a single I/O pin whose direction is determined by the local OEB signal. - // The other five are straight-through connections of the 3-wire interface. - - assign mgmt_gpio_out[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-3] = - mgmt_gpio_out_pre[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-3]; - assign mgmt_gpio_out[1:0] = mgmt_gpio_out_pre[1:0]; - - genvar i; - - // This implements high-impedence buffers on the GPIO outputs other than - // the first and last two GPIOs so that these pins can be tied together - // at the top level to create the single-wire interface on those GPIOs. - generate - for (i = 2; i < `MPRJ_IO_PADS-3; i = i + 1) begin - assign mgmt_gpio_out[i] = mgmt_gpio_oeb[i] ? 1'bz : mgmt_gpio_out_pre[i]; - end - endgenerate - // Pass-through mode. Housekeeping SPI signals get inserted // between the management SoC and the flash SPI I/O. @@ -750,7 +730,7 @@ module housekeeping #( .reset(~porb), .SCK(mgmt_gpio_in[4]), .SDI(mgmt_gpio_in[2]), - .CSB((spi_is_active) ? mgmt_gpio_in[3] : 1'b1), + .CSB((spi_is_enabled) ? mgmt_gpio_in[3] : 1'b1), .SDO(sdo), .sdoenb(sdo_enb), .idata(odata), @@ -777,9 +757,9 @@ module housekeeping #( // GPIO data handling to and from the management SoC - assign mgmt_gpio_out_pre[37] = (qspi_enabled) ? spimemio_flash_io3_do : + assign mgmt_gpio_out[37] = (qspi_enabled) ? spimemio_flash_io3_do : mgmt_gpio_data[37]; - assign mgmt_gpio_out_pre[36] = (qspi_enabled) ? spimemio_flash_io2_do : + assign mgmt_gpio_out[36] = (qspi_enabled) ? spimemio_flash_io2_do : mgmt_gpio_data[36]; assign mgmt_gpio_oeb[37] = (qspi_enabled) ? spimemio_flash_io3_oeb : @@ -795,32 +775,32 @@ module housekeeping #( assign spimemio_flash_io2_di = mgmt_gpio_in[36]; // SPI master is assigned to the other 4 bits of the data high word. - assign mgmt_gpio_out_pre[32] = (spi_enabled) ? spi_sck : mgmt_gpio_data[32]; - assign mgmt_gpio_out_pre[33] = (spi_enabled) ? spi_csb : mgmt_gpio_data[33]; - assign mgmt_gpio_out_pre[34] = mgmt_gpio_data[34]; - assign mgmt_gpio_out_pre[35] = (spi_enabled) ? spi_sdo : mgmt_gpio_data[35]; + assign mgmt_gpio_out[32] = (spi_enabled) ? spi_sck : mgmt_gpio_data[32]; + assign mgmt_gpio_out[33] = (spi_enabled) ? spi_csb : mgmt_gpio_data[33]; + assign mgmt_gpio_out[34] = mgmt_gpio_data[34]; + assign mgmt_gpio_out[35] = (spi_enabled) ? spi_sdo : mgmt_gpio_data[35]; - assign mgmt_gpio_out_pre[31:16] = mgmt_gpio_data[31:16]; - assign mgmt_gpio_out_pre[12:11] = mgmt_gpio_data[12:11]; + assign mgmt_gpio_out[31:16] = mgmt_gpio_data[31:16]; + assign mgmt_gpio_out[12:11] = mgmt_gpio_data[12:11]; - assign mgmt_gpio_out_pre[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2] + assign mgmt_gpio_out[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2] : mgmt_gpio_data[10]; - assign mgmt_gpio_out_pre[9] = (pass_thru_user) ? mgmt_gpio_in[4] + assign mgmt_gpio_out[9] = (pass_thru_user) ? mgmt_gpio_in[4] : mgmt_gpio_data[9]; - assign mgmt_gpio_out_pre[8] = (pass_thru_user_delay) ? mgmt_gpio_in[3] + assign mgmt_gpio_out[8] = (pass_thru_user_delay) ? mgmt_gpio_in[3] : mgmt_gpio_data[8]; - assign mgmt_gpio_out_pre[7] = mgmt_gpio_data[7]; - assign mgmt_gpio_out_pre[6] = (uart_enabled) ? ser_tx : mgmt_gpio_data[6]; - assign mgmt_gpio_out_pre[5:2] = mgmt_gpio_data[5:2]; + assign mgmt_gpio_out[7] = mgmt_gpio_data[7]; + assign mgmt_gpio_out[6] = (uart_enabled) ? ser_tx : mgmt_gpio_data[6]; + assign mgmt_gpio_out[5:2] = mgmt_gpio_data[5:2]; // In pass-through modes, route SDO from the respective flash (user or // management SoC) to the dedicated SDO pin (GPIO[1]) - assign mgmt_gpio_out_pre[1] = (pass_thru_mgmt) ? pad_flash_io1_di : + assign mgmt_gpio_out[1] = (pass_thru_mgmt) ? pad_flash_io1_di : (pass_thru_user) ? mgmt_gpio_in[11] : (spi_is_active) ? sdo : mgmt_gpio_data[1]; - assign mgmt_gpio_out_pre[0] = (debug_mode) ? debug_out : mgmt_gpio_data[0]; + assign mgmt_gpio_out[0] = (debug_mode) ? debug_out : mgmt_gpio_data[0]; assign mgmt_gpio_oeb[1] = (spi_is_active) ? sdo_enb : ~gpio_configure[0][INP_DIS]; assign mgmt_gpio_oeb[0] = (debug_mode) ? debug_oeb : ~gpio_configure[0][INP_DIS]; @@ -843,11 +823,11 @@ module housekeeping #( // so the pad being under control of the user area takes precedence // over the system monitoring function. - assign mgmt_gpio_out_pre[15] = (clk2_output_dest == 1'b1) ? user_clock + assign mgmt_gpio_out[15] = (clk2_output_dest == 1'b1) ? user_clock : mgmt_gpio_data[15]; - assign mgmt_gpio_out_pre[14] = (clk1_output_dest == 1'b1) ? wb_clk_i + assign mgmt_gpio_out[14] = (clk1_output_dest == 1'b1) ? wb_clk_i : mgmt_gpio_data[14]; - assign mgmt_gpio_out_pre[13] = (trap_output_dest == 1'b1) ? trap + assign mgmt_gpio_out[13] = (trap_output_dest == 1'b1) ? trap : mgmt_gpio_data[13]; assign irq[0] = irq_spi; @@ -1041,7 +1021,7 @@ module housekeeping #( end else begin if (j == 3) begin // j == 3 corresponds to CSB, which is a weak pull-up - gpio_configure[j] <= 'h0c01; + gpio_configure[j] <= 'h0801; end else begin gpio_configure[j] <= 'h0403; end