Merge pull request #180 from mo-hosni/caravel_redesign

Caravel redesign

openlane/constant_block/config.tcl

@@ -0,0 +1,67 @@
+set ::env(DESIGN_NAME) constant_block
+set ::env(ROUTING_CORES) 2
+set ::env(DESIGN_IS_CORE) 0
+set ::env(PDK) "sky130A"
+
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/../../rtl/constant_block.v]
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(CLOCK_PORT) ""
+
+set ::env(VDD_PIN) {vccd}
+set ::env(VDD_NET) {vccd}
+set ::env(GND_PIN) {vssd}
+set ::env(GND_NET) {vssd}
+
+# Synthesis
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(SYNTH_BUFFERING) 0
+set ::env(DRC_EXCLUDE_CELL_LIST) [glob $::env(DESIGN_DIR)/drc_exclude.list] 
+
+set ::env(CLOCK_TREE_SYNTH) 0
+
+## Floorplan
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) "0.0 0.0 14 13"
+set ::env(CELL_PAD) 0
+set ::env(FP_PDN_LOWER_LAYER) {met4}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hd__decap_3"
+set ::env(DECAP_CELL) {sky130_fd_sc_hd__decap_3}
+set ::env(DIODE_PADDING) 0
+set ::env(TAP_DECAP_INSERTION) {1}
+set ::env(FILL_INSERTION) 1
+set ::env(BOTTOM_MARGIN_MULT) 0.2
+set ::env(TOP_MARGIN_MULT) 0.2
+set ::env(LEFT_MARGIN_MULT) 1
+set ::env(RIGHT_MARGIN_MULT) 1
+
+## PDN
+set ::env(FP_PDN_AUTO_ADJUST) {0}
+set ::env(FP_PDN_CHECK_NODES) {0}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_VWIDTH) {0.9}
+set ::env(FP_PDN_VOFFSET) 1
+set ::env(FP_PDN_VPITCH) 5
+set ::env(FP_PDN_VSPACING) 1.6
+set ::env(FP_TAPCELL_DIST) 12
+# set ::env(PDN_CFG) [glob $::env(DESIGN_DIR)/pdn.tcl]
+
+## Placement 
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.95
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+
+## Routing 
+set ::env(RT_MIN_LAYER) "met1"
+set ::env(RT_MAX_LAYER) "met3"
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+
+## Antenna 
+set ::env(DIODE_INSERTION_STRATEGY) 3

openlane/constant_block/drc_exclude.list

@@ -0,0 +1,75 @@
+sky130_fd_sc_hd__a2111oi_0
+sky130_fd_sc_hd__a21boi_0
+sky130_fd_sc_hd__and2_0
+sky130_fd_sc_hd__buf_16
+sky130_fd_sc_hd__clkdlybuf4s15_1
+sky130_fd_sc_hd__clkdlybuf4s18_1
+sky130_fd_sc_hd__fa_4
+sky130_fd_sc_hd__lpflow_bleeder_1
+sky130_fd_sc_hd__lpflow_clkbufkapwr_1
+sky130_fd_sc_hd__lpflow_clkbufkapwr_16
+sky130_fd_sc_hd__lpflow_clkbufkapwr_2
+sky130_fd_sc_hd__lpflow_clkbufkapwr_4
+sky130_fd_sc_hd__lpflow_clkbufkapwr_8
+sky130_fd_sc_hd__lpflow_clkinvkapwr_1
+sky130_fd_sc_hd__lpflow_clkinvkapwr_16
+sky130_fd_sc_hd__lpflow_clkinvkapwr_2
+sky130_fd_sc_hd__lpflow_clkinvkapwr_4
+sky130_fd_sc_hd__lpflow_clkinvkapwr_8
+sky130_fd_sc_hd__lpflow_decapkapwr_12
+sky130_fd_sc_hd__lpflow_decapkapwr_3
+sky130_fd_sc_hd__lpflow_decapkapwr_4
+sky130_fd_sc_hd__lpflow_decapkapwr_6
+sky130_fd_sc_hd__lpflow_decapkapwr_8
+sky130_fd_sc_hd__lpflow_inputiso0n_1
+sky130_fd_sc_hd__lpflow_inputiso0p_1
+sky130_fd_sc_hd__lpflow_inputiso1n_1
+sky130_fd_sc_hd__lpflow_inputiso1p_1
+sky130_fd_sc_hd__lpflow_inputisolatch_1
+sky130_fd_sc_hd__lpflow_isobufsrc_1
+sky130_fd_sc_hd__lpflow_isobufsrc_16
+sky130_fd_sc_hd__lpflow_isobufsrc_2
+sky130_fd_sc_hd__lpflow_isobufsrc_4
+sky130_fd_sc_hd__lpflow_isobufsrc_8
+sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
+sky130_fd_sc_hd__mux4_4
+sky130_fd_sc_hd__o21ai_0
+sky130_fd_sc_hd__o311ai_0
+sky130_fd_sc_hd__or2_0
+sky130_fd_sc_hd__probe_p_8
+sky130_fd_sc_hd__probec_p_8
+sky130_fd_sc_hd__xor3_1
+sky130_fd_sc_hd__xor3_2
+sky130_fd_sc_hd__xor3_4
+sky130_fd_sc_hd__xnor3_1
+sky130_fd_sc_hd__xnor3_2
+sky130_fd_sc_hd__xnor3_4
+sky130_fd_sc_hd__clkbuf_1
+sky130_fd_sc_hd__clkbuf_2
+sky130_fd_sc_hd__clkbuf_12
+sky130_fd_sc_hd__clkbuf_16
+sky130_fd_sc_hd__clkdlybuf4s15_1
+sky130_fd_sc_hd__clkdlybuf4s15_2
+sky130_fd_sc_hd__clkdlybuf4s18_1
+sky130_fd_sc_hd__clkdlybuf4s18_2
+sky130_fd_sc_hd__clkdlybuf4s25_1
+sky130_fd_sc_hd__clkdlybuf4s25_2
+sky130_fd_sc_hd__clkdlybuf4s50_1
+sky130_fd_sc_hd__clkdlybuf4s50_2
+sky130_fd_sc_hd__dlygate4sd1_1
+sky130_fd_sc_hd__dlygate4sd2_1
+sky130_fd_sc_hd__dlygate4sd3_1
+sky130_fd_sc_hd__dlymetal6s2s_1
+sky130_fd_sc_hd__dlymetal6s4s_1
+sky130_fd_sc_hd__dlymetal6s6s_1
+sky130_fd_sc_hd__buf_1
+sky130_fd_sc_hd__buf_2
+sky130_fd_sc_hd__buf_12
+sky130_fd_sc_hd__decap_3

openlane/constant_block/pdn.tcl

@@ -0,0 +1,25 @@
+puts "set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)"
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
+
+# Assesses whether the design is the core of the chip or not based on the
+# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+define_pdn_grid \
+    -name stdcell_grid \
+    -starts_with POWER \
+    -voltage_domain CORE \
+    -pins "met4"
+
+##vertical
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer met4 \
+    -width 1.6 \
+    -pitch 75.25 \
+    -offset 2 \
+    -spacing 5 \
+    -nets "VPWR VGND" \
+    -starts_with POWER -extend_to_core_ring
+
+add_pdn_connect \
+    -grid stdcell_grid \
+    -layers "met1 met4"

openlane/constant_block/pin_order.cfg

@@ -0,0 +1,5 @@
+#E
+one
+
+#W
+zero

openlane/housekeeping/config.tcl

@@ -14,7 +14,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 ## This should be changed to point at Caravel root
-set ::env(CARAVEL_ROOT) $::env(HOME)/home/hosni/caravel_redesign/caravel
+set ::env(CARAVEL_ROOT) $::env(DESIGN_DIR)/../..
 
 set ::env(DESIGN_NAME) "housekeeping"
 set ::env(ROUTING_CORES) 12

verilog/gl/constant_block.v

@@ -1,28 +1,79 @@
 module constant_block (one,
-    zero);
+    zero,
+    vccd,
+    vssd);
  output one;
  output zero;
+ input vccd;
+ input vssd;
 
  wire one_unbuf;
  wire zero_unbuf;
 
  sky130_fd_sc_hd__buf_16 const_one_buf (.A(one_unbuf),
+    .VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd),
     .X(one));
- sky130_fd_sc_hd__conb_1 const_source (.HI(one_unbuf),
+ sky130_fd_sc_hd__conb_1 const_source (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd),
+    .HI(one_unbuf),
     .LO(zero_unbuf));
  sky130_fd_sc_hd__buf_16 const_zero_buf (.A(zero_unbuf),
+    .VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd),
     .X(zero));
- sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_0 ();
- sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1 ();
- sky130_fd_sc_hd__fill_2 FILLER_0_0 ();
- sky130_fd_sc_hd__fill_2 FILLER_0_24 ();
- sky130_fd_sc_hd__fill_1 FILLER_0_27 ();
- sky130_fd_sc_hd__fill_4 FILLER_1_0 ();
- sky130_fd_sc_hd__fill_1 FILLER_1_4 ();
- sky130_fd_sc_hd__fill_8 FILLER_1_8 ();
- sky130_fd_sc_hd__fill_8 FILLER_1_16 ();
- sky130_fd_sc_hd__fill_4 FILLER_1_24 ();
- sky130_fd_sc_hd__fill_2 FILLER_2_0 ();
- sky130_fd_sc_hd__fill_2 FILLER_2_24 ();
- sky130_fd_sc_hd__fill_1 FILLER_2_27 ();
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_0 (.VGND(vssd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1 (.VGND(vssd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_0 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_24 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_4 FILLER_1_0 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_4 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_8 FILLER_1_8 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_8 FILLER_1_16 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_4 FILLER_1_24 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_0 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_24 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(vssd),
+    .VNB(vssd),
+    .VPB(vccd),
+    .VPWR(vccd));
 endmodule