diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 5e9c6189..dcf4a9dc 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -292,10 +292,6 @@ module caravan ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - - // Connect 1.8V constant one to nearest GPIO control block - .vccd_const_one(mprj_io_one[`MPRJ_IO_PADS-`ANALOG_PADS-1]), - .gpio(gpio), .mprj_io(mprj_io), .clock(clock), diff --git a/verilog/rtl/caravan_netlists.v b/verilog/rtl/caravan_netlists.v index 8dc8a7eb..488fda46 100644 --- a/verilog/rtl/caravan_netlists.v +++ b/verilog/rtl/caravan_netlists.v @@ -58,6 +58,7 @@ `include "gl/mprj2_logic_high.v" `include "gl/mgmt_protect.v" `include "gl/mgmt_protect_hv.v" + `include "gl/constant_block.v" `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" @@ -83,6 +84,7 @@ `include "mprj2_logic_high.v" `include "mgmt_protect.v" `include "mgmt_protect_hv.v" + `include "constant_block.v" `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 5ee33bdc..315fbc30 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -253,8 +253,6 @@ module caravel ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - // Connect 1.8V constant one to nearest GPIO control block - .vccd_const_one(mprj_io_one[`MPRJ_IO_PADS-1]), .gpio(gpio), .mprj_io(mprj_io), .clock(clock), diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index c967700e..2a6d2d0a 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -56,6 +56,7 @@ `include "gl/mprj2_logic_high.v" `include "gl/mgmt_protect.v" `include "gl/mgmt_protect_hv.v" + `include "gl/constant_block.v" `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" @@ -65,6 +66,10 @@ `include "gl/spare_logic_block.v" `include "gl/mgmt_defines.v" `include "gl/mgmt_core_wrapper.v" + `include "gl/mgmt_core.v" + `include "gl/DFFRAM.v" + `include "gl/DFFRAMBB.v" + `include "gl/VexRiscv_LiteDebug.v" `include "gl/caravel.v" `else `include "digital_pll.v" @@ -81,12 +86,17 @@ `include "mprj2_logic_high.v" `include "mgmt_protect.v" `include "mgmt_protect_hv.v" + `include "constant_block.v" `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" `include "xres_buf.v" `include "spare_logic_block.v" `include "mgmt_core_wrapper.v" + `include "mgmt_core.v" + `include "DFFRAM.v" + `include "DFFRAMBB.v" + `include "VexRiscv_LiteDebug.v" `include "caravel.v" `endif diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 6d2b3d07..88087745 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -61,7 +61,6 @@ module chip_io( // Chip Core Interface input porb_h, input por, - input vccd_const_one, output resetb_core_h, output clock_core, input gpio_out_core, @@ -277,18 +276,28 @@ module chip_io( {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; // Management clock input pad - `INPUT_PAD(clock, clock_core, vccd_const_one); + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); + + wire [6:0] vccd_const_one; // Constant value for management pins + wire [6:0] vssd_const_zero; // Constant value for management pins + + constant_block constant_value_inst [6:0] ( + .vccd(vccd), + .vssd(vssd), + .one(vccd_const_one), + .zero(vssd_const_zero) + ); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, vccd_const_one, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -313,7 +322,7 @@ module chip_io( .INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input .FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter .PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd_const_one) + .ENABLE_VDDIO(vccd_const_one[6]) ); // Corner cells (These are overlay cells; it is not clear what is normally diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v index b99afbac..3b74b35d 100644 --- a/verilog/rtl/chip_io_alt.v +++ b/verilog/rtl/chip_io_alt.v @@ -344,18 +344,28 @@ module chip_io_alt #( wire[2:0] flash_io1_mode = {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; + wire [6:0] vccd_const_one; // Constant value for management pins + wire [6:0] vssd_const_zero; // Constant value for management pins + + constant_block constant_value_inst [6:0] ( + .vccd(vccd), + .vssd(vssd), + .one(vccd_const_one), + .zero(vssd_const_zero) + ); + // Management clock input pad - `INPUT_PAD(clock, clock_core, vccd_const_one); + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, vccd_const_one, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -380,7 +390,7 @@ module chip_io_alt #( .INP_SEL_H(xres_zero_loop), // 1 = use filt_in_h else filter the pad input .FILT_IN_H(xres_zero_loop), // Alternate input for glitch filter .PULLUP_H(xres_zero_loop), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd_const_one) + .ENABLE_VDDIO(vccd_const_one[6]) ); // Corner cells (These are overlay cells; it is not clear what is normally diff --git a/verilog/rtl/constant_block.v b/verilog/rtl/constant_block.v new file mode 100644 index 00000000..d6a03b3e --- /dev/null +++ b/verilog/rtl/constant_block.v @@ -0,0 +1,77 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *--------------------------------------------------------------------- + * A simple module that generates buffered high and low outputs + * in the 1.8V domain. + *--------------------------------------------------------------------- + */ + +module constant_block ( + `ifdef USE_POWER_PINS + inout vccd, + inout vssd, + `endif + + output one, + output zero +); + + wire one_unbuf; + wire zero_unbuf; + + sky130_fd_sc_hd__conb_1 const_source ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .HI(one_unbuf), + .LO(zero_unbuf) + ); + + /* Buffer the constant outputs (could be synthesized) */ + /* NOTE: Constant cell HI, LO outputs are connected to power */ + /* rails through an approximately 120 ohm resistor, which is not */ + /* enough to drive inputs in the I/O cells while ensuring ESD */ + /* requirements, without buffering. */ + + sky130_fd_sc_hd__buf_16 const_one_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(one_unbuf), + .X(one) + ); + + sky130_fd_sc_hd__buf_16 const_zero_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(zero_unbuf), + .X(zero) + ); + +endmodule +`default_nettype wire diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index 5bfdd24d..3a0d6ea9 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -135,8 +135,8 @@ module gpio_control_block #( wire pad_gpio_outenb; wire pad_gpio_out; wire pad_gpio_in; - wire one; - wire zero; + wire one_unbuf; + wire zero_unbuf; wire user_gpio_in; wire gpio_in_unbuf; @@ -280,8 +280,36 @@ module gpio_control_block #( .VPB(vccd), .VNB(vssd), `endif - .HI(one), - .LO(zero) + .HI(one_unbuf), + .LO(zero_unbuf) + ); + + /* Buffer the constant outputs (could be synthesized) */ + /* NOTE: Constant cell HI, LO outputs are connected to power */ + /* rails through an approximately 120 ohm resistor, which is not */ + /* enough to drive inputs in the I/O cells while ensuring ESD */ + /* requirements, without buffering. */ + + sky130_fd_sc_hd__buf_8 const_one_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(one_unbuf), + .X(one) + ); + + sky130_fd_sc_hd__buf_8 const_zero_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(zero_unbuf), + .X(zero) ); endmodule diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index 3a09e243..623fc818 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -73,7 +73,7 @@ .SRC_BDY_LVC1(L1), \ .SRC_BDY_LVC2(L2) -`define INPUT_PAD(X,Y,CONB_ONE) \ +`define INPUT_PAD(X,Y,CONB_ONE,CONB_ZERO) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -81,7 +81,7 @@ `ifndef TOP_ROUTING \ .PAD(X), \ `endif \ - .OUT(loop_zero_``X), \ + .OUT(CONB_ZERO), \ .OE_N(CONB_ONE), \ .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ @@ -90,14 +90,14 @@ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(por), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ - .DM({loop_zero_``X, loop_zero_``X, vccd}), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ZERO, CONB_ZERO, CONB_ONE}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ @@ -106,7 +106,7 @@ .TIE_HI_ESD(loop_one_``X), \ .TIE_LO_ESD(loop_zero_``X) ) -`define OUTPUT_PAD(X,Y,CONB_ONE,INPUT_DIS,OUT_EN_N) \ +`define OUTPUT_PAD(X,Y,CONB_ONE,CONB_ZERO,INPUT_DIS,OUT_EN_N) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -123,14 +123,14 @@ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ - .DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ @@ -139,7 +139,7 @@ .TIE_HI_ESD(loop_one_``X), \ .TIE_LO_ESD(loop_zero_``X)) -`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,OUT_EN_N) \ +`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,CONB_ZERO,OUT_EN_N) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -155,15 +155,15 @@ .ENABLE_VDDA_H(porb_h), \ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ - .INP_DIS(loop_zero_``X), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ - .DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \ + .INP_DIS(CONB_ZERO), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ @@ -172,7 +172,7 @@ .TIE_HI_ESD(loop_one_``X), \ .TIE_LO_ESD(loop_zero_``X)) -`define INOUT_PAD(X,Y,CONB_ONE,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ +`define INOUT_PAD(X,Y,CONB_ONE,CONB_ZERO,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -189,13 +189,13 @@ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ .DM(MODE), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \