[DATA] Update caravel_clocking module floorplan

lef/caravel_clocking.lef

@@ -6,33 +6,53 @@ MACRO caravel_clocking
   CLASS BLOCK ;
   FOREIGN caravel_clocking ;
   ORIGIN 0.000 0.000 ;
-  SIZE 80.000 BY 80.000 ;
+  SIZE 100.000 BY 60.000 ;
   PIN VGND
     DIRECTION INPUT ;
     USE GROUND ;
     PORT
-      LAYER met4 ;
+      LAYER met5 ;
-        RECT 27.705 10.640 29.305 68.240 ;
+        RECT 0.000 15.330 94.300 16.930 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 31.705 94.300 33.305 ;
     END
     PORT
       LAYER met4 ;
-        RECT 50.690 10.640 52.290 68.240 ;
+        RECT 30.690 -0.240 32.290 49.200 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 62.185 -0.240 63.785 49.200 ;
     END
   END VGND
   PIN VPWR
     DIRECTION INPUT ;
     USE POWER ;
     PORT
-      LAYER met4 ;
+      LAYER met5 ;
-        RECT 16.215 10.640 17.815 68.240 ;
+        RECT 0.000 7.145 94.300 8.745 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 23.520 94.300 25.120 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 39.890 94.300 41.490 ;
     END
     PORT
       LAYER met4 ;
-        RECT 39.200 10.640 40.800 68.240 ;
+        RECT 14.945 -0.240 16.545 49.200 ;
     END
     PORT
       LAYER met4 ;
-        RECT 62.185 10.640 63.785 68.240 ;
+        RECT 46.435 -0.240 48.035 49.200 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 77.930 -0.240 79.530 49.200 ;
     END
   END VPWR
   PIN core_clk
@@ -40,7 +60,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 13.430 76.000 13.710 80.000 ;
+        RECT 35.510 56.000 35.790 60.000 ;
     END
   END core_clk
   PIN ext_clk
@@ -48,7 +68,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 59.890 0.000 60.170 4.000 ;
+        RECT 21.250 56.000 21.530 60.000 ;
     END
   END ext_clk
   PIN ext_clk_sel
@@ -56,7 +76,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 4.800 80.000 5.400 ;
+        RECT 96.000 3.440 100.000 4.040 ;
     END
   END ext_clk_sel
   PIN ext_reset
@@ -64,23 +84,23 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 74.840 80.000 75.440 ;
+        RECT 96.000 55.800 100.000 56.400 ;
     END
   END ext_reset
   PIN pll_clk
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
+      LAYER met2 ;
-        RECT 0.000 19.760 4.000 20.360 ;
+        RECT 78.290 56.000 78.570 60.000 ;
     END
   END pll_clk
   PIN pll_clk90
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
+      LAYER met2 ;
-        RECT 0.000 59.880 4.000 60.480 ;
+        RECT 92.550 56.000 92.830 60.000 ;
     END
   END pll_clk90
   PIN resetb
@@ -88,7 +108,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 19.870 0.000 20.150 4.000 ;
+        RECT 6.990 56.000 7.270 60.000 ;
     END
   END resetb
   PIN resetb_sync
@@ -96,7 +116,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 66.790 76.000 67.070 80.000 ;
+        RECT 64.030 56.000 64.310 60.000 ;
     END
   END resetb_sync
   PIN sel2[0]
@@ -104,7 +124,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 44.920 80.000 45.520 ;
+        RECT 96.000 33.360 100.000 33.960 ;
     END
   END sel2[0]
   PIN sel2[1]
@@ -112,7 +132,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 54.440 80.000 55.040 ;
+        RECT 96.000 40.840 100.000 41.440 ;
     END
   END sel2[1]
   PIN sel2[2]
@@ -120,7 +140,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 64.640 80.000 65.240 ;
+        RECT 96.000 48.320 100.000 48.920 ;
     END
   END sel2[2]
   PIN sel[0]
@@ -128,7 +148,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 14.320 80.000 14.920 ;
+        RECT 96.000 10.920 100.000 11.520 ;
     END
   END sel[0]
   PIN sel[1]
@@ -136,7 +156,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 24.520 80.000 25.120 ;
+        RECT 96.000 18.400 100.000 19.000 ;
     END
   END sel[1]
   PIN sel[2]
@@ -144,7 +164,7 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 76.000 34.720 80.000 35.320 ;
+        RECT 96.000 25.880 100.000 26.480 ;
     END
   END sel[2]
   PIN user_clk
@@ -152,43 +172,94 @@ MACRO caravel_clocking
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 40.110 76.000 40.390 80.000 ;
+        RECT 49.770 56.000 50.050 60.000 ;
     END
   END user_clk
   OBS
+      LAYER nwell ;
+        RECT -0.190 44.825 94.490 47.655 ;
+        RECT -0.190 39.385 94.490 42.215 ;
+        RECT -0.190 33.945 94.490 36.775 ;
+        RECT -0.190 28.505 94.490 31.335 ;
+        RECT -0.190 23.065 94.490 25.895 ;
+        RECT -0.190 17.625 94.490 20.455 ;
+        RECT -0.190 12.185 94.490 15.015 ;
+        RECT -0.190 6.745 94.490 9.575 ;
+        RECT -0.190 1.305 94.490 4.135 ;
+      LAYER pwell ;
+        RECT 0.145 -0.085 0.315 0.085 ;
+        RECT 1.525 -0.085 1.695 0.085 ;
+        RECT 7.045 -0.085 7.215 0.085 ;
+        RECT 12.560 -0.055 12.680 0.055 ;
+        RECT 13.485 -0.085 13.655 0.085 ;
+        RECT 19.005 -0.085 19.175 0.085 ;
+        RECT 24.525 -0.085 24.695 0.085 ;
+        RECT 26.365 -0.085 26.535 0.085 ;
+        RECT 31.885 -0.085 32.055 0.085 ;
+        RECT 35.575 -0.050 35.735 0.060 ;
+        RECT 37.405 -0.085 37.575 0.085 ;
+        RECT 37.875 -0.050 38.035 0.060 ;
+        RECT 39.245 -0.085 39.415 0.085 ;
+        RECT 42.005 -0.085 42.175 0.085 ;
+        RECT 51.200 -0.055 51.320 0.055 ;
+        RECT 52.125 -0.085 52.295 0.085 ;
+        RECT 55.350 -0.085 55.520 0.085 ;
+        RECT 56.725 -0.085 56.895 0.085 ;
+        RECT 62.245 -0.085 62.415 0.085 ;
+        RECT 64.080 -0.055 64.200 0.055 ;
+        RECT 65.005 -0.085 65.175 0.085 ;
+        RECT 70.525 -0.085 70.695 0.085 ;
+        RECT 76.045 -0.085 76.215 0.085 ;
+        RECT 77.885 -0.085 78.055 0.085 ;
+        RECT 83.405 -0.085 83.575 0.085 ;
+        RECT 84.785 -0.085 84.955 0.085 ;
+        RECT 88.005 -0.085 88.175 0.085 ;
+        RECT 89.840 -0.055 89.960 0.055 ;
+        RECT 90.775 -0.050 90.935 0.060 ;
+        RECT 92.605 -0.085 92.775 0.085 ;
+        RECT 93.985 -0.085 94.155 0.085 ;
       LAYER li1 ;
-        RECT 5.520 5.185 77.135 75.055 ;
+        RECT 0.000 0.085 95.075 49.045 ;
+      LAYER li1 ;
+        RECT 0.000 -0.085 94.300 0.085 ;
+      LAYER li1 ;
+        RECT 94.300 0.000 95.075 0.085 ;
       LAYER met1 ;
-        RECT 5.520 5.140 77.195 75.100 ;
+        RECT 0.000 0.000 95.135 49.200 ;
+        RECT 0.000 -0.240 94.300 0.000 ;
       LAYER met2 ;
-        RECT 7.000 75.720 13.150 76.000 ;
+        RECT 1.940 55.720 6.710 56.285 ;
-        RECT 13.990 75.720 39.830 76.000 ;
+        RECT 7.550 55.720 20.970 56.285 ;
-        RECT 40.670 75.720 66.510 76.000 ;
+        RECT 21.810 55.720 35.230 56.285 ;
-        RECT 67.350 75.720 75.350 76.000 ;
+        RECT 36.070 55.720 49.490 56.285 ;
-        RECT 7.000 4.280 75.350 75.720 ;
+        RECT 50.330 55.720 63.750 56.285 ;
-        RECT 7.000 4.000 19.590 4.280 ;
+        RECT 64.590 55.720 78.010 56.285 ;
-        RECT 20.430 4.000 59.610 4.280 ;
+        RECT 78.850 55.720 92.270 56.285 ;
-        RECT 60.450 4.000 75.350 4.280 ;
+        RECT 93.110 55.720 93.290 56.285 ;
+        RECT 1.940 0.000 93.290 55.720 ;
+        RECT 30.720 -0.240 32.260 0.000 ;
+        RECT 62.215 -0.240 63.755 0.000 ;
       LAYER met3 ;
-        RECT 4.000 74.440 75.600 75.305 ;
+        RECT 14.945 55.400 95.600 56.265 ;
-        RECT 4.000 65.640 76.000 74.440 ;
+        RECT 14.945 49.320 96.000 55.400 ;
-        RECT 4.000 64.240 75.600 65.640 ;
+        RECT 14.945 47.920 95.600 49.320 ;
-        RECT 4.000 60.880 76.000 64.240 ;
+        RECT 14.945 41.840 96.000 47.920 ;
-        RECT 4.400 59.480 76.000 60.880 ;
+        RECT 14.945 40.440 95.600 41.840 ;
-        RECT 4.000 55.440 76.000 59.480 ;
+        RECT 14.945 34.360 96.000 40.440 ;
-        RECT 4.000 54.040 75.600 55.440 ;
+        RECT 14.945 32.960 95.600 34.360 ;
-        RECT 4.000 45.920 76.000 54.040 ;
+        RECT 14.945 26.880 96.000 32.960 ;
-        RECT 4.000 44.520 75.600 45.920 ;
+        RECT 14.945 25.480 95.600 26.880 ;
-        RECT 4.000 35.720 76.000 44.520 ;
+        RECT 14.945 19.400 96.000 25.480 ;
-        RECT 4.000 34.320 75.600 35.720 ;
+        RECT 14.945 18.000 95.600 19.400 ;
-        RECT 4.000 25.520 76.000 34.320 ;
+        RECT 14.945 11.920 96.000 18.000 ;
-        RECT 4.000 24.120 75.600 25.520 ;
+        RECT 14.945 10.520 95.600 11.920 ;
-        RECT 4.000 20.760 76.000 24.120 ;
+        RECT 14.945 4.440 96.000 10.520 ;
-        RECT 4.400 19.360 76.000 20.760 ;
+        RECT 14.945 3.040 95.600 4.440 ;
-        RECT 4.000 15.320 76.000 19.360 ;
+        RECT 14.945 0.000 96.000 3.040 ;
-        RECT 4.000 13.920 75.600 15.320 ;
+        RECT 30.690 -0.165 32.290 0.000 ;
-        RECT 4.000 5.800 76.000 13.920 ;
+        RECT 62.185 -0.165 63.785 0.000 ;
-        RECT 4.000 4.935 75.600 5.800 ;
+      LAYER met4 ;
+        RECT 48.035 -0.240 48.040 49.200 ;
   END
 END caravel_clocking
 END LIBRARY

maglef/caravel_clocking.mag

@@ -1,110 +1,174 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636983108
+timestamp 1637274818
+<< nwell >>
+rect -38 8965 18898 9531
+rect -38 7877 18898 8443
+rect -38 6789 18898 7355
+rect -38 5701 18898 6267
+rect -38 4613 18898 5179
+rect -38 3525 18898 4091
+rect -38 2437 18898 3003
+rect -38 1349 18898 1915
+rect -38 261 18898 827
+<< pwell >>
+rect 29 -17 63 17
+rect 305 -17 339 17
+rect 1409 -17 1443 17
+rect 2512 -11 2536 11
+rect 2697 -17 2731 17
+rect 3801 -17 3835 17
+rect 4905 -17 4939 17
+rect 5273 -17 5307 17
+rect 6377 -17 6411 17
+rect 7115 -10 7147 12
+rect 7481 -17 7515 17
+rect 7575 -10 7607 12
+rect 7849 -17 7883 17
+rect 8401 -17 8435 17
+rect 10240 -11 10264 11
+rect 10425 -17 10459 17
+rect 11070 -17 11104 17
+rect 11345 -17 11379 17
+rect 12449 -17 12483 17
+rect 12816 -11 12840 11
+rect 13001 -17 13035 17
+rect 14105 -17 14139 17
+rect 15209 -17 15243 17
+rect 15577 -17 15611 17
+rect 16681 -17 16715 17
+rect 16957 -17 16991 17
+rect 17601 -17 17635 17
+rect 17968 -11 17992 11
+rect 18155 -10 18187 12
+rect 18521 -17 18555 17
+rect 18797 -17 18831 17
 << obsli1 >>
-rect 1104 1037 15427 15011
+rect 0 0 19015 9809
+rect 0 -17 18860 0
 << obsm1 >>
-rect 1104 1028 15439 15020
+rect 0 0 19027 9840
+rect 0 -48 18860 0
 << metal2 >>
-rect 2686 15200 2742 16000
+rect 1398 11200 1454 12000
-rect 8022 15200 8078 16000
+rect 4250 11200 4306 12000
-rect 13358 15200 13414 16000
+rect 7102 11200 7158 12000
-rect 3974 0 4030 800
+rect 9954 11200 10010 12000
-rect 11978 0 12034 800
+rect 12806 11200 12862 12000
+rect 15658 11200 15714 12000
+rect 18510 11200 18566 12000
 << obsm2 >>
-rect 1400 15144 2630 15200
+rect 388 11144 1342 11257
-rect 2798 15144 7966 15200
+rect 1510 11144 4194 11257
-rect 8134 15144 13302 15200
+rect 4362 11144 7046 11257
-rect 13470 15144 15070 15200
+rect 7214 11144 9898 11257
-rect 1400 856 15070 15144
+rect 10066 11144 12750 11257
-rect 1400 800 3918 856
+rect 12918 11144 15602 11257
-rect 4086 800 11922 856
+rect 15770 11144 18454 11257
-rect 12090 800 15070 856
+rect 18622 11144 18658 11257
+rect 388 0 18658 11144
+rect 6144 -48 6452 0
+rect 12443 -48 12751 0
 << metal3 >>
-rect 15200 14968 16000 15088
+rect 19200 11160 20000 11280
-rect 15200 12928 16000 13048
+rect 19200 9664 20000 9784
-rect 0 11976 800 12096
+rect 19200 8168 20000 8288
-rect 15200 10888 16000 11008
+rect 19200 6672 20000 6792
-rect 15200 8984 16000 9104
+rect 19200 5176 20000 5296
-rect 15200 6944 16000 7064
+rect 19200 3680 20000 3800
-rect 15200 4904 16000 5024
+rect 19200 2184 20000 2304
-rect 0 3952 800 4072
+rect 19200 688 20000 808
-rect 15200 2864 16000 2984
-rect 15200 960 16000 1080
 << obsm3 >>
-rect 800 14888 15120 15061
+rect 2989 11080 19120 11253
-rect 800 13128 15200 14888
+rect 2989 9864 19200 11080
-rect 800 12848 15120 13128
+rect 2989 9584 19120 9864
-rect 800 12176 15200 12848
+rect 2989 8368 19200 9584
-rect 880 11896 15200 12176
+rect 2989 8088 19120 8368
-rect 800 11088 15200 11896
+rect 2989 6872 19200 8088
-rect 800 10808 15120 11088
+rect 2989 6592 19120 6872
-rect 800 9184 15200 10808
+rect 2989 5376 19200 6592
-rect 800 8904 15120 9184
+rect 2989 5096 19120 5376
-rect 800 7144 15200 8904
+rect 2989 3880 19200 5096
-rect 800 6864 15120 7144
+rect 2989 3600 19120 3880
-rect 800 5104 15200 6864
+rect 2989 2384 19200 3600
-rect 800 4824 15120 5104
+rect 2989 2104 19120 2384
-rect 800 4152 15200 4824
+rect 2989 888 19200 2104
-rect 880 3872 15200 4152
+rect 2989 608 19120 888
-rect 800 3064 15200 3872
+rect 2989 0 19200 608
-rect 800 2784 15120 3064
+rect 6138 -33 6458 0
-rect 800 1160 15200 2784
+rect 12437 -33 12757 0
-rect 800 987 15120 1160
 << metal4 >>
-rect 3243 2128 3563 13648
+rect 2989 -48 3309 9840
-rect 5541 2128 5861 13648
+rect 6138 -48 6458 9840
-rect 7840 2128 8160 13648
+rect 9287 -48 9607 9840
-rect 10138 2128 10458 13648
+rect 12437 -48 12757 9840
-rect 12437 2128 12757 13648
+rect 15586 -48 15906 9840
+<< obsm4 >>
+rect 9607 -48 9608 9840
+<< metal5 >>
+rect 0 7978 18860 8298
+rect 0 6341 18860 6661
+rect 0 4704 18860 5024
+rect 0 3066 18860 3386
+rect 0 1429 18860 1749
 << labels >>
-rlabel metal4 s 5541 2128 5861 13648 6 VGND
+rlabel metal5 s 0 3066 18860 3386 6 VGND
 port 1 nsew ground input
-rlabel metal4 s 10138 2128 10458 13648 6 VGND
+rlabel metal5 s 0 6341 18860 6661 6 VGND
 port 1 nsew ground input
-rlabel metal4 s 3243 2128 3563 13648 6 VPWR
+rlabel metal4 s 6138 -48 6458 9840 6 VGND
+port 1 nsew ground input
+rlabel metal4 s 12437 -48 12757 9840 6 VGND
+port 1 nsew ground input
+rlabel metal5 s 0 1429 18860 1749 6 VPWR
 port 2 nsew power input
-rlabel metal4 s 7840 2128 8160 13648 6 VPWR
+rlabel metal5 s 0 4704 18860 5024 6 VPWR
 port 2 nsew power input
-rlabel metal4 s 12437 2128 12757 13648 6 VPWR
+rlabel metal5 s 0 7978 18860 8298 6 VPWR
 port 2 nsew power input
-rlabel metal2 s 2686 15200 2742 16000 6 core_clk
+rlabel metal4 s 2989 -48 3309 9840 6 VPWR
+port 2 nsew power input
+rlabel metal4 s 9287 -48 9607 9840 6 VPWR
+port 2 nsew power input
+rlabel metal4 s 15586 -48 15906 9840 6 VPWR
+port 2 nsew power input
+rlabel metal2 s 7102 11200 7158 12000 6 core_clk
 port 3 nsew signal output
-rlabel metal2 s 11978 0 12034 800 6 ext_clk
+rlabel metal2 s 4250 11200 4306 12000 6 ext_clk
 port 4 nsew signal input
-rlabel metal3 s 15200 960 16000 1080 6 ext_clk_sel
+rlabel metal3 s 19200 688 20000 808 6 ext_clk_sel
 port 5 nsew signal input
-rlabel metal3 s 15200 14968 16000 15088 6 ext_reset
+rlabel metal3 s 19200 11160 20000 11280 6 ext_reset
 port 6 nsew signal input
-rlabel metal3 s 0 3952 800 4072 6 pll_clk
+rlabel metal2 s 15658 11200 15714 12000 6 pll_clk
 port 7 nsew signal input
-rlabel metal3 s 0 11976 800 12096 6 pll_clk90
+rlabel metal2 s 18510 11200 18566 12000 6 pll_clk90
 port 8 nsew signal input
-rlabel metal2 s 3974 0 4030 800 6 resetb
+rlabel metal2 s 1398 11200 1454 12000 6 resetb
 port 9 nsew signal input
-rlabel metal2 s 13358 15200 13414 16000 6 resetb_sync
+rlabel metal2 s 12806 11200 12862 12000 6 resetb_sync
 port 10 nsew signal output
-rlabel metal3 s 15200 8984 16000 9104 6 sel2[0]
+rlabel metal3 s 19200 6672 20000 6792 6 sel2[0]
 port 11 nsew signal input
-rlabel metal3 s 15200 10888 16000 11008 6 sel2[1]
+rlabel metal3 s 19200 8168 20000 8288 6 sel2[1]
 port 12 nsew signal input
-rlabel metal3 s 15200 12928 16000 13048 6 sel2[2]
+rlabel metal3 s 19200 9664 20000 9784 6 sel2[2]
 port 13 nsew signal input
-rlabel metal3 s 15200 2864 16000 2984 6 sel[0]
+rlabel metal3 s 19200 2184 20000 2304 6 sel[0]
 port 14 nsew signal input
-rlabel metal3 s 15200 4904 16000 5024 6 sel[1]
+rlabel metal3 s 19200 3680 20000 3800 6 sel[1]
 port 15 nsew signal input
-rlabel metal3 s 15200 6944 16000 7064 6 sel[2]
+rlabel metal3 s 19200 5176 20000 5296 6 sel[2]
 port 16 nsew signal input
-rlabel metal2 s 8022 15200 8078 16000 6 user_clk
+rlabel metal2 s 9954 11200 10010 12000 6 user_clk
 port 17 nsew signal output
 << properties >>
 string LEFclass BLOCK
-string FIXED_BBOX 0 0 16000 16000
+string FIXED_BBOX 0 0 20000 12000
 string LEFview TRUE
-string GDS_FILE /project/openlane/caravel_clocking/runs/caravel_clocking/results/magic/caravel_clocking.gds
+string GDS_FILE /home/ma/ef/caravel_openframe/openlane/caravel_clocking/runs/caravel_clocking/results/magic/caravel_clocking.gds
-string GDS_END 1061116
+string GDS_END 1020802
-string GDS_START 351586
+string GDS_START 357236
 << end >>
 

openlane/caravel_clocking/base.sdc

@@ -38,8 +38,9 @@ set_input_delay $ext_clk_input_delay_value  -clock [get_clocks {ext_clk}] -add_d
 set_input_delay $ext_clk_input_delay_value  -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
 set_input_delay $ext_clk_input_delay_value  -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
 set_input_delay $ext_clk_input_delay_value  -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
-#set_output_delay $output_delay_value  -clock [get_clocks {ext_clk}] -add_delay [get_ports {core_clk}]
+
 set_output_delay $ext_clk_output_delay_value  -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
+#set_output_delay $output_delay_value  -clock [get_clocks {ext_clk}] -add_delay [get_ports {core_clk}]
 #set_output_delay $output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {user_clk}]
 
 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]

openlane/caravel_clocking/config.tcl

@@ -16,7 +16,7 @@
 set script_dir [file dirname [file normalize [info script]]]
 
 set ::env(DESIGN_NAME) caravel_clocking
-set ::env(DESIGN_IS_CORE) 0
+set ::env(DESIGN_IS_CORE) 1
 
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/defines.v\
@@ -39,10 +39,13 @@ set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list
 
 ## Floorplan
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 80 80"
+set ::env(DIE_AREA) "0 0 100 60"
 
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
+set ::env(LEFT_MARGIN_MULT) 0
+set ::env(BOTTOM_MARGIN_MULT) 0
+
 set ::env(CELL_PAD) 0
 
 ## Placement
@@ -53,12 +56,14 @@ set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
 
 ## Routing
 set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(GLB_RT_MINLAYER) 2
+set ::env(GLB_RT_MAXLAYER) 6
 
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
 
 ## Diode Insertion
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(DIODE_INSERTION_STRATEGY) 3
 
 ## 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) 0

openlane/caravel_clocking/pin_order.cfg

@@ -1,17 +1,13 @@
-#S
-resetb
-ext_clk
-
 #E
 ext_clk_sel
 sel.*
 ext_reset
 
-#W
-pll_clk
-pll_clk90
-
 #N
+resetb
+ext_clk
 core_clk
 user_clk
-resetb_sync
+resetb_sync
+pll_clk
+pll_clk90

signoff/caravel_clocking/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 2021.09.09_03.00.48-60-gcbb562b
+openlane 2021.09.09_03.00.48-66-gbdb1b56

signoff/caravel_clocking/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m5s,-1,83437.5,0.0064,41718.75,89.0,668.91,267,0,0,0,0,0,0,0,0,0,0,-1,5362,2031,-3.73,-5.41,-1,-5.06,-1,-24.41,-36.66,-1,-29.74,-1,2636042.0,22.97,25.9,15.17,0.43,0.0,-1,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,42,57,0,99,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,22.986666666666668,19.413333333333334,0.94,0,sky130_fd_sc_hd,0,4
+0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m3s,-1,89000.0,0.006,44500.0,74.66,661.45,267,0,0,0,0,0,0,0,0,0,0,-1,5162,1877,-3.73,-5.42,-1,-5.02,-1,-24.41,-36.7,-1,-29.25,-1,2976421.0,0.0,29.23,16.28,1.81,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,36,70,0,106,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,31.493333333333336,16.37333333333333,0.94,0,sky130_fd_sc_hd,0,3