mirror of https://github.com/efabless/caravel.git
Apply automatic changes to Manifest and README.rst
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@ -20,9 +20,9 @@ fa26aa34b4b382aacad9b7ac07a36b17172a401f verilog/rtl/caravel.v
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1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v
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1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v
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ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v
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ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v
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d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
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d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
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66cd4cc70097aa0a0666d0105712affa140a3977 verilog/rtl/chip_io.v
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e54c181033aa019f0edcaed5ffc71e54c3888970 verilog/rtl/chip_io.v
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f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v
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1088531d6a69d82b976d4aca7ae923423680a715 verilog/rtl/chip_io_alt.v
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09740344da1a9bb76438165247c49b4795b94b9b verilog/rtl/chip_io_openframe.v
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e293e138c6e6f5df76db78bdaa34a35003f6ba5f verilog/rtl/chip_io_openframe.v
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126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
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126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
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941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
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941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
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58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
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58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
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@ -48,7 +48,7 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v
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3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
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3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
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5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
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5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
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33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v
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33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v
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51f7c21d36076958a145a1ff8f4947b147e54fd4 verilog/rtl/pads.v
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b53c154e6acaf44e858c936c8027d0229608676e verilog/rtl/pads.v
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669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
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669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
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83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v
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83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v
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b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
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b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
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