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caravel
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update script and top level testbench for sdf

This commit is contained in:
M0stafaRady 2022-10-13 04:25:14 -07:00
parent 95cca2dec0
commit 5d3766edf7
4 changed files with 18 additions and 10 deletions
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2
sdf_pt/sdf_includes.v
View File

@ -2,5 +2,5 @@ initial begin
// $sdf_annotate({`MAIN_PATH,"sdf_pt//RAM256", `SDF_POSTFIX, ".sdf"}, uut.soc.RAM256,,"annotation_logs/DFFRAM.log","MINIMUM");
// $sdf_annotate({`MAIN_PATH,"sdf_pt//RAM128", `SDF_POSTFIX, ".sdf"}, uut.soc.RAM128,,"annotation_logs/DFFRAM.log","MINIMUM");
// $sdf_annotate({`MAIN_PATH,"sdf_pt//mgmt_core_wrapper", `SDF_POSTFIX, ".sdf"}, uut.soc,,"annotation_logs/mgmt_core_wrapper.log","MINIMUM");
$sdf_annotate({"sdf_pt/caravel", `SDF_POSTFIX,".sdf"}, uut,,{`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,"annotation_logs/caravel.log"},"MINIMUM");
$sdf_annotate({`MAIN_PATH,"/../../../sdf_pt/","caravel", `SDF_POSTFIX,".sdf"}, uut,,{`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},"MINIMUM");
end

8
verilog/dv/cocotb/caravel_top.sv
View File

@ -1,3 +1,4 @@
`timescale 1 ns / 1 ps
`ifdef VCS
`ifndef ENABLE_SDF
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
@ -8,14 +9,13 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`else
`include "cvc-pdk/sky130_ef_io.v"
`include "cvc-pdk/sky130_fd_io.v "
`include "cvc-pdk/sky130_fd_io.v"
`include "cvc-pdk/primitives_hd.v"
`include "cvc-pdk/sky130_fd_sc_hd.v"
`include "cvc-pdk/primitives_hvl.v"
`include "cvc-pdk/sky130_fd_sc_hvl.v"
`endif // ENABLE_SDF
`endif // VCS
`timescale 1 ns / 1 ps
module caravel_top ;
@ -34,9 +34,11 @@ initial begin
$dumpvars (0, caravel_top);
`endif
end
`ifdef VCS
`ifdef ENABLE_SDF
`include "sdf_pt/sdf_includes.v"
`include "sdf_includes.v"
`endif
`endif // VCS
wire vddio_tb; // Common 3.3V padframe/ESD power
wire vddio_2_tb; // Common 3.3V padframe/ESD power
wire vssio_tb; // Common padframe/ESD ground

2
verilog/dv/cocotb/tests/common_functions/test_functions.py
View File

@ -57,7 +57,7 @@ def repot_test(func):
cocotb.log.error = CallCounted(cocotb.log.error)
cocotb.log.critical = CallCounted(cocotb.log.critical)
cocotb.log.warning = CallCounted(cocotb.log.warning)
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('SIM')}-{TestName}/{TestName}.log",mode='w')
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('TESTFULLNAME')}/{TestName}.log",mode='w')
handler.addFilter(SimTimeContextFilter())
handler.setFormatter(SimLogFormatter())
cocotb.log.addHandler(handler)

14
verilog/dv/cocotb/verify_cocotb.py
View File

@ -10,6 +10,7 @@ from fnmatch import fnmatch
from datetime import datetime
import random
from pathlib import Path
import shutil
iverilog = True
@ -90,7 +91,7 @@ class RunTest:
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" '
else:
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" '
full_test_name = f"{self.sim_type}-{self.test_name}"
macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
if self.test_name == "la":
macros = f'{macros} +define+LA_TESTING'
@ -102,7 +103,8 @@ class RunTest:
if (self.sim_type=="GL_SDF"):
macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"-{self.corner}\\\"'
os.makedirs(f"annotation_logs",exist_ok=True)
dirs = f"{dirs} +incdir+\\\"{os.getenv('CARAVEL_ROOT')}/sdf_pt\\\""
dirs = f"{dirs} +incdir+\\\"{os.getenv('CARAVEL_ROOT')}/sdf_pt\\\" +incdir+\\\"{os.getenv('MCW_ROOT')}/verilog/\\\" "
full_test_name = f"{self.sim_type}-{self.test_name}-{self.corner}"
elif(self.sim_type=="GL"):
macros = f'{macros} +define+GL +define+SIM=GL'
elif (self.sim_type=="RTL"):
@ -115,12 +117,16 @@ class RunTest:
os.environ["TESTCASE"] = f"{self.test_name}"
os.environ["MODULE"] = f"caravel_tests"
os.environ["SIM"] = self.sim_type
os.environ["TESTFULLNAME"] = f"{full_test_name}"
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{full_test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")
if os.path.exists(f"{self.cocotb_path}/sdfAnnotateInfo"):
shutil.move(f"{self.cocotb_path}/sdfAnnotateInfo", f"{self.sim_path}/sdfAnnotateInfo")
shutil.copyfile(f'{self.cocotb_path}/hex_files/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
def find(self,name, path):
for root, dirs, files in os.walk(path):
@ -293,7 +299,7 @@ class RunRegression:
for sim_type,corners in sim_types.items():
for corner,status in corners.items():
new_test_name= f"{sim_type}-{test}-{corner}"
f.write(f"{new_test_name:<25} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
f.write(f"{new_test_name:<33} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ")
f.close()