mirror of https://github.com/efabless/caravel.git
Updated the verify_defaults_blocks.py script to also check the
modified caravel_core.mag layout to ensure that all the defaults blocks got the correct substitutions. Previously, only the individual defaults blocks layouts were checked and verified.
This commit is contained in:
parent
431d2b6065
commit
5c59ae6eba
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@ -17,6 +17,7 @@
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import os
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import os
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import re
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import re
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import sys
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import sys
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import gzip
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import subprocess
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import subprocess
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bits_list = ["0000", "0001", "0002", "0004", "0008", "0010", "0020", "0040",
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bits_list = ["0000", "0001", "0002", "0004", "0008", "0010", "0020", "0040",
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@ -39,24 +40,35 @@ expected_results = [
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# IMPORTANT NOTE: This script is invasive and changes files and does not change
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# IMPORTANT NOTE: This script is invasive and changes files and does not change
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# them back. Run this only in a git branch which can be removed afterward.
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# them back. Run this only in a git branch which can be removed afterward.
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if not os.path.isdir('verilog/rtl'):
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print('***ERROR: This script must be run from the caravel top level directory.')
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sys.exit(1)
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with open('verilog/rtl/user_defines.v', 'w') as ofile:
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with open('verilog/rtl/user_defines.v', 'w') as ofile:
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print('`default_nettype none', file=ofile)
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print('`default_nettype none', file=ofile)
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print('`ifndef __USER_DEFINES_H', file=ofile)
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print('`ifndef __USER_DEFINES_H', file=ofile)
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print('`define __USER_DEFINES_H', file=ofile)
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print('`define __USER_DEFINES_H', file=ofile)
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i = 5
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i = 5
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for bits in bits_list:
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for bits in bits_list:
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print("`define USER_CONFIG_GPIO_" + str(i) + "_INIT 13'h" + bits, file=ofile)
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print("`define USER_CONFIG_GPIO_" + str(i) + "_INIT 13'h" + bits, file=ofile)
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i = i + 1
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i = i + 1
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print('`endif // __USER_DEFINES_H', file=ofile)
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print('`endif // __USER_DEFINES_H', file=ofile)
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subprocess.run('scripts/gen_gpio_defaults.py')
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subprocess.run('scripts/gen_gpio_defaults.py')
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# Create the list of bits in order with channel number.
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ordered_bits_list = ["1803", "1803", "0403", "0801", "0403"]
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ordered_bits_list.extend(bits_list)
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# Add the defaults for channels 0 to 5 to the list.
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# Add the defaults for channels 0 to 5 to the list.
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bits_list.extend(["0403", "0801", "1803"])
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bits_list.extend(["0403", "0801", "1803"])
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os.chdir('mag')
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os.chdir('mag')
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print('Generating netlists from gpio_defaults layouts')
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for bits in bits_list:
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for bits in bits_list:
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if not os.path.isfile('gpio_defaults_block_' + bits + '.spice'):
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if not os.path.isfile('gpio_defaults_block_' + bits + '.mag'):
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print('***ERROR: There is no layout file for gpio_defaults_block_' + bits + '!')
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elif not os.path.isfile('gpio_defaults_block_' + bits + '.spice'):
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with open('gpio_verify.tcl', 'w') as ofile:
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with open('gpio_verify.tcl', 'w') as ofile:
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print('load gpio_defaults_block_' + bits, file=ofile)
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print('load gpio_defaults_block_' + bits, file=ofile)
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print('extract do local', file=ofile)
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print('extract do local', file=ofile)
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@ -73,30 +85,64 @@ for bits in bits_list:
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conbrex = re.compile('^Xgpio_default_value.*\[([0-9]+).*\]')
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conbrex = re.compile('^Xgpio_default_value.*\[([0-9]+).*\]')
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i = 0
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i = 0
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print('Checking each generated layout netlist:')
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for bits in bits_list:
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for bits in bits_list:
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# Read SPICE file and verify
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# Read SPICE file and verify
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bits_verify = ['X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X']
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bits_verify = ['X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X']
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with open('gpio_defaults_block_' + bits + '.spice', 'r') as ifile:
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if not os.path.isfile('gpio_defaults_block_' + bits + '.spice'):
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spicelines = ifile.read().splitlines()
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print('***ERROR: No netlist generated for gpio_defaults_block_' + bits + '!')
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for line in spicelines:
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else:
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cmatch = conbrex.match(line)
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with open('gpio_defaults_block_' + bits + '.spice', 'r') as ifile:
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if cmatch:
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spicelines = ifile.read().splitlines()
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bitnum = int(cmatch.group(1))
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for line in spicelines:
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tokens = line.split()
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cmatch = conbrex.match(line)
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if 'gpio_defaults' in tokens[5] and 'gpio_default_value' in tokens[6]:
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if cmatch:
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bits_verify[bitnum] = '1'
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bitnum = int(cmatch.group(1))
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elif 'gpio_defaults' in tokens[6] and 'gpio_default_value' in tokens[5]:
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tokens = line.split()
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bits_verify[bitnum] = '0'
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if 'gpio_defaults' in tokens[5] and 'gpio_default_value' in tokens[6]:
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else:
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bits_verify[bitnum] = '1'
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print('Bad line in netlist: ' + line)
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elif 'gpio_defaults' in tokens[6] and 'gpio_default_value' in tokens[5]:
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# Put zero bit at end
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bits_verify[bitnum] = '0'
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bits_verify.reverse()
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else:
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verify_string = ''.join(bits_verify)
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print('Bad line in netlist: ' + line)
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print('Layout for default ' + bits + ' has configuration ' + verify_string)
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# Put zero bit at end
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if verify_string != expected_results[i]:
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bits_verify.reverse()
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print('***ERROR: Expected bit string ' + expected_results[i] + ' but got ' + verify_string + '!')
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verify_string = ''.join(bits_verify)
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i = i + 1
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print('Layout for default ' + bits + ' has configuration ' + verify_string)
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if verify_string != expected_results[i]:
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print('***ERROR: Expected bit string ' + expected_results[i] + ' but got ' + verify_string + '!')
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i = i + 1
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blrex = re.compile('^use gpio_defaults_block_([0-9a-zA-Z]+).*gpio_defaults_block_([0-9]+)$')
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found = 0
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print('Checking modified caravel_core layout:')
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if os.path.isfile('caravel_core.mag.gz'):
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with gzip.open('caravel_core.mag.gz', 'r') as ifile:
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for line in ifile.readlines():
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bmatch = blrex.match(line.decode('ascii'))
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if bmatch:
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found = found + 1
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index = int(bmatch.group(2))
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value = bmatch.group(1)
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if value != ordered_bits_list[index]:
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print('***ERROR: Expected bit string ' + ordered_bits_list[index] + ' but got ' + value + ' for defaults block index ' + str(index) + '!')
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elif os.path.isfile('caravel_core.mag'):
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with open('caravel_core.mag', 'r') as ifile:
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for line in ifile.readlines():
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bmatch = blrex.match(line.decode('ascii'))
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if bmatch:
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found = found + 1
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index = int(bmatch.group(2))
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value = bmatch.group(1)
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if value != ordered_bits_list[index]:
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print('***ERROR: Expected bit string ' + ordered_bits_list[index] + ' but got ' + value + ' for defaults block index ' + str(index) + '!')
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else:
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print('***ERROR: There is no caravel_core.mag(.gz) file. Did you run the script from the project top level?')
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if found != 38:
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print('***ERROR: Found ' + str(found) + ' defaults blocks in caravel_core, not the expected 38!')
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# Remove all .ext and .spice files
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# Remove all .ext and .spice files
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for bits in bits_list:
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for bits in bits_list:
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