riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Corrected chip_io and chip_io_alt layouts to restore the accidentally 

deleted "resetb_core_h" port label.  Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
This commit is contained in:
Tim Edwards 2021-11-15 17:13:43 -05:00
parent f18a219be4
commit 559675d392
4 changed files with 2410 additions and 2520 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2505
mag/chip_io.mag
View File

File diff suppressed because it is too large Load Diff

2261
mag/chip_io_alt.mag
View File

File diff suppressed because it is too large Load Diff

84
verilog/rtl/chip_io.v
View File

@ -218,30 +218,15 @@ module chip_io(
`endif `endif
); );
// VCCD1/VSSD1 must be routed to clamps from outside sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
sky130_fd_io__top_power_lvc_wpad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
,.P_PAD(vccd1_pad),
.P_CORE(vccd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRN_LVC1(vccd1),
.DRN_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VCCD(vccd1) .VCCD1(vccd1),
.VSSD1(vssd1)
`else `else
,.VCCD_PAD(vccd1_pad) ,.VCCD_PAD(vccd1_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] ( sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
@ -262,30 +247,15 @@ module chip_io(
`endif `endif
); );
// VCCD1/VSSD1 must be routed to clamps from outside sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
sky130_fd_io__top_ground_lvc_wpad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
,.G_PAD(vssd1_pad),
.G_CORE(vssd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRN_LVC1(vccd1),
.DRN_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd1) .VCCD1(vccd1),
.VSSD1(vssd1)
`else `else
,.VSSD_PAD(vssd1_pad) ,.VSSD_PAD(vssd1_pad)
`endif `endif
); );
*/
// Instantiate power and ground pads for user 2 domain // Instantiate power and ground pads for user 2 domain
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp. // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
@ -299,30 +269,15 @@ module chip_io(
`endif `endif
); );
// VCCD2/VSSD2 must be routed to clamps from outside sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
sky130_fd_io__top_power_lvc_wpad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS
,.P_PAD(vccd2_pad),
.P_CORE(vccd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRN_LVC1(vccd2),
.DRN_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VCCD(vccd2) .VCCD1(vccd2),
.VSSD1(vssd2)
`else `else
,.VCCD_PAD(vccd2_pad) ,.VCCD_PAD(vccd2_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad ( sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
@ -333,30 +288,15 @@ module chip_io(
`endif `endif
); );
// VCCD2/VSSD2 must be routed to clamps from outside sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
sky130_fd_io__top_ground_lvc_wpad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS
,.G_PAD(vssd2_pad),
.G_CORE(vssd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRN_LVC1(vccd2),
.DRN_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd2) .VCCD1(vccd2),
.VSSD1(vssd2)
`else `else
,.VSSD_PAD(vssd2_pad) ,.VSSD_PAD(vssd2_pad)
`endif `endif
); );
*/
wire [2:0] dm_all = wire [2:0] dm_all =
{gpio_mode1_core, gpio_mode1_core, gpio_mode0_core}; {gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};

80
verilog/rtl/chip_io_alt.v
View File

@ -250,29 +250,15 @@ module chip_io_alt #(
`endif `endif
); );
// VCCD1/VSSD1 must be routed to clamps from outside sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
sky130_fd_io__top_power_lvc_wpad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vccd1_pad),
.P_CORE(vccd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRC_LVC1(vccd1),
.DRC_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VCCD(vccd1) .VCCD1(vccd1),
.VSSD1(vssd1)
`else `else
,.VCCD_PAD(vccd1_pad) ,.VCCD_PAD(vccd1_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] ( sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
@ -292,29 +278,15 @@ module chip_io_alt #(
`endif `endif
); );
// VCCD1/VSSD1 must be routed to clamps from outside sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
sky130_fd_io__top_ground_lvc_wpad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vssd1_pad),
.P_CORE(vssd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRC_LVC1(vccd1),
.DRC_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd1) .VCCD1(vccd1),
.VSSD1(vssd1)
`else `else
,.VSSD_PAD(vssd1_pad) ,.VSSD_PAD(vssd1_pad)
`endif `endif
); );
*/
// Instantiate power and ground pads for user 2 domain // Instantiate power and ground pads for user 2 domain
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp. // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
@ -328,29 +300,15 @@ module chip_io_alt #(
`endif `endif
); );
// VCCD2/VSSD2 must be routed to clamps from outside sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
sky130_fd_io__top_power_lvc_wpad user2_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vccd2_pad),
.P_CORE(vccd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRC_LVC1(vccd2),
.DRC_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VCCD(vccd2) .VCCD1(vccd2),
.VSSD1(vssd2)
`else `else
,.VCCD_PAD(vccd2_pad) ,.VCCD_PAD(vccd2_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad ( sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
@ -361,29 +319,15 @@ module chip_io_alt #(
`endif `endif
); );
// VCCD2/VSSD2 must be routed to clamps from outside sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
sky130_fd_io__top_ground_lvc_wpad user2_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vssd2_pad),
.P_CORE(vssd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRC_LVC1(vccd2),
.DRC_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd2) .VCCD1(vccd2),
.VSSD1(vssd2)
`else `else
,.VSSD_PAD(vssd2_pad) ,.VSSD_PAD(vssd2_pad)
`endif `endif
); );
*/
// Instantiate analog pads in user area 1 using the custom analog pad // Instantiate analog pads in user area 1 using the custom analog pad
sky130_ef_io__analog_pad user1_analog_pad [ANALOG_PADS_1-2:0] ( sky130_ef_io__analog_pad user1_analog_pad [ANALOG_PADS_1-2:0] (