From 555488c832f90a54616d659fbe9af484cdf40afe Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 04:11:46 -0700 Subject: [PATCH] fix timeout values to the passing number of cycles required + 10% --- verilog/dv/cocotb/tests/bitbang/bitbang_tests.py | 6 +++--- verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py | 10 +++++----- verilog/dv/cocotb/tests/cpu/cpu_stress.py | 2 +- .../dv/cocotb/tests/gpio/{gpio_all_o.py => gpio.py} | 4 ++-- .../housekeeping_regs/housekeeping_regs_tests.py | 2 +- verilog/dv/cocotb/tests/irq/IRQ_external.py | 2 +- verilog/dv/cocotb/tests/irq/IRQ_timer.py | 2 +- verilog/dv/cocotb/tests/mem/mem_stress.py | 2 +- verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 4 ++-- verilog/dv/cocotb/tests/timer/timer.py | 4 ++-- verilog/dv/cocotb/tests/uart/uart.py | 2 +- verilog/dv/cocotb/tests/uart/uart_rx.c | 5 ----- 12 files changed, 20 insertions(+), 25 deletions(-) rename verilog/dv/cocotb/tests/gpio/{gpio_all_o.py => gpio.py} (95%) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py index a0232e90..75349be4 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def bitbang_no_cpu_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000) + caravelEnv = await test_configure(dut,timeout_cycles=10206) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) @@ -128,7 +128,7 @@ async def bitbang_no_cpu_all_o(dut): @cocotb.test() @repot_test async def bitbang_no_cpu_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000) + caravelEnv = await test_configure(dut,timeout_cycles=8005) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) @@ -261,7 +261,7 @@ async def io_ports(dut): @cocotb.test() @repot_test async def bitbang_spi(dut): - caravelEnv = await test_configure(dut) + caravelEnv = await test_configure(dut,timeout_cycles=18910) # Apply data 0x1809 (management standard output) to first block of # user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards) cpu = RiskV(dut) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index 7260f281..d5a5584d 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def bitbang_cpu_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=2075459) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -55,7 +55,7 @@ async def bitbang_cpu_all_o(dut): @cocotb.test() @repot_test async def bitbang_cpu_all_10(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=2863378) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -91,7 +91,7 @@ def shift(gpio,shift_type): @cocotb.test() @repot_test async def bitbang_cpu_all_01(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=2863378) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -112,7 +112,7 @@ async def bitbang_cpu_all_01(dut): @cocotb.test() @repot_test async def bitbang_cpu_all_0011(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=5065204) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -173,7 +173,7 @@ def shift_2(gpio,shift_type): @cocotb.test() @repot_test async def bitbang_cpu_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=1691295) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/cpu/cpu_stress.py b/verilog/dv/cocotb/tests/cpu/cpu_stress.py index b572bb2e..50bb7b42 100644 --- a/verilog/dv/cocotb/tests/cpu/cpu_stress.py +++ b/verilog/dv/cocotb/tests/cpu/cpu_stress.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def cpu_stress(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1492434) + caravelEnv = await test_configure(dut,timeout_cycles=1492541) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o.py b/verilog/dv/cocotb/tests/gpio/gpio.py similarity index 95% rename from verilog/dv/cocotb/tests/gpio/gpio_all_o.py rename to verilog/dv/cocotb/tests/gpio/gpio.py index 6757cf15..ad0bc24e 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_o.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def gpio_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=264012) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -55,7 +55,7 @@ async def gpio_all_o(dut): @cocotb.test() @repot_test async def gpio_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=45464) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index 6786bb82..be69fee6 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -18,7 +18,7 @@ reg = Regs() @cocotb.test() @repot_test async def hk_regs_wr_wb(dut): - caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + caravelEnv = await test_configure(dut,timeout_cycles=237,num_error=INFINITY) cpu = RiskV(dut) cpu.cpu_force_reset() with open('wb_models/housekeepingWB/HK_regs.json') as f: diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.py b/verilog/dv/cocotb/tests/irq/IRQ_external.py index a1d959a0..91fda43d 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_external.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.py @@ -21,7 +21,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_external(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=164360) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/irq/IRQ_timer.py b/verilog/dv/cocotb/tests/irq/IRQ_timer.py index 250f68c8..0f27ce01 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_timer.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_timer.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_timer(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=166519) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/mem/mem_stress.py b/verilog/dv/cocotb/tests/mem/mem_stress.py index 70595f20..63d6ad46 100644 --- a/verilog/dv/cocotb/tests/mem/mem_stress.py +++ b/verilog/dv/cocotb/tests/mem/mem_stress.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def mem_stress(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=18164004) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 1f67643b..32050500 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def mgmt_gpio_out(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=99562) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -61,7 +61,7 @@ async def mgmt_gpio_out(dut): @cocotb.test() @repot_test async def mgmt_gpio_in(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=326525) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/timer/timer.py b/verilog/dv/cocotb/tests/timer/timer.py index 8a616df9..ee471562 100644 --- a/verilog/dv/cocotb/tests/timer/timer.py +++ b/verilog/dv/cocotb/tests/timer/timer.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def timer0_oneshot(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1000000000) + caravelEnv = await test_configure(dut,timeout_cycles=1114136) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -56,7 +56,7 @@ async def timer0_oneshot(dut): @cocotb.test() @repot_test async def timer0_periodic(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1000000000) + caravelEnv = await test_configure(dut,timeout_cycles=58257) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 7c3324d9..1e86e100 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -18,7 +18,7 @@ reg = Regs() @cocotb.test() @repot_test async def uart_tx(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481) + caravelEnv,clock = await test_configure(dut,timeout_cycles=375862) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c index 16779691..8a0ec37d 100644 --- a/verilog/dv/cocotb/tests/uart/uart_rx.c +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -40,11 +40,6 @@ void main(){ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; - // Set clock to 64 kbaud and enable the UART. It is important to do this - // before applying the configuration, or else the Tx line initializes as - // zero, which indicates the start of a byte to the receiver. - - // Now, apply the configuration reg_mprj_xfer = 1; while (reg_mprj_xfer == 1);