diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index 57a6d74a..d6c1ab90 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -1372,6 +1372,7 @@ module caravan (
     );
 
     // Spare logic for metal mask fixes
+    wire [107:0] spare_xz_nc;
     wire [15:0] spare_xi_nc;
     wire [3:0] spare_xib_nc;
     wire [7:0] spare_xna_nc;
@@ -1385,6 +1386,7 @@ module caravan (
 		.vccd(vccd_core),
 		.vssd(vssd_core),
 	`endif
+		.spare_xz(spare_xz_nc),
 		.spare_xi(spare_xi_nc),
 		.spare_xib(spare_xib_nc),
 		.spare_xna(spare_xna_nc),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 7502f681..bdf2ab4b 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1427,6 +1427,7 @@ module caravel (
     );
 
     // Spare logic for metal mask fixes
+    wire [107:0] spare_xz_nc;
     wire [15:0] spare_xi_nc;
     wire [3:0] spare_xib_nc;
     wire [7:0] spare_xna_nc;
@@ -1440,6 +1441,7 @@ module caravel (
 		.vccd(vccd_core),
 		.vssd(vssd_core),
 	`endif
+		.spare_xz(spare_xz_nc),
 		.spare_xi(spare_xi_nc),
 		.spare_xib(spare_xib_nc),
 		.spare_xna(spare_xna_nc),
diff --git a/verilog/rtl/spare_logic_block.v b/verilog/rtl/spare_logic_block.v
index 2c61da5e..e12d0de5 100644
--- a/verilog/rtl/spare_logic_block.v
+++ b/verilog/rtl/spare_logic_block.v
@@ -27,13 +27,14 @@ module spare_logic_block (
         inout vssd,
     `endif
 
-    output [3:0] spare_xi,	// Inverter outputs
-    output	 spare_xib,	// Big inverter output
-    output [1:0] spare_xna,	// NAND outputs
-    output [1:0] spare_xno,	// NOR outputs
-    output [1:0] spare_xmx,	// Mux outputs
-    output [1:0] spare_xfq,	// Flop noninverted output
-    output [1:0] spare_xfqn 	// Flop inverted output
+    output [26:0] spare_xz,	// Constant 0 outputs (and block inputs)
+    output [3:0]  spare_xi,	// Inverter outputs
+    output	  spare_xib,	// Big inverter output
+    output [1:0]  spare_xna,	// NAND outputs
+    output [1:0]  spare_xno,	// NOR outputs
+    output [1:0]  spare_xmx,	// Mux outputs
+    output [1:0]  spare_xfq,	// Flop noninverted output
+    output [1:0]  spare_xfqn 	// Flop inverted output
 );
 
     wire [3:0] spare_logic_nc;
@@ -48,6 +49,10 @@ module spare_logic_block (
 
     wire [26:0] spare_logic1;
     wire [26:0] spare_logic0;
+    wire [26:0] spare_xz;
+
+    // Rename the logic0 outputs at the block pins.
+    assign spare_xz = spare_logic0;
 
     sky130_fd_sc_hd__conb_1 spare_logic_const [26:0] (
 	`ifdef USE_POWER_PINS