mirror of https://github.com/efabless/caravel.git
Merge pull request #245 from mo-hosni/buff_update
add buff_flash_clkrst
This commit is contained in:
Marwan Abbas
GitHub
commit
510d47a082
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@ -28,27 +28,44 @@ VIAS 3 ;
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- via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 85 65 65 + ROWCOL 1 4 ;
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- via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 90 60 100 65 + ROWCOL 1 4 ;
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END VIAS
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COMPONENTS 73 ;
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COMPONENTS 98 ;
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- ANTENNA_BUF\[0\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 4600 13600 ) S ;
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- ANTENNA_BUF\[10\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 25760 13600 ) S ;
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- ANTENNA_BUF\[11\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 23000 16320 ) FN ;
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- ANTENNA_BUF\[12\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 20240 16320 ) FN ;
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- ANTENNA_BUF\[13\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 25760 16320 ) FN ;
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- ANTENNA_BUF\[14\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 12880 5440 ) FN ;
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- ANTENNA_BUF\[1\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 12420 16320 ) FN ;
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- ANTENNA_BUF\[2\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 5980 10880 ) FN ;
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- ANTENNA_BUF\[3\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 16100 10880 ) FN ;
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- ANTENNA_BUF\[4\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 16100 16320 ) FN ;
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- ANTENNA_BUF\[5\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 16100 5440 ) FN ;
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- ANTENNA_BUF\[6\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 23000 13600 ) S ;
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- ANTENNA_BUF\[7\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 18860 5440 ) FN ;
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- ANTENNA_BUF\[8\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 25760 8160 ) S ;
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- ANTENNA_BUF\[9\]_A sky130_fd_sc_hd__diode_2 + PLACED ( 34500 10880 ) FN ;
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- BUF\[0\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 5520 5440 ) N ;
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- BUF\[10\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 8160 ) FS ;
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- BUF\[11\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 13600 ) FS ;
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- BUF\[12\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 5440 ) FN ;
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- BUF\[13\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 16320 ) FN ;
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- BUF\[14\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 21620 5440 ) FN ;
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- BUF\[1\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 5520 16320 ) N ;
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- BUF\[2\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 4600 8160 ) S ;
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- BUF\[3\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 9200 13600 ) FS ;
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- BUF\[12\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 5440 ) N ;
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- BUF\[13\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 16320 ) N ;
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- BUF\[14\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 21620 5440 ) N ;
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- BUF\[1\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 5520 16320 ) FN ;
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- BUF\[2\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 4600 8160 ) FS ;
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- BUF\[3\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 9200 13600 ) S ;
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- BUF\[4\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 8740 10880 ) FN ;
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- BUF\[5\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 11500 8160 ) S ;
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- BUF\[6\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 16100 13600 ) FS ;
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- BUF\[6\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 16100 13600 ) S ;
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- BUF\[7\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 18400 8160 ) FS ;
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- BUF\[8\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 20700 10880 ) N ;
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- BUF\[9\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 27600 10880 ) N ;
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- FILLER_0_19 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 10580 5440 ) N ;
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- FILLER_0_27 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14260 5440 ) N ;
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- FILLER_0_29 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 15180 5440 ) N ;
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- BUF\[8\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 20700 10880 ) FN ;
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- BUF\[9\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 27600 10880 ) FN ;
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- FILLER_0_19 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 10580 5440 ) N ;
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- FILLER_0_23 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 12420 5440 ) N ;
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- FILLER_0_26 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 13800 5440 ) N ;
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- FILLER_0_29 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 15180 5440 ) N ;
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- FILLER_0_3 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 3220 5440 ) N ;
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- FILLER_0_41 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 20700 5440 ) N ;
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- FILLER_0_33 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 17020 5440 ) N ;
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- FILLER_0_39 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 19780 5440 ) N ;
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- FILLER_0_54 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26680 5440 ) N ;
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- FILLER_0_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 5440 ) N ;
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- FILLER_0_7 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5060 5440 ) N ;
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@ -57,30 +74,38 @@ COMPONENTS 73 ;
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- FILLER_1_17 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 9660 8160 ) FS ;
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- FILLER_1_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 3220 8160 ) FS ;
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- FILLER_1_32 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 16560 8160 ) FS ;
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- FILLER_1_47 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 23460 8160 ) FS ;
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- FILLER_1_55 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 27140 8160 ) FS ;
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- FILLER_1_47 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 23460 8160 ) FS ;
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- FILLER_1_51 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 25300 8160 ) FS ;
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- FILLER_1_54 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26680 8160 ) FS ;
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- FILLER_1_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 8160 ) FS ;
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- FILLER_1_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 8160 ) FS ;
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- FILLER_1_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 35880 8160 ) FS ;
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- FILLER_2_11 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 6900 10880 ) N ;
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- FILLER_2_26 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 13800 10880 ) N ;
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- FILLER_2_29 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 15180 10880 ) N ;
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- FILLER_2_3 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 3220 10880 ) N ;
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- FILLER_2_29 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 15180 10880 ) N ;
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- FILLER_2_3 sky130_fd_sc_hd__decap_6 + SOURCE DIST + PLACED ( 3220 10880 ) N ;
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- FILLER_2_33 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 17020 10880 ) N ;
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- FILLER_2_52 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 25760 10880 ) N ;
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- FILLER_2_67 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 32660 10880 ) N ;
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- FILLER_3_15 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8740 13600 ) FS ;
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- FILLER_2_67 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 32660 10880 ) N ;
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- FILLER_2_73 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 35420 10880 ) N ;
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- FILLER_3_27 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 14260 13600 ) FS ;
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- FILLER_3_3 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 3220 13600 ) FS ;
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- FILLER_3_42 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 21160 13600 ) FS ;
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- FILLER_3_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 3220 13600 ) FS ;
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- FILLER_3_42 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 21160 13600 ) FS ;
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- FILLER_3_48 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 23920 13600 ) FS ;
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- FILLER_3_54 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26680 13600 ) FS ;
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- FILLER_3_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 13600 ) FS ;
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- FILLER_3_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 13600 ) FS ;
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- FILLER_3_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 35880 13600 ) FS ;
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- FILLER_4_19 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 10580 16320 ) N ;
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- FILLER_4_27 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14260 16320 ) N ;
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- FILLER_4_29 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 15180 16320 ) N ;
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- FILLER_3_8 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 5520 13600 ) FS ;
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- FILLER_4_19 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 10580 16320 ) N ;
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- FILLER_4_25 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 13340 16320 ) N ;
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- FILLER_4_29 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 15180 16320 ) N ;
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- FILLER_4_3 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 3220 16320 ) N ;
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- FILLER_4_41 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 20700 16320 ) N ;
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- FILLER_4_53 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26220 16320 ) N ;
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- FILLER_4_33 sky130_fd_sc_hd__decap_6 + SOURCE DIST + PLACED ( 17020 16320 ) N ;
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- FILLER_4_39 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 19780 16320 ) N ;
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- FILLER_4_42 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 21160 16320 ) N ;
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- FILLER_4_48 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 23920 16320 ) N ;
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- FILLER_4_54 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26680 16320 ) N ;
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- FILLER_4_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 16320 ) N ;
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- FILLER_4_7 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5060 16320 ) N ;
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- FILLER_4_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 16320 ) N ;
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@ -118,123 +143,123 @@ PINS 32 ;
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+ LAYER met4 ( -18730 -7040 ) ( -17130 7040 )
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+ LAYER met4 ( -27695 -7040 ) ( -26095 7040 )
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+ FIXED ( 33215 12240 ) N ;
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- in_n[0] + NET in_n[0] + DIRECTION INPUT + USE SIGNAL
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- in_e[0] + NET in_e[0] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 10810 23000 ) N ;
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- in_n[10] + NET in_n[10] + DIRECTION INPUT + USE SIGNAL
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- in_e[10] + NET in_e[10] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 33810 23000 ) N ;
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- in_n[11] + NET in_n[11] + DIRECTION INPUT + USE SIGNAL
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- in_e[11] + NET in_e[11] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 36110 23000 ) N ;
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- in_n[1] + NET in_n[1] + DIRECTION INPUT + USE SIGNAL
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- in_e[1] + NET in_e[1] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 13110 23000 ) N ;
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- in_n[2] + NET in_n[2] + DIRECTION INPUT + USE SIGNAL
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- in_e[2] + NET in_e[2] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 15410 23000 ) N ;
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- in_n[3] + NET in_n[3] + DIRECTION INPUT + USE SIGNAL
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- in_e[3] + NET in_e[3] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 17710 23000 ) N ;
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- in_n[4] + NET in_n[4] + DIRECTION INPUT + USE SIGNAL
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- in_e[4] + NET in_e[4] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 20010 23000 ) N ;
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- in_n[5] + NET in_n[5] + DIRECTION INPUT + USE SIGNAL
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- in_e[5] + NET in_e[5] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 22310 23000 ) N ;
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- in_n[6] + NET in_n[6] + DIRECTION INPUT + USE SIGNAL
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- in_e[6] + NET in_e[6] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 24610 23000 ) N ;
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- in_n[7] + NET in_n[7] + DIRECTION INPUT + USE SIGNAL
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- in_e[7] + NET in_e[7] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 26910 23000 ) N ;
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- in_n[8] + NET in_n[8] + DIRECTION INPUT + USE SIGNAL
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- in_e[8] + NET in_e[8] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
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+ PLACED ( 29210 23000 ) N ;
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- in_n[9] + NET in_n[9] + DIRECTION INPUT + USE SIGNAL
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- in_e[9] + NET in_e[9] + DIRECTION INPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
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+ PLACED ( 31510 23000 ) N ;
|
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- in_s[0] + NET in_s[0] + DIRECTION INPUT + USE SIGNAL
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- in_w[0] + NET in_w[0] + DIRECTION INPUT + USE SIGNAL
|
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+ PORT
|
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 3910 2000 ) N ;
|
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- in_s[1] + NET in_s[1] + DIRECTION INPUT + USE SIGNAL
|
||||
- in_w[1] + NET in_w[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
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+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 6210 2000 ) N ;
|
||||
- in_s[2] + NET in_s[2] + DIRECTION INPUT + USE SIGNAL
|
||||
- in_w[2] + NET in_w[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 8510 2000 ) N ;
|
||||
- out_n[0] + NET out_n[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_e[0] + NET out_e[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 3910 23000 ) N ;
|
||||
- out_n[1] + NET out_n[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_e[1] + NET out_e[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 6210 23000 ) N ;
|
||||
- out_n[2] + NET out_n[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_e[2] + NET out_e[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 8510 23000 ) N ;
|
||||
- out_s[0] + NET out_s[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[0] + NET out_w[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 10810 2000 ) N ;
|
||||
- out_s[10] + NET out_s[10] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[10] + NET out_w[10] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 33810 2000 ) N ;
|
||||
- out_s[11] + NET out_s[11] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[11] + NET out_w[11] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 36110 2000 ) N ;
|
||||
- out_s[1] + NET out_s[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[1] + NET out_w[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 13110 2000 ) N ;
|
||||
- out_s[2] + NET out_s[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[2] + NET out_w[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 15410 2000 ) N ;
|
||||
- out_s[3] + NET out_s[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[3] + NET out_w[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 17710 2000 ) N ;
|
||||
- out_s[4] + NET out_s[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[4] + NET out_w[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 20010 2000 ) N ;
|
||||
- out_s[5] + NET out_s[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[5] + NET out_w[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 22310 2000 ) N ;
|
||||
- out_s[6] + NET out_s[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[6] + NET out_w[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 24610 2000 ) N ;
|
||||
- out_s[7] + NET out_s[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[7] + NET out_w[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 26910 2000 ) N ;
|
||||
- out_s[8] + NET out_s[8] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[8] + NET out_w[8] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 29210 2000 ) N ;
|
||||
- out_s[9] + NET out_s[9] + DIRECTION OUTPUT + USE SIGNAL
|
||||
- out_w[9] + NET out_w[9] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
|
||||
+ PLACED ( 31510 2000 ) N ;
|
||||
|
|
@ -378,146 +403,210 @@ SPECIALNETS 2 ;
|
|||
NEW met1 0 + SHAPE STRIPE ( 6320 8160 ) via2_3_1600_480_1_5_320_320 ;
|
||||
END SPECIALNETS
|
||||
NETS 30 ;
|
||||
- in_n[0] ( PIN in_n[0] ) ( BUF\[3\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 9430 15470 ) ( * 21420 )
|
||||
NEW met2 ( 9430 21420 ) ( 10810 * 0 )
|
||||
NEW li1 ( 9430 15470 ) L1M1_PR_MR
|
||||
NEW met1 ( 9430 15470 ) M1M2_PR
|
||||
NEW met1 ( 9430 15470 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_n[10] ( PIN in_n[10] ) ( BUF\[13\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 33810 17510 ) ( 34270 * )
|
||||
NEW met2 ( 34270 17510 ) ( * 20060 )
|
||||
NEW met2 ( 33810 20060 ) ( 34270 * )
|
||||
NEW met2 ( 33810 20060 ) ( * 21420 0 )
|
||||
NEW li1 ( 33810 17510 ) L1M1_PR_MR
|
||||
NEW met1 ( 34270 17510 ) M1M2_PR ;
|
||||
- in_n[11] ( PIN in_n[11] ) ( BUF\[14\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 26450 6630 ) ( 31510 * )
|
||||
NEW met1 ( 31510 6630 ) ( * 6970 )
|
||||
NEW met1 ( 31510 6970 ) ( 34270 * )
|
||||
NEW met1 ( 34270 6630 ) ( * 6970 )
|
||||
NEW met1 ( 34270 6630 ) ( 36110 * )
|
||||
NEW met2 ( 36110 6630 ) ( * 21420 0 )
|
||||
NEW li1 ( 26450 6630 ) L1M1_PR_MR
|
||||
NEW met1 ( 36110 6630 ) M1M2_PR ;
|
||||
- in_n[1] ( PIN in_n[1] ) ( BUF\[4\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 13570 12070 ) ( * 21420 )
|
||||
NEW met2 ( 13110 21420 0 ) ( 13570 * )
|
||||
- in_e[0] ( PIN in_e[0] ) ( ANTENNA_BUF\[3\]_A DIODE ) ( BUF\[3\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 12650 15470 ) ( 14030 * )
|
||||
NEW met2 ( 12650 15470 ) ( * 21420 )
|
||||
NEW met2 ( 10810 21420 0 ) ( 12650 * )
|
||||
NEW met1 ( 14030 13090 ) ( 16330 * )
|
||||
NEW met2 ( 14030 13090 ) ( * 15470 )
|
||||
NEW li1 ( 14030 15470 ) L1M1_PR_MR
|
||||
NEW met1 ( 12650 15470 ) M1M2_PR
|
||||
NEW li1 ( 16330 13090 ) L1M1_PR_MR
|
||||
NEW met1 ( 14030 13090 ) M1M2_PR
|
||||
NEW met1 ( 14030 15470 ) M1M2_PR
|
||||
NEW met1 ( 14030 15470 ) RECT ( -595 -70 0 70 ) ;
|
||||
- in_e[10] ( PIN in_e[10] ) ( ANTENNA_BUF\[13\]_A DIODE ) ( BUF\[13\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 29210 17510 ) ( 31970 * )
|
||||
NEW met2 ( 31970 17510 ) ( * 21420 )
|
||||
NEW met2 ( 31970 21420 ) ( 33810 * 0 )
|
||||
NEW met1 ( 26450 17510 ) ( 29210 * )
|
||||
NEW li1 ( 29210 17510 ) L1M1_PR_MR
|
||||
NEW met1 ( 31970 17510 ) M1M2_PR
|
||||
NEW li1 ( 26450 17510 ) L1M1_PR_MR ;
|
||||
- in_e[11] ( PIN in_e[11] ) ( ANTENNA_BUF\[14\]_A DIODE ) ( BUF\[14\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 21850 5950 ) ( * 6290 )
|
||||
NEW met1 ( 21850 5950 ) ( 34730 * )
|
||||
NEW met2 ( 34730 5950 ) ( * 21420 )
|
||||
NEW met2 ( 34730 21420 ) ( 36110 * 0 )
|
||||
NEW met1 ( 13570 6290 ) ( 21850 * )
|
||||
NEW li1 ( 21850 6290 ) L1M1_PR_MR
|
||||
NEW met1 ( 34730 5950 ) M1M2_PR
|
||||
NEW li1 ( 13570 6290 ) L1M1_PR_MR ;
|
||||
- in_e[1] ( PIN in_e[1] ) ( ANTENNA_BUF\[4\]_A DIODE ) ( BUF\[4\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 13110 18530 ) ( 16330 * )
|
||||
NEW met2 ( 13110 18530 ) ( * 21420 0 )
|
||||
NEW met1 ( 13110 12070 ) ( 13570 * )
|
||||
NEW met2 ( 13110 12070 ) ( * 18530 )
|
||||
NEW li1 ( 16330 18530 ) L1M1_PR_MR
|
||||
NEW met1 ( 13110 18530 ) M1M2_PR
|
||||
NEW li1 ( 13570 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 13570 12070 ) M1M2_PR
|
||||
NEW met1 ( 13570 12070 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_n[2] ( PIN in_n[2] ) ( BUF\[5\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 14030 10030 ) ( 16330 * )
|
||||
NEW met2 ( 14030 10030 ) ( * 21420 )
|
||||
NEW met2 ( 14030 21420 ) ( 15410 * 0 )
|
||||
NEW met1 ( 13110 12070 ) M1M2_PR ;
|
||||
- in_e[2] ( PIN in_e[2] ) ( ANTENNA_BUF\[5\]_A DIODE ) ( BUF\[5\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 16330 10030 ) ( * 21420 )
|
||||
NEW met2 ( 15410 21420 0 ) ( 16330 * )
|
||||
NEW met2 ( 16330 7650 ) ( * 10030 )
|
||||
NEW li1 ( 16330 10030 ) L1M1_PR_MR
|
||||
NEW met1 ( 14030 10030 ) M1M2_PR ;
|
||||
- in_n[3] ( PIN in_n[3] ) ( BUF\[6\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 16330 15470 ) ( * 21420 )
|
||||
NEW met2 ( 16330 21420 ) ( 17710 * 0 )
|
||||
NEW li1 ( 16330 15470 ) L1M1_PR_MR
|
||||
NEW met1 ( 16330 15470 ) M1M2_PR
|
||||
NEW met1 ( 16330 15470 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_n[4] ( PIN in_n[4] ) ( BUF\[7\] A ) + USE SIGNAL
|
||||
NEW met1 ( 16330 10030 ) M1M2_PR
|
||||
NEW li1 ( 16330 7650 ) L1M1_PR_MR
|
||||
NEW met1 ( 16330 7650 ) M1M2_PR
|
||||
NEW met1 ( 16330 10030 ) RECT ( -355 -70 0 70 )
|
||||
NEW met1 ( 16330 7650 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_e[3] ( PIN in_e[3] ) ( ANTENNA_BUF\[6\]_A DIODE ) ( BUF\[6\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 18170 15470 ) ( 20930 * )
|
||||
NEW met2 ( 18170 15470 ) ( * 21420 )
|
||||
NEW met2 ( 17710 21420 0 ) ( 18170 * )
|
||||
NEW met1 ( 20930 15470 ) ( 23230 * )
|
||||
NEW li1 ( 20930 15470 ) L1M1_PR_MR
|
||||
NEW met1 ( 18170 15470 ) M1M2_PR
|
||||
NEW li1 ( 23230 15470 ) L1M1_PR_MR ;
|
||||
- in_e[4] ( PIN in_e[4] ) ( ANTENNA_BUF\[7\]_A DIODE ) ( BUF\[7\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 18630 10030 ) ( * 21420 )
|
||||
NEW met2 ( 18630 21420 ) ( 20010 * 0 )
|
||||
NEW met1 ( 18630 7650 ) ( 19090 * )
|
||||
NEW met2 ( 18630 7650 ) ( * 10030 )
|
||||
NEW li1 ( 18630 10030 ) L1M1_PR_MR
|
||||
NEW met1 ( 18630 10030 ) M1M2_PR
|
||||
NEW li1 ( 19090 7650 ) L1M1_PR_MR
|
||||
NEW met1 ( 18630 7650 ) M1M2_PR
|
||||
NEW met1 ( 18630 10030 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_n[5] ( PIN in_n[5] ) ( BUF\[8\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 20930 12070 ) ( * 21420 )
|
||||
NEW met2 ( 20930 21420 ) ( 22310 * 0 )
|
||||
NEW li1 ( 20930 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 20930 12070 ) M1M2_PR
|
||||
NEW met1 ( 20930 12070 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_n[6] ( PIN in_n[6] ) ( BUF\[9\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 26450 12070 ) ( 27830 * )
|
||||
NEW met2 ( 26450 12070 ) ( * 21420 )
|
||||
NEW met2 ( 24610 21420 0 ) ( 26450 * )
|
||||
NEW li1 ( 27830 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 26450 12070 ) M1M2_PR ;
|
||||
- in_n[7] ( PIN in_n[7] ) ( BUF\[10\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 26910 10030 ) ( 29210 * )
|
||||
NEW met2 ( 26910 10030 ) ( * 21420 0 )
|
||||
- in_e[5] ( PIN in_e[5] ) ( ANTENNA_BUF\[8\]_A DIODE ) ( BUF\[8\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 23230 12070 ) ( 25530 * )
|
||||
NEW met2 ( 23230 12070 ) ( * 21420 )
|
||||
NEW met2 ( 22310 21420 0 ) ( 23230 * )
|
||||
NEW met2 ( 25990 10370 ) ( * 12070 )
|
||||
NEW met1 ( 25530 12070 ) ( 25990 * )
|
||||
NEW li1 ( 25530 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 23230 12070 ) M1M2_PR
|
||||
NEW li1 ( 25990 10370 ) L1M1_PR_MR
|
||||
NEW met1 ( 25990 10370 ) M1M2_PR
|
||||
NEW met1 ( 25990 12070 ) M1M2_PR
|
||||
NEW met1 ( 25990 10370 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_e[6] ( PIN in_e[6] ) ( ANTENNA_BUF\[9\]_A DIODE ) ( BUF\[9\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 32430 12070 ) ( * 12410 )
|
||||
NEW met1 ( 25990 12410 ) ( 32430 * )
|
||||
NEW met1 ( 25990 12410 ) ( * 12750 )
|
||||
NEW met2 ( 25990 12750 ) ( * 21420 )
|
||||
NEW met2 ( 24610 21420 0 ) ( 25990 * )
|
||||
NEW met1 ( 32430 12410 ) ( 34730 * )
|
||||
NEW li1 ( 32430 12070 ) L1M1_PR_MR
|
||||
NEW met1 ( 25990 12750 ) M1M2_PR
|
||||
NEW li1 ( 34730 12410 ) L1M1_PR_MR ;
|
||||
- in_e[7] ( PIN in_e[7] ) ( ANTENNA_BUF\[10\]_A DIODE ) ( BUF\[10\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 26450 15810 ) ( * 21420 )
|
||||
NEW met2 ( 26450 21420 ) ( 26910 * 0 )
|
||||
NEW met1 ( 27830 10030 ) ( 29210 * )
|
||||
NEW met2 ( 27830 9860 ) ( * 10030 )
|
||||
NEW met2 ( 27370 9860 ) ( 27830 * )
|
||||
NEW met2 ( 27370 9860 ) ( * 13940 )
|
||||
NEW met2 ( 26450 13940 ) ( 27370 * )
|
||||
NEW met2 ( 26450 13940 ) ( * 15810 )
|
||||
NEW li1 ( 26450 15810 ) L1M1_PR_MR
|
||||
NEW met1 ( 26450 15810 ) M1M2_PR
|
||||
NEW li1 ( 29210 10030 ) L1M1_PR_MR
|
||||
NEW met1 ( 26910 10030 ) M1M2_PR ;
|
||||
- in_n[8] ( PIN in_n[8] ) ( BUF\[11\] A ) + USE SIGNAL
|
||||
NEW met1 ( 27830 10030 ) M1M2_PR
|
||||
NEW met1 ( 26450 15810 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_e[8] ( PIN in_e[8] ) ( ANTENNA_BUF\[11\]_A DIODE ) ( BUF\[11\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 29210 15470 ) ( 30130 * )
|
||||
NEW met2 ( 30130 15470 ) ( * 18020 )
|
||||
NEW met2 ( 29210 18020 ) ( 30130 * )
|
||||
NEW met2 ( 29210 18020 ) ( * 21420 0 )
|
||||
NEW met2 ( 30130 15470 ) ( * 17340 )
|
||||
NEW met2 ( 29210 17340 ) ( 30130 * )
|
||||
NEW met2 ( 29210 17340 ) ( * 21420 0 )
|
||||
NEW met1 ( 23690 18190 ) ( 29210 * )
|
||||
NEW li1 ( 29210 15470 ) L1M1_PR_MR
|
||||
NEW met1 ( 30130 15470 ) M1M2_PR ;
|
||||
- in_n[9] ( PIN in_n[9] ) ( BUF\[12\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 31970 6630 ) ( 33810 * )
|
||||
NEW met2 ( 31970 6630 ) ( * 21420 )
|
||||
NEW met2 ( 31510 21420 0 ) ( 31970 * )
|
||||
NEW li1 ( 33810 6630 ) L1M1_PR_MR
|
||||
NEW met1 ( 31970 6630 ) M1M2_PR ;
|
||||
- in_s[0] ( PIN in_s[0] ) ( BUF\[0\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 3910 3740 0 ) ( * 6290 )
|
||||
NEW met1 ( 3910 6290 ) ( 5750 * )
|
||||
NEW met1 ( 3910 6290 ) M1M2_PR
|
||||
NEW li1 ( 5750 6290 ) L1M1_PR_MR ;
|
||||
- in_s[1] ( PIN in_s[1] ) ( BUF\[1\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 6210 3740 0 ) ( * 7140 )
|
||||
NEW met2 ( 5290 7140 ) ( 6210 * )
|
||||
NEW met2 ( 5290 7140 ) ( * 17170 )
|
||||
NEW met1 ( 5290 17170 ) ( 5750 * )
|
||||
NEW met1 ( 5290 17170 ) M1M2_PR
|
||||
NEW li1 ( 5750 17170 ) L1M1_PR_MR ;
|
||||
- in_s[2] ( PIN in_s[2] ) ( BUF\[2\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 8510 3740 0 ) ( * 9690 )
|
||||
NEW met1 ( 8510 9690 ) ( 9430 * )
|
||||
NEW met1 ( 8510 9690 ) M1M2_PR
|
||||
NEW li1 ( 9430 9690 ) L1M1_PR_MR ;
|
||||
- out_n[0] ( PIN out_n[0] ) ( BUF\[0\] X ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 4830 6630 ) ( 9430 * )
|
||||
NEW met2 ( 4830 6630 ) ( * 21420 )
|
||||
NEW met1 ( 30130 15470 ) M1M2_PR
|
||||
NEW li1 ( 23690 18190 ) L1M1_PR_MR
|
||||
NEW met1 ( 29210 18190 ) M1M2_PR
|
||||
NEW met2 ( 29210 18190 ) RECT ( -70 -485 70 0 ) ;
|
||||
- in_e[9] ( PIN in_e[9] ) ( ANTENNA_BUF\[12\]_A DIODE ) ( BUF\[12\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 20930 18530 ) ( 31510 * )
|
||||
NEW met2 ( 31510 18530 ) ( * 21420 0 )
|
||||
NEW met1 ( 29210 6290 ) ( 30590 * )
|
||||
NEW met2 ( 30590 6290 ) ( * 18530 )
|
||||
NEW li1 ( 20930 18530 ) L1M1_PR_MR
|
||||
NEW met1 ( 31510 18530 ) M1M2_PR
|
||||
NEW li1 ( 29210 6290 ) L1M1_PR_MR
|
||||
NEW met1 ( 30590 6290 ) M1M2_PR
|
||||
NEW met1 ( 30590 18530 ) M1M2_PR
|
||||
NEW met1 ( 30590 18530 ) RECT ( -595 -70 0 70 ) ;
|
||||
- in_w[0] ( PIN in_w[0] ) ( ANTENNA_BUF\[0\]_A DIODE ) ( BUF\[0\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 5290 6630 ) ( 5750 * )
|
||||
NEW met2 ( 5290 6630 ) ( * 14110 )
|
||||
NEW met2 ( 3910 3740 0 ) ( * 6630 )
|
||||
NEW met1 ( 3910 6630 ) ( 5290 * )
|
||||
NEW li1 ( 5750 6630 ) L1M1_PR_MR
|
||||
NEW met1 ( 5290 6630 ) M1M2_PR
|
||||
NEW li1 ( 5290 14110 ) L1M1_PR_MR
|
||||
NEW met1 ( 5290 14110 ) M1M2_PR
|
||||
NEW met1 ( 3910 6630 ) M1M2_PR
|
||||
NEW met1 ( 5290 14110 ) RECT ( -355 -70 0 70 ) ;
|
||||
- in_w[1] ( PIN in_w[1] ) ( ANTENNA_BUF\[1\]_A DIODE ) ( BUF\[1\] A ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 4370 17170 ) ( 10350 * )
|
||||
NEW met2 ( 4370 3740 ) ( * 17170 )
|
||||
NEW met2 ( 4370 3740 ) ( 5750 * )
|
||||
NEW met2 ( 5750 3740 ) ( * 4420 )
|
||||
NEW met2 ( 5750 4420 ) ( 6210 * )
|
||||
NEW met2 ( 6210 3740 0 ) ( * 4420 )
|
||||
NEW met1 ( 10350 17170 ) ( 12650 * )
|
||||
NEW li1 ( 10350 17170 ) L1M1_PR_MR
|
||||
NEW met1 ( 4370 17170 ) M1M2_PR
|
||||
NEW li1 ( 12650 17170 ) L1M1_PR_MR ;
|
||||
- in_w[2] ( PIN in_w[2] ) ( ANTENNA_BUF\[2\]_A DIODE ) ( BUF\[2\] A ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 6670 9180 ) ( * 11390 )
|
||||
NEW met2 ( 6670 9180 ) ( 7590 * )
|
||||
NEW met2 ( 7590 8500 ) ( * 9180 )
|
||||
NEW met2 ( 7590 8500 ) ( 8510 * )
|
||||
NEW met2 ( 8510 3740 0 ) ( * 8500 )
|
||||
NEW met1 ( 4830 9690 ) ( 6670 * )
|
||||
NEW li1 ( 6670 11390 ) L1M1_PR_MR
|
||||
NEW met1 ( 6670 11390 ) M1M2_PR
|
||||
NEW li1 ( 4830 9690 ) L1M1_PR_MR
|
||||
NEW met1 ( 6670 9690 ) M1M2_PR
|
||||
NEW met1 ( 6670 11390 ) RECT ( -355 -70 0 70 )
|
||||
NEW met2 ( 6670 9690 ) RECT ( -70 -485 70 0 ) ;
|
||||
- out_e[0] ( PIN out_e[0] ) ( BUF\[0\] X ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 4830 6290 ) ( 9430 * )
|
||||
NEW met2 ( 4830 6290 ) ( * 21420 )
|
||||
NEW met2 ( 3910 21420 0 ) ( 4830 * )
|
||||
NEW li1 ( 9430 6630 ) L1M1_PR_MR
|
||||
NEW met1 ( 4830 6630 ) M1M2_PR ;
|
||||
- out_n[1] ( PIN out_n[1] ) ( BUF\[1\] X ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 7590 17850 ) ( 9430 * )
|
||||
NEW li1 ( 9430 6290 ) L1M1_PR_MR
|
||||
NEW met1 ( 4830 6290 ) M1M2_PR ;
|
||||
- out_e[1] ( PIN out_e[1] ) ( BUF\[1\] X ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 6670 17850 ) ( 7590 * )
|
||||
NEW met2 ( 7590 17850 ) ( * 21420 )
|
||||
NEW met2 ( 6210 21420 0 ) ( 7590 * )
|
||||
NEW li1 ( 9430 17850 ) L1M1_PR_MR
|
||||
NEW li1 ( 6670 17850 ) L1M1_PR_MR
|
||||
NEW met1 ( 7590 17850 ) M1M2_PR ;
|
||||
- out_n[2] ( PIN out_n[2] ) ( BUF\[2\] X ) + USE SIGNAL
|
||||
+ ROUTED met1 ( 5750 10030 ) ( 8050 * )
|
||||
NEW met2 ( 8050 10030 ) ( * 21420 )
|
||||
NEW met2 ( 8050 21420 ) ( 8510 * 0 )
|
||||
NEW li1 ( 5750 10030 ) L1M1_PR_MR
|
||||
NEW met1 ( 8050 10030 ) M1M2_PR ;
|
||||
- out_s[0] ( PIN out_s[0] ) ( BUF\[3\] X ) + USE SIGNAL
|
||||
- out_e[2] ( PIN out_e[2] ) ( BUF\[2\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 8510 10030 ) ( * 21420 0 )
|
||||
NEW li1 ( 8510 10030 ) L1M1_PR_MR
|
||||
NEW met1 ( 8510 10030 ) M1M2_PR
|
||||
NEW met1 ( 8510 10030 ) RECT ( -355 -70 0 70 ) ;
|
||||
- out_w[0] ( PIN out_w[0] ) ( BUF\[3\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 10810 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 10810 4420 ) ( 11270 * )
|
||||
NEW met2 ( 11270 3740 ) ( * 4420 )
|
||||
NEW met2 ( 11270 3740 ) ( 12190 * )
|
||||
NEW met2 ( 12190 3740 ) ( * 14790 )
|
||||
NEW met1 ( 12190 14790 ) ( 13110 * )
|
||||
NEW met1 ( 12190 14790 ) M1M2_PR
|
||||
NEW li1 ( 13110 14790 ) L1M1_PR_MR ;
|
||||
- out_s[10] ( PIN out_s[10] ) ( BUF\[13\] X ) + USE SIGNAL
|
||||
NEW met2 ( 10350 4420 ) ( 10810 * )
|
||||
NEW met2 ( 10350 3740 ) ( * 4420 )
|
||||
NEW met2 ( 9430 3740 ) ( 10350 * )
|
||||
NEW met2 ( 9430 3740 ) ( * 14790 )
|
||||
NEW met1 ( 9430 14790 ) ( 9890 * )
|
||||
NEW met1 ( 9430 14790 ) M1M2_PR
|
||||
NEW li1 ( 9890 14790 ) L1M1_PR_MR ;
|
||||
- out_w[10] ( PIN out_w[10] ) ( BUF\[13\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 33810 3740 0 ) ( * 7140 )
|
||||
NEW met2 ( 33810 7140 ) ( 34270 * )
|
||||
NEW met2 ( 34270 7140 ) ( * 16830 )
|
||||
NEW met1 ( 34270 16830 ) ( * 17170 )
|
||||
NEW met1 ( 30130 17170 ) ( 34270 * )
|
||||
NEW met1 ( 34270 16830 ) M1M2_PR
|
||||
NEW li1 ( 30130 17170 ) L1M1_PR_MR ;
|
||||
- out_s[11] ( PIN out_s[11] ) ( BUF\[14\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 36110 3740 0 ) ( * 5950 )
|
||||
NEW met1 ( 22770 5950 ) ( 36110 * )
|
||||
NEW met1 ( 22770 5950 ) ( * 6290 )
|
||||
NEW met1 ( 36110 5950 ) M1M2_PR
|
||||
NEW li1 ( 22770 6290 ) L1M1_PR_MR ;
|
||||
- out_s[1] ( PIN out_s[1] ) ( BUF\[4\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 13110 3740 0 ) ( * 11730 )
|
||||
NEW met2 ( 34270 7140 ) ( * 17170 )
|
||||
NEW met1 ( 33350 17170 ) ( 34270 * )
|
||||
NEW met1 ( 34270 17170 ) M1M2_PR
|
||||
NEW li1 ( 33350 17170 ) L1M1_PR_MR ;
|
||||
- out_w[11] ( PIN out_w[11] ) ( BUF\[14\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 36110 3740 0 ) ( * 6630 )
|
||||
NEW met1 ( 25990 6630 ) ( 36110 * )
|
||||
NEW met1 ( 36110 6630 ) M1M2_PR
|
||||
NEW li1 ( 25990 6630 ) L1M1_PR_MR ;
|
||||
- out_w[1] ( PIN out_w[1] ) ( BUF\[4\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 13110 3740 0 ) ( * 11390 )
|
||||
NEW met1 ( 13110 11390 ) ( * 11730 )
|
||||
NEW met1 ( 9890 11730 ) ( 13110 * )
|
||||
NEW met1 ( 13110 11730 ) M1M2_PR
|
||||
NEW met1 ( 13110 11390 ) M1M2_PR
|
||||
NEW li1 ( 9890 11730 ) L1M1_PR_MR ;
|
||||
- out_s[2] ( PIN out_s[2] ) ( BUF\[5\] X ) + USE SIGNAL
|
||||
- out_w[2] ( PIN out_w[2] ) ( BUF\[5\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 15410 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 14950 4420 ) ( 15410 * )
|
||||
NEW met2 ( 14950 3740 ) ( * 4420 )
|
||||
|
|
@ -526,46 +615,48 @@ NETS 30 ;
|
|||
NEW met1 ( 12650 9350 ) ( 14030 * )
|
||||
NEW met1 ( 14030 9350 ) M1M2_PR
|
||||
NEW li1 ( 12650 9350 ) L1M1_PR_MR ;
|
||||
- out_s[3] ( PIN out_s[3] ) ( BUF\[6\] X ) + USE SIGNAL
|
||||
- out_w[3] ( PIN out_w[3] ) ( BUF\[6\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 17710 3740 0 ) ( * 14790 )
|
||||
NEW met1 ( 17710 14790 ) ( 20010 * )
|
||||
NEW met1 ( 17250 14790 ) ( 17710 * )
|
||||
NEW met1 ( 17710 14790 ) M1M2_PR
|
||||
NEW li1 ( 20010 14790 ) L1M1_PR_MR ;
|
||||
- out_s[4] ( PIN out_s[4] ) ( BUF\[7\] X ) + USE SIGNAL
|
||||
NEW li1 ( 17250 14790 ) L1M1_PR_MR ;
|
||||
- out_w[4] ( PIN out_w[4] ) ( BUF\[7\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 20010 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 20010 4420 ) ( 20930 * )
|
||||
NEW met2 ( 20930 4420 ) ( * 9350 )
|
||||
NEW met1 ( 20930 9350 ) ( 22310 * )
|
||||
NEW met1 ( 20930 9350 ) M1M2_PR
|
||||
NEW li1 ( 22310 9350 ) L1M1_PR_MR ;
|
||||
- out_s[5] ( PIN out_s[5] ) ( BUF\[8\] X ) + USE SIGNAL
|
||||
- out_w[5] ( PIN out_w[5] ) ( BUF\[8\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 22310 3740 0 ) ( * 11730 )
|
||||
NEW met1 ( 22310 11730 ) ( 24610 * )
|
||||
NEW met1 ( 21850 11730 ) ( 22310 * )
|
||||
NEW met1 ( 22310 11730 ) M1M2_PR
|
||||
NEW li1 ( 24610 11730 ) L1M1_PR_MR ;
|
||||
- out_s[6] ( PIN out_s[6] ) ( BUF\[9\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 24610 3740 0 ) ( * 5780 )
|
||||
NEW met2 ( 24610 5780 ) ( 25530 * )
|
||||
NEW met2 ( 25530 5780 ) ( * 11730 )
|
||||
NEW met1 ( 25530 11730 ) ( 31510 * )
|
||||
NEW met1 ( 25530 11730 ) M1M2_PR
|
||||
NEW li1 ( 31510 11730 ) L1M1_PR_MR ;
|
||||
- out_s[7] ( PIN out_s[7] ) ( BUF\[10\] X ) + USE SIGNAL
|
||||
NEW li1 ( 21850 11730 ) L1M1_PR_MR ;
|
||||
- out_w[6] ( PIN out_w[6] ) ( BUF\[9\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 24610 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 24610 4420 ) ( 25070 * )
|
||||
NEW met2 ( 25070 3740 ) ( * 4420 )
|
||||
NEW met2 ( 25070 3740 ) ( 26450 * )
|
||||
NEW met2 ( 26450 3740 ) ( * 11730 )
|
||||
NEW met1 ( 26450 11730 ) ( 28290 * )
|
||||
NEW met1 ( 26450 11730 ) M1M2_PR
|
||||
NEW li1 ( 28290 11730 ) L1M1_PR_MR ;
|
||||
- out_w[7] ( PIN out_w[7] ) ( BUF\[10\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 26910 3740 0 ) ( * 9350 )
|
||||
NEW met1 ( 26910 9350 ) ( 32890 * )
|
||||
NEW met1 ( 26910 9350 ) M1M2_PR
|
||||
NEW li1 ( 32890 9350 ) L1M1_PR_MR ;
|
||||
- out_s[8] ( PIN out_s[8] ) ( BUF\[11\] X ) + USE SIGNAL
|
||||
- out_w[8] ( PIN out_w[8] ) ( BUF\[11\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 29210 3740 0 ) ( * 4420 )
|
||||
NEW met2 ( 29210 4420 ) ( 30130 * )
|
||||
NEW met2 ( 30130 4420 ) ( * 14790 )
|
||||
NEW met1 ( 30130 14790 ) ( 32890 * )
|
||||
NEW met1 ( 30130 14790 ) M1M2_PR
|
||||
NEW li1 ( 32890 14790 ) L1M1_PR_MR ;
|
||||
- out_s[9] ( PIN out_s[9] ) ( BUF\[12\] X ) + USE SIGNAL
|
||||
- out_w[9] ( PIN out_w[9] ) ( BUF\[12\] X ) + USE SIGNAL
|
||||
+ ROUTED met2 ( 31510 3740 0 ) ( * 6290 )
|
||||
NEW met1 ( 30130 6290 ) ( 31510 * )
|
||||
NEW met1 ( 31510 6290 ) ( 32890 * )
|
||||
NEW met1 ( 31510 6290 ) M1M2_PR
|
||||
NEW li1 ( 30130 6290 ) L1M1_PR_MR ;
|
||||
NEW li1 ( 32890 6290 ) L1M1_PR_MR ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -47,246 +47,246 @@ MACRO buff_flash_clkrst
|
|||
RECT 32.415 5.200 34.015 19.280 ;
|
||||
END
|
||||
END VPWR
|
||||
PIN in_n[0]
|
||||
PIN in_e[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 10.670 21.000 10.950 25.000 ;
|
||||
END
|
||||
END in_n[0]
|
||||
PIN in_n[10]
|
||||
END in_e[0]
|
||||
PIN in_e[10]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 33.670 21.000 33.950 25.000 ;
|
||||
END
|
||||
END in_n[10]
|
||||
PIN in_n[11]
|
||||
END in_e[10]
|
||||
PIN in_e[11]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 35.970 21.000 36.250 25.000 ;
|
||||
END
|
||||
END in_n[11]
|
||||
PIN in_n[1]
|
||||
END in_e[11]
|
||||
PIN in_e[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 12.970 21.000 13.250 25.000 ;
|
||||
END
|
||||
END in_n[1]
|
||||
PIN in_n[2]
|
||||
END in_e[1]
|
||||
PIN in_e[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 15.270 21.000 15.550 25.000 ;
|
||||
END
|
||||
END in_n[2]
|
||||
PIN in_n[3]
|
||||
END in_e[2]
|
||||
PIN in_e[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 17.570 21.000 17.850 25.000 ;
|
||||
END
|
||||
END in_n[3]
|
||||
PIN in_n[4]
|
||||
END in_e[3]
|
||||
PIN in_e[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 19.870 21.000 20.150 25.000 ;
|
||||
END
|
||||
END in_n[4]
|
||||
PIN in_n[5]
|
||||
END in_e[4]
|
||||
PIN in_e[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 22.170 21.000 22.450 25.000 ;
|
||||
END
|
||||
END in_n[5]
|
||||
PIN in_n[6]
|
||||
END in_e[5]
|
||||
PIN in_e[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 24.470 21.000 24.750 25.000 ;
|
||||
END
|
||||
END in_n[6]
|
||||
PIN in_n[7]
|
||||
END in_e[6]
|
||||
PIN in_e[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 26.770 21.000 27.050 25.000 ;
|
||||
END
|
||||
END in_n[7]
|
||||
PIN in_n[8]
|
||||
END in_e[7]
|
||||
PIN in_e[8]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 29.070 21.000 29.350 25.000 ;
|
||||
END
|
||||
END in_n[8]
|
||||
PIN in_n[9]
|
||||
END in_e[8]
|
||||
PIN in_e[9]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 31.370 21.000 31.650 25.000 ;
|
||||
END
|
||||
END in_n[9]
|
||||
PIN in_s[0]
|
||||
END in_e[9]
|
||||
PIN in_w[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 3.770 0.000 4.050 4.000 ;
|
||||
END
|
||||
END in_s[0]
|
||||
PIN in_s[1]
|
||||
END in_w[0]
|
||||
PIN in_w[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 6.070 0.000 6.350 4.000 ;
|
||||
END
|
||||
END in_s[1]
|
||||
PIN in_s[2]
|
||||
END in_w[1]
|
||||
PIN in_w[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 8.370 0.000 8.650 4.000 ;
|
||||
END
|
||||
END in_s[2]
|
||||
PIN out_n[0]
|
||||
END in_w[2]
|
||||
PIN out_e[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 3.770 21.000 4.050 25.000 ;
|
||||
END
|
||||
END out_n[0]
|
||||
PIN out_n[1]
|
||||
END out_e[0]
|
||||
PIN out_e[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 6.070 21.000 6.350 25.000 ;
|
||||
END
|
||||
END out_n[1]
|
||||
PIN out_n[2]
|
||||
END out_e[1]
|
||||
PIN out_e[2]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 8.370 21.000 8.650 25.000 ;
|
||||
END
|
||||
END out_n[2]
|
||||
PIN out_s[0]
|
||||
END out_e[2]
|
||||
PIN out_w[0]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 10.670 0.000 10.950 4.000 ;
|
||||
END
|
||||
END out_s[0]
|
||||
PIN out_s[10]
|
||||
END out_w[0]
|
||||
PIN out_w[10]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 33.670 0.000 33.950 4.000 ;
|
||||
END
|
||||
END out_s[10]
|
||||
PIN out_s[11]
|
||||
END out_w[10]
|
||||
PIN out_w[11]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 35.970 0.000 36.250 4.000 ;
|
||||
END
|
||||
END out_s[11]
|
||||
PIN out_s[1]
|
||||
END out_w[11]
|
||||
PIN out_w[1]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 12.970 0.000 13.250 4.000 ;
|
||||
END
|
||||
END out_s[1]
|
||||
PIN out_s[2]
|
||||
END out_w[1]
|
||||
PIN out_w[2]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 15.270 0.000 15.550 4.000 ;
|
||||
END
|
||||
END out_s[2]
|
||||
PIN out_s[3]
|
||||
END out_w[2]
|
||||
PIN out_w[3]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 17.570 0.000 17.850 4.000 ;
|
||||
END
|
||||
END out_s[3]
|
||||
PIN out_s[4]
|
||||
END out_w[3]
|
||||
PIN out_w[4]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 19.870 0.000 20.150 4.000 ;
|
||||
END
|
||||
END out_s[4]
|
||||
PIN out_s[5]
|
||||
END out_w[4]
|
||||
PIN out_w[5]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 22.170 0.000 22.450 4.000 ;
|
||||
END
|
||||
END out_s[5]
|
||||
PIN out_s[6]
|
||||
END out_w[5]
|
||||
PIN out_w[6]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 24.470 0.000 24.750 4.000 ;
|
||||
END
|
||||
END out_s[6]
|
||||
PIN out_s[7]
|
||||
END out_w[6]
|
||||
PIN out_w[7]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 26.770 0.000 27.050 4.000 ;
|
||||
END
|
||||
END out_s[7]
|
||||
PIN out_s[8]
|
||||
END out_w[7]
|
||||
PIN out_w[8]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 29.070 0.000 29.350 4.000 ;
|
||||
END
|
||||
END out_s[8]
|
||||
PIN out_s[9]
|
||||
END out_w[8]
|
||||
PIN out_w[9]
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met2 ;
|
||||
RECT 31.370 0.000 31.650 4.000 ;
|
||||
END
|
||||
END out_s[9]
|
||||
END out_w[9]
|
||||
OBS
|
||||
LAYER nwell ;
|
||||
RECT 1.650 17.625 37.910 19.230 ;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1665682150
|
||||
timestamp 1665840466
|
||||
<< nwell >>
|
||||
rect 330 3525 7582 3846
|
||||
rect 330 2437 7582 3003
|
||||
|
|
@ -101,72 +101,72 @@ rlabel metal4 s 4690 1040 5010 3856 6 VPWR
|
|||
port 2 nsew power bidirectional
|
||||
rlabel metal4 s 6483 1040 6803 3856 6 VPWR
|
||||
port 2 nsew power bidirectional
|
||||
rlabel metal2 s 2134 4200 2190 5000 6 in_n[0]
|
||||
rlabel metal2 s 2134 4200 2190 5000 6 in_e[0]
|
||||
port 3 nsew signal input
|
||||
rlabel metal2 s 6734 4200 6790 5000 6 in_n[10]
|
||||
rlabel metal2 s 6734 4200 6790 5000 6 in_e[10]
|
||||
port 4 nsew signal input
|
||||
rlabel metal2 s 7194 4200 7250 5000 6 in_n[11]
|
||||
rlabel metal2 s 7194 4200 7250 5000 6 in_e[11]
|
||||
port 5 nsew signal input
|
||||
rlabel metal2 s 2594 4200 2650 5000 6 in_n[1]
|
||||
rlabel metal2 s 2594 4200 2650 5000 6 in_e[1]
|
||||
port 6 nsew signal input
|
||||
rlabel metal2 s 3054 4200 3110 5000 6 in_n[2]
|
||||
rlabel metal2 s 3054 4200 3110 5000 6 in_e[2]
|
||||
port 7 nsew signal input
|
||||
rlabel metal2 s 3514 4200 3570 5000 6 in_n[3]
|
||||
rlabel metal2 s 3514 4200 3570 5000 6 in_e[3]
|
||||
port 8 nsew signal input
|
||||
rlabel metal2 s 3974 4200 4030 5000 6 in_n[4]
|
||||
rlabel metal2 s 3974 4200 4030 5000 6 in_e[4]
|
||||
port 9 nsew signal input
|
||||
rlabel metal2 s 4434 4200 4490 5000 6 in_n[5]
|
||||
rlabel metal2 s 4434 4200 4490 5000 6 in_e[5]
|
||||
port 10 nsew signal input
|
||||
rlabel metal2 s 4894 4200 4950 5000 6 in_n[6]
|
||||
rlabel metal2 s 4894 4200 4950 5000 6 in_e[6]
|
||||
port 11 nsew signal input
|
||||
rlabel metal2 s 5354 4200 5410 5000 6 in_n[7]
|
||||
rlabel metal2 s 5354 4200 5410 5000 6 in_e[7]
|
||||
port 12 nsew signal input
|
||||
rlabel metal2 s 5814 4200 5870 5000 6 in_n[8]
|
||||
rlabel metal2 s 5814 4200 5870 5000 6 in_e[8]
|
||||
port 13 nsew signal input
|
||||
rlabel metal2 s 6274 4200 6330 5000 6 in_n[9]
|
||||
rlabel metal2 s 6274 4200 6330 5000 6 in_e[9]
|
||||
port 14 nsew signal input
|
||||
rlabel metal2 s 754 0 810 800 6 in_s[0]
|
||||
rlabel metal2 s 754 0 810 800 6 in_w[0]
|
||||
port 15 nsew signal input
|
||||
rlabel metal2 s 1214 0 1270 800 6 in_s[1]
|
||||
rlabel metal2 s 1214 0 1270 800 6 in_w[1]
|
||||
port 16 nsew signal input
|
||||
rlabel metal2 s 1674 0 1730 800 6 in_s[2]
|
||||
rlabel metal2 s 1674 0 1730 800 6 in_w[2]
|
||||
port 17 nsew signal input
|
||||
rlabel metal2 s 754 4200 810 5000 6 out_n[0]
|
||||
rlabel metal2 s 754 4200 810 5000 6 out_e[0]
|
||||
port 18 nsew signal output
|
||||
rlabel metal2 s 1214 4200 1270 5000 6 out_n[1]
|
||||
rlabel metal2 s 1214 4200 1270 5000 6 out_e[1]
|
||||
port 19 nsew signal output
|
||||
rlabel metal2 s 1674 4200 1730 5000 6 out_n[2]
|
||||
rlabel metal2 s 1674 4200 1730 5000 6 out_e[2]
|
||||
port 20 nsew signal output
|
||||
rlabel metal2 s 2134 0 2190 800 6 out_s[0]
|
||||
rlabel metal2 s 2134 0 2190 800 6 out_w[0]
|
||||
port 21 nsew signal output
|
||||
rlabel metal2 s 6734 0 6790 800 6 out_s[10]
|
||||
rlabel metal2 s 6734 0 6790 800 6 out_w[10]
|
||||
port 22 nsew signal output
|
||||
rlabel metal2 s 7194 0 7250 800 6 out_s[11]
|
||||
rlabel metal2 s 7194 0 7250 800 6 out_w[11]
|
||||
port 23 nsew signal output
|
||||
rlabel metal2 s 2594 0 2650 800 6 out_s[1]
|
||||
rlabel metal2 s 2594 0 2650 800 6 out_w[1]
|
||||
port 24 nsew signal output
|
||||
rlabel metal2 s 3054 0 3110 800 6 out_s[2]
|
||||
rlabel metal2 s 3054 0 3110 800 6 out_w[2]
|
||||
port 25 nsew signal output
|
||||
rlabel metal2 s 3514 0 3570 800 6 out_s[3]
|
||||
rlabel metal2 s 3514 0 3570 800 6 out_w[3]
|
||||
port 26 nsew signal output
|
||||
rlabel metal2 s 3974 0 4030 800 6 out_s[4]
|
||||
rlabel metal2 s 3974 0 4030 800 6 out_w[4]
|
||||
port 27 nsew signal output
|
||||
rlabel metal2 s 4434 0 4490 800 6 out_s[5]
|
||||
rlabel metal2 s 4434 0 4490 800 6 out_w[5]
|
||||
port 28 nsew signal output
|
||||
rlabel metal2 s 4894 0 4950 800 6 out_s[6]
|
||||
rlabel metal2 s 4894 0 4950 800 6 out_w[6]
|
||||
port 29 nsew signal output
|
||||
rlabel metal2 s 5354 0 5410 800 6 out_s[7]
|
||||
rlabel metal2 s 5354 0 5410 800 6 out_w[7]
|
||||
port 30 nsew signal output
|
||||
rlabel metal2 s 5814 0 5870 800 6 out_s[8]
|
||||
rlabel metal2 s 5814 0 5870 800 6 out_w[8]
|
||||
port 31 nsew signal output
|
||||
rlabel metal2 s 6274 0 6330 800 6 out_s[9]
|
||||
rlabel metal2 s 6274 0 6330 800 6 out_w[9]
|
||||
port 32 nsew signal output
|
||||
<< properties >>
|
||||
string FIXED_BBOX 0 0 8000 5000
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 83666
|
||||
string GDS_FILE ../gds/buff_flash_clkrst.gds
|
||||
string GDS_START 25066
|
||||
string GDS_END 98794
|
||||
string GDS_FILE /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.magic.gds
|
||||
string GDS_START 27910
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#S
|
||||
in_s.*
|
||||
out_s.*
|
||||
in_w.*
|
||||
out_w.*
|
||||
|
||||
#N
|
||||
out_n.*
|
||||
in_n.*
|
||||
out_e.*
|
||||
in_e.*
|
||||
|
|
@ -1,2 +1,2 @@
|
|||
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
|
||||
/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst,buff_flash_clkrst,22_10_13_10_28,flow completed,0h0m29s0ms,0h0m13s0ms,-2.0,0.001,-1,46.74,481.88,-1,0,0,0,0,0,0,0,-1,-1,-1,-1,357,60,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,376761.0,0.0,5.19,13.85,0.0,0.0,0.0,4,30,4,30,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,10,7,0,17,487.96799999999985,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,8.0,125.0,8,AREA 0,10,50,1,8.965,3.395,0.96,0.3,sky130_fd_sc_hd,3
|
||||
/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst,buff_flash_clkrst,22_10_15_06_27,flow completed,0h0m29s0ms,0h0m13s0ms,-2.0,0.001,-1,46.74,477.77,-1,0,0,0,0,0,0,0,-1,0,-1,-1,428,89,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,376761.0,0.0,9.91,24.62,0.0,0.0,0.0,4,30,4,30,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,10,7,0,17,487.96799999999985,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,8.0,125.0,8,AREA 0,10,50,1,8.965,3.395,0.96,0.3,sky130_fd_sc_hd,3
|
||||
|
|
|
|||
|
|
|
@ -1,40 +1,40 @@
|
|||
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.min.lef
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.min.lef
|
||||
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
|
||||
The LEF parser will ignore this statement.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.min.lef at line 930.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.min.lef at line 930.
|
||||
|
||||
[INFO ODB-0223] Created 13 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0225] Created 441 library cells
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.min.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.min.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0128] Design: buff_flash_clkrst
|
||||
[INFO ODB-0130] Created 32 pins.
|
||||
[INFO ODB-0131] Created 73 components and 308 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 278 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 30 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0131] Created 98 components and 423 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 378 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 45 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
Using RCX ruleset '/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre'...
|
||||
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
|
||||
[INFO RCX-0029] Defined extraction corner X
|
||||
[INFO RCX-0008] extracting parasitics of buff_flash_clkrst ...
|
||||
[INFO RCX-0435] Reading extraction model file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre ...
|
||||
[INFO RCX-0436] RC segment generation buff_flash_clkrst (max_merge_res 50.0) ...
|
||||
[INFO RCX-0040] Final 30 rc segments
|
||||
[INFO RCX-0040] Final 60 rc segments
|
||||
[INFO RCX-0439] Coupling Cap extraction buff_flash_clkrst ...
|
||||
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
|
||||
[INFO RCX-0043] 156 wires to be extracted
|
||||
[INFO RCX-0442] 66% completion -- 103 wires have been extracted
|
||||
[INFO RCX-0442] 100% completion -- 156 wires have been extracted
|
||||
[INFO RCX-0045] Extract 30 nets, 60 rsegs, 60 caps, 53 ccs
|
||||
[INFO RCX-0043] 189 wires to be extracted
|
||||
[INFO RCX-0442] 64% completion -- 121 wires have been extracted
|
||||
[INFO RCX-0442] 100% completion -- 189 wires have been extracted
|
||||
[INFO RCX-0045] Extract 30 nets, 90 rsegs, 90 caps, 83 ccs
|
||||
[INFO RCX-0015] Finished extracting buff_flash_clkrst.
|
||||
Writing result to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_min/buff_flash_clkrst.spef...
|
||||
Writing result to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_min/buff_flash_clkrst.spef...
|
||||
Setting global connections for newly added cells...
|
||||
[WARNING] Did not save OpenROAD database!
|
||||
Writing extracted parasitics to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_min/buff_flash_clkrst.spef...
|
||||
Writing extracted parasitics to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_min/buff_flash_clkrst.spef...
|
||||
[INFO RCX-0016] Writing SPEF ...
|
||||
[INFO RCX-0443] 30 nets finished
|
||||
[INFO RCX-0017] Finished writing SPEF ...
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,40 +1,40 @@
|
|||
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.max.lef
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.max.lef
|
||||
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
|
||||
The LEF parser will ignore this statement.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.max.lef at line 930.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.max.lef at line 930.
|
||||
|
||||
[INFO ODB-0223] Created 13 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0225] Created 441 library cells
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.max.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.max.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0128] Design: buff_flash_clkrst
|
||||
[INFO ODB-0130] Created 32 pins.
|
||||
[INFO ODB-0131] Created 73 components and 308 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 278 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 30 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0131] Created 98 components and 423 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 378 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 45 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
Using RCX ruleset '/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre'...
|
||||
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
|
||||
[INFO RCX-0029] Defined extraction corner X
|
||||
[INFO RCX-0008] extracting parasitics of buff_flash_clkrst ...
|
||||
[INFO RCX-0435] Reading extraction model file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre ...
|
||||
[INFO RCX-0436] RC segment generation buff_flash_clkrst (max_merge_res 50.0) ...
|
||||
[INFO RCX-0040] Final 46 rc segments
|
||||
[INFO RCX-0040] Final 72 rc segments
|
||||
[INFO RCX-0439] Coupling Cap extraction buff_flash_clkrst ...
|
||||
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
|
||||
[INFO RCX-0043] 156 wires to be extracted
|
||||
[INFO RCX-0442] 66% completion -- 103 wires have been extracted
|
||||
[INFO RCX-0442] 100% completion -- 156 wires have been extracted
|
||||
[INFO RCX-0045] Extract 30 nets, 76 rsegs, 76 caps, 53 ccs
|
||||
[INFO RCX-0043] 189 wires to be extracted
|
||||
[INFO RCX-0442] 64% completion -- 121 wires have been extracted
|
||||
[INFO RCX-0442] 100% completion -- 189 wires have been extracted
|
||||
[INFO RCX-0045] Extract 30 nets, 102 rsegs, 102 caps, 87 ccs
|
||||
[INFO RCX-0015] Finished extracting buff_flash_clkrst.
|
||||
Writing result to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_max/buff_flash_clkrst.spef...
|
||||
Writing result to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_max/buff_flash_clkrst.spef...
|
||||
Setting global connections for newly added cells...
|
||||
[WARNING] Did not save OpenROAD database!
|
||||
Writing extracted parasitics to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_max/buff_flash_clkrst.spef...
|
||||
Writing extracted parasitics to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_max/buff_flash_clkrst.spef...
|
||||
[INFO RCX-0016] Writing SPEF ...
|
||||
[INFO RCX-0443] 30 nets finished
|
||||
[INFO RCX-0017] Finished writing SPEF ...
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,40 +1,40 @@
|
|||
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
|
||||
The LEF parser will ignore this statement.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef at line 930.
|
||||
|
||||
[INFO ODB-0223] Created 13 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0225] Created 441 library cells
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0128] Design: buff_flash_clkrst
|
||||
[INFO ODB-0130] Created 32 pins.
|
||||
[INFO ODB-0131] Created 73 components and 308 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 278 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 30 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0131] Created 98 components and 423 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 378 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 45 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
Using RCX ruleset '/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre'...
|
||||
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
|
||||
[INFO RCX-0029] Defined extraction corner X
|
||||
[INFO RCX-0008] extracting parasitics of buff_flash_clkrst ...
|
||||
[INFO RCX-0435] Reading extraction model file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre ...
|
||||
[INFO RCX-0436] RC segment generation buff_flash_clkrst (max_merge_res 50.0) ...
|
||||
[INFO RCX-0040] Final 30 rc segments
|
||||
[INFO RCX-0040] Final 60 rc segments
|
||||
[INFO RCX-0439] Coupling Cap extraction buff_flash_clkrst ...
|
||||
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
|
||||
[INFO RCX-0043] 156 wires to be extracted
|
||||
[INFO RCX-0442] 66% completion -- 103 wires have been extracted
|
||||
[INFO RCX-0442] 100% completion -- 156 wires have been extracted
|
||||
[INFO RCX-0045] Extract 30 nets, 60 rsegs, 60 caps, 53 ccs
|
||||
[INFO RCX-0043] 189 wires to be extracted
|
||||
[INFO RCX-0442] 64% completion -- 121 wires have been extracted
|
||||
[INFO RCX-0442] 100% completion -- 189 wires have been extracted
|
||||
[INFO RCX-0045] Extract 30 nets, 90 rsegs, 90 caps, 83 ccs
|
||||
[INFO RCX-0015] Finished extracting buff_flash_clkrst.
|
||||
Writing result to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef...
|
||||
Writing result to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef...
|
||||
Setting global connections for newly added cells...
|
||||
[WARNING] Did not save OpenROAD database!
|
||||
Writing extracted parasitics to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef...
|
||||
Writing extracted parasitics to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef...
|
||||
[INFO RCX-0016] Writing SPEF ...
|
||||
[INFO RCX-0443] 30 nets finished
|
||||
[INFO RCX-0017] Finished writing SPEF ...
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -7,8 +7,8 @@ min_report
|
|||
===========================================================================
|
||||
report_checks -path_delay min (Hold)
|
||||
============================================================================
|
||||
Startpoint: in_n[3] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[3] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_w[2] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_e[2] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: min
|
||||
|
||||
|
|
@ -17,43 +17,12 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 v input external delay
|
||||
0.01 0.01 1.61 v in_n[3] (in)
|
||||
1 0.00 in_n[3] (net)
|
||||
0.01 0.00 1.61 v BUF[6]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.74 v BUF[6]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[3] (net)
|
||||
0.05 0.00 1.74 v out_s[3] (out)
|
||||
1.74 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.25 0.25 clock uncertainty
|
||||
0.00 0.25 clock reconvergence pessimism
|
||||
-1.60 -1.35 output external delay
|
||||
-1.35 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
-1.35 data required time
|
||||
-1.74 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
3.09 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_n[10] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[10] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 v input external delay
|
||||
0.01 0.01 1.61 v in_n[10] (in)
|
||||
1 0.00 in_n[10] (net)
|
||||
0.01 0.00 1.61 v BUF[13]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.74 v BUF[13]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[10] (net)
|
||||
0.05 0.00 1.75 v out_s[10] (out)
|
||||
0.02 0.01 1.61 v in_w[2] (in)
|
||||
2 0.01 in_w[2] (net)
|
||||
0.02 0.00 1.61 v BUF[2]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.75 v BUF[2]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_e[2] (net)
|
||||
0.05 0.00 1.75 v out_e[2] (out)
|
||||
1.75 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
|
|
@ -69,8 +38,8 @@ Fanout Cap Slew Delay Time Description
|
|||
3.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_n[0] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[0] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_e[2] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[2] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: min
|
||||
|
||||
|
|
@ -79,12 +48,12 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 v input external delay
|
||||
0.01 0.01 1.61 v in_n[0] (in)
|
||||
1 0.00 in_n[0] (net)
|
||||
0.01 0.00 1.61 v BUF[3]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.74 v BUF[3]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[0] (net)
|
||||
0.05 0.00 1.75 v out_s[0] (out)
|
||||
0.02 0.01 1.61 v in_e[2] (in)
|
||||
2 0.01 in_e[2] (net)
|
||||
0.02 0.00 1.61 v BUF[5]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.75 v BUF[5]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[2] (net)
|
||||
0.05 0.00 1.75 v out_w[2] (out)
|
||||
1.75 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
|
|
@ -100,8 +69,8 @@ Fanout Cap Slew Delay Time Description
|
|||
3.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_s[2] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_n[2] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_e[5] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[5] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: min
|
||||
|
||||
|
|
@ -110,12 +79,12 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 v input external delay
|
||||
0.01 0.01 1.61 v in_s[2] (in)
|
||||
1 0.00 in_s[2] (net)
|
||||
0.01 0.00 1.61 v BUF[2]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.74 v BUF[2]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_n[2] (net)
|
||||
0.05 0.00 1.75 v out_n[2] (out)
|
||||
0.02 0.01 1.61 v in_e[5] (in)
|
||||
2 0.01 in_e[5] (net)
|
||||
0.02 0.00 1.61 v BUF[8]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.75 v BUF[8]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[5] (net)
|
||||
0.05 0.00 1.75 v out_w[5] (out)
|
||||
1.75 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
|
|
@ -131,8 +100,8 @@ Fanout Cap Slew Delay Time Description
|
|||
3.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_n[8] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[8] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_e[3] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[3] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: min
|
||||
|
||||
|
|
@ -141,12 +110,43 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 v input external delay
|
||||
0.01 0.01 1.61 v in_n[8] (in)
|
||||
1 0.00 in_n[8] (net)
|
||||
0.01 0.00 1.61 v BUF[11]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.74 v BUF[11]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[8] (net)
|
||||
0.05 0.00 1.75 v out_s[8] (out)
|
||||
0.02 0.01 1.61 v in_e[3] (in)
|
||||
2 0.01 in_e[3] (net)
|
||||
0.02 0.00 1.61 v BUF[6]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.75 v BUF[6]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[3] (net)
|
||||
0.05 0.00 1.75 v out_w[3] (out)
|
||||
1.75 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.25 0.25 clock uncertainty
|
||||
0.00 0.25 clock reconvergence pessimism
|
||||
-1.60 -1.35 output external delay
|
||||
-1.35 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
-1.35 data required time
|
||||
-1.75 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
3.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_e[10] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[10] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 v input external delay
|
||||
0.02 0.01 1.61 v in_e[10] (in)
|
||||
2 0.01 in_e[10] (net)
|
||||
0.02 0.00 1.61 v BUF[13]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.05 0.14 1.75 v BUF[13]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[10] (net)
|
||||
0.05 0.00 1.75 v out_w[10] (out)
|
||||
1.75 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
|
|
@ -168,8 +168,8 @@ max_report
|
|||
===========================================================================
|
||||
report_checks -path_delay max (Setup)
|
||||
============================================================================
|
||||
Startpoint: in_n[11] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[11] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_e[11] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[11] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
|
|
@ -178,12 +178,105 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.04 0.03 1.63 ^ in_n[11] (in)
|
||||
1 0.01 in_n[11] (net)
|
||||
0.04 0.00 1.63 ^ BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.08 0.16 1.78 ^ BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[11] (net)
|
||||
0.08 0.00 1.78 ^ out_s[11] (out)
|
||||
0.05 0.04 1.64 ^ in_e[11] (in)
|
||||
2 0.01 in_e[11] (net)
|
||||
0.05 0.00 1.64 ^ BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.16 1.80 ^ BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[11] (net)
|
||||
0.07 0.00 1.80 ^ out_w[11] (out)
|
||||
1.80 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
-0.25 7.75 clock uncertainty
|
||||
0.00 7.75 clock reconvergence pessimism
|
||||
-1.60 6.15 output external delay
|
||||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.80 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.35 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_e[9] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[9] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.05 0.03 1.63 ^ in_e[9] (in)
|
||||
2 0.01 in_e[9] (net)
|
||||
0.05 0.00 1.63 ^ BUF[12]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.16 1.79 ^ BUF[12]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[9] (net)
|
||||
0.07 0.00 1.79 ^ out_w[9] (out)
|
||||
1.79 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
-0.25 7.75 clock uncertainty
|
||||
0.00 7.75 clock reconvergence pessimism
|
||||
-1.60 6.15 output external delay
|
||||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.79 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.36 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_w[1] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_e[1] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.04 0.03 1.63 ^ in_w[1] (in)
|
||||
2 0.01 in_w[1] (net)
|
||||
0.04 0.00 1.63 ^ BUF[1]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.16 1.79 ^ BUF[1]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_e[1] (net)
|
||||
0.07 0.00 1.79 ^ out_e[1] (out)
|
||||
1.79 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
-0.25 7.75 clock uncertainty
|
||||
0.00 7.75 clock reconvergence pessimism
|
||||
-1.60 6.15 output external delay
|
||||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.79 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.36 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_e[6] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[6] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.04 0.03 1.63 ^ in_e[6] (in)
|
||||
2 0.01 in_e[6] (net)
|
||||
0.04 0.00 1.63 ^ BUF[9]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.16 1.78 ^ BUF[9]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[6] (net)
|
||||
0.07 0.00 1.78 ^ out_w[6] (out)
|
||||
1.78 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
|
|
@ -199,8 +292,8 @@ Fanout Cap Slew Delay Time Description
|
|||
4.37 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_n[2] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[2] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_w[0] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_e[0] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
|
|
@ -209,105 +302,12 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.03 0.02 1.62 ^ in_n[2] (in)
|
||||
1 0.01 in_n[2] (net)
|
||||
0.03 0.00 1.62 ^ BUF[5]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.15 1.78 ^ BUF[5]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[2] (net)
|
||||
0.07 0.00 1.78 ^ out_s[2] (out)
|
||||
1.78 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
-0.25 7.75 clock uncertainty
|
||||
0.00 7.75 clock reconvergence pessimism
|
||||
-1.60 6.15 output external delay
|
||||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.78 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.37 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_n[6] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[6] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.03 0.02 1.62 ^ in_n[6] (in)
|
||||
1 0.01 in_n[6] (net)
|
||||
0.03 0.00 1.62 ^ BUF[9]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.15 1.78 ^ BUF[9]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[6] (net)
|
||||
0.07 0.00 1.78 ^ out_s[6] (out)
|
||||
1.78 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
-0.25 7.75 clock uncertainty
|
||||
0.00 7.75 clock reconvergence pessimism
|
||||
-1.60 6.15 output external delay
|
||||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.78 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.37 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_n[7] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[7] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.03 0.02 1.62 ^ in_n[7] (in)
|
||||
1 0.01 in_n[7] (net)
|
||||
0.03 0.00 1.62 ^ BUF[10]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.15 1.78 ^ BUF[10]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[7] (net)
|
||||
0.07 0.00 1.78 ^ out_s[7] (out)
|
||||
1.78 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
-0.25 7.75 clock uncertainty
|
||||
0.00 7.75 clock reconvergence pessimism
|
||||
-1.60 6.15 output external delay
|
||||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.78 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.37 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in_s[1] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_n[1] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.03 0.02 1.62 ^ in_s[1] (in)
|
||||
1 0.01 in_s[1] (net)
|
||||
0.03 0.00 1.62 ^ BUF[1]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.15 1.78 ^ BUF[1]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_n[1] (net)
|
||||
0.07 0.00 1.78 ^ out_n[1] (out)
|
||||
0.04 0.02 1.62 ^ in_w[0] (in)
|
||||
2 0.01 in_w[0] (net)
|
||||
0.04 0.00 1.62 ^ BUF[0]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.08 0.16 1.78 ^ BUF[0]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_e[0] (net)
|
||||
0.08 0.00 1.78 ^ out_e[0] (out)
|
||||
1.78 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
|
|
@ -329,8 +329,8 @@ check_report
|
|||
===========================================================================
|
||||
report_checks -unconstrained
|
||||
============================================================================
|
||||
Startpoint: in_n[11] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_s[11] (output port clocked by __VIRTUAL_CLK__)
|
||||
Startpoint: in_e[11] (input port clocked by __VIRTUAL_CLK__)
|
||||
Endpoint: out_w[11] (output port clocked by __VIRTUAL_CLK__)
|
||||
Path Group: __VIRTUAL_CLK__
|
||||
Path Type: max
|
||||
|
||||
|
|
@ -339,13 +339,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.60 1.60 ^ input external delay
|
||||
0.04 0.03 1.63 ^ in_n[11] (in)
|
||||
1 0.01 in_n[11] (net)
|
||||
0.04 0.00 1.63 ^ BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.08 0.16 1.78 ^ BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_s[11] (net)
|
||||
0.08 0.00 1.78 ^ out_s[11] (out)
|
||||
1.78 data arrival time
|
||||
0.05 0.04 1.64 ^ in_e[11] (in)
|
||||
2 0.01 in_e[11] (net)
|
||||
0.05 0.00 1.64 ^ BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
|
||||
0.07 0.16 1.80 ^ BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
|
||||
1 0.03 out_w[11] (net)
|
||||
0.07 0.00 1.80 ^ out_w[11] (out)
|
||||
1.80 data arrival time
|
||||
|
||||
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
|
|
@ -355,9 +355,9 @@ Fanout Cap Slew Delay Time Description
|
|||
6.15 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
6.15 data required time
|
||||
-1.78 data arrival time
|
||||
-1.80 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
4.37 slack (MET)
|
||||
4.35 slack (MET)
|
||||
|
||||
|
||||
|
||||
|
|
@ -397,12 +397,12 @@ worst_slack
|
|||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack 4.37
|
||||
worst slack 4.35
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack 3.09
|
||||
worst slack 3.10
|
||||
worst_slack_end
|
||||
power_report
|
||||
|
||||
|
|
@ -413,21 +413,21 @@ Group Internal Switching Leakage Total
|
|||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Combinational 8.50e-06 1.01e-05 1.92e-10 1.86e-05 100.0%
|
||||
Combinational 8.49e-06 1.01e-05 2.31e-10 1.86e-05 100.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 8.50e-06 1.01e-05 1.92e-10 1.86e-05 100.0%
|
||||
45.6% 54.4% 0.0%
|
||||
Total 8.49e-06 1.01e-05 2.31e-10 1.86e-05 100.0%
|
||||
45.5% 54.5% 0.0%
|
||||
power_report_end
|
||||
area_report
|
||||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 215 u^2 44% utilization.
|
||||
Design area 253 u^2 52% utilization.
|
||||
area_report_end
|
||||
Setting global connections for newly added cells...
|
||||
[WARNING] Did not save OpenROAD database!
|
||||
Writing SDF to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.sdf...
|
||||
Writing timing model to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.lib...
|
||||
Writing SDF to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.sdf...
|
||||
Writing timing model to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.lib...
|
||||
|
|
@ -1,24 +1,24 @@
|
|||
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
|
||||
The LEF parser will ignore this statement.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef at line 930.
|
||||
|
||||
[INFO ODB-0223] Created 13 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0225] Created 441 library cells
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0128] Design: buff_flash_clkrst
|
||||
[INFO ODB-0130] Created 32 pins.
|
||||
[INFO ODB-0131] Created 73 components and 308 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 278 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 30 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0131] Created 98 components and 423 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 378 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 45 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
[INFO]: Setting RC values...
|
||||
[INFO PSM-0002] Output voltage file is specified as: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/21-irdrop.rpt.
|
||||
[INFO PSM-0002] Output voltage file is specified as: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/23-irdrop.rpt.
|
||||
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
|
||||
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
|
||||
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
|
||||
|
|
@ -32,6 +32,6 @@ To avoid this warning in the future, remove this statement from the LEF file wit
|
|||
[INFO PSM-0040] All PDN stripes on net VPWR are connected.
|
||||
########## IR report #################
|
||||
Worstcase voltage: 1.80e+00 V
|
||||
Average IR drop : 2.19e-10 V
|
||||
Worstcase IR drop: 3.61e-10 V
|
||||
Average IR drop : 2.63e-10 V
|
||||
Worstcase IR drop: 4.35e-10 V
|
||||
######################################
|
||||
|
|
@ -19,9 +19,10 @@ Reading "sky130_fd_sc_hd__clkbuf_8".
|
|||
Reading "sky130_fd_sc_hd__decap_4".
|
||||
Reading "sky130_fd_sc_hd__fill_1".
|
||||
Reading "sky130_fd_sc_hd__decap_3".
|
||||
Reading "sky130_fd_sc_hd__decap_8".
|
||||
Reading "sky130_ef_sc_hd__decap_12".
|
||||
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
|
||||
Reading "sky130_fd_sc_hd__diode_2".
|
||||
Reading "sky130_fd_sc_hd__fill_2".
|
||||
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
|
||||
Reading "sky130_fd_sc_hd__decap_6".
|
||||
Reading "sky130_fd_sc_hd__decap_8".
|
||||
Reading "buff_flash_clkrst".
|
||||
[INFO]: Wrote /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/gds_ptrs.mag including GDS pointers.
|
||||
[INFO]: Wrote /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/gds_ptrs.mag including GDS pointers.
|
||||
|
|
@ -41,14 +41,15 @@ LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ig
|
|||
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
|
||||
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
|
||||
LEF read: Processed 797 lines.
|
||||
Reading DEF data from file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def.
|
||||
Reading DEF data from file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def.
|
||||
This action cannot be undone.
|
||||
Processed 3 vias total.
|
||||
Processed 73 subcell instances total.
|
||||
Processed 98 subcell instances total.
|
||||
Processed 32 pins total.
|
||||
Processed 2 special nets total.
|
||||
Processed 30 nets total.
|
||||
DEF read: Processed 571 lines.
|
||||
DEF read: Processed 662 lines.
|
||||
Moving label "VGND" from metal1 to via1 in cell buff_flash_clkrst.
|
||||
Root cell box:
|
||||
width x height ( llx, lly ), ( urx, ury ) area (units^2)
|
||||
|
||||
|
|
@ -59,9 +60,10 @@ internal: 8000 x 5000 ( 0, 0 ), ( 8000, 5000 ) 40000000
|
|||
Generating output for cell sky130_fd_sc_hd__decap_4
|
||||
Generating output for cell sky130_fd_sc_hd__fill_1
|
||||
Generating output for cell sky130_fd_sc_hd__decap_3
|
||||
Generating output for cell sky130_fd_sc_hd__decap_8
|
||||
Generating output for cell sky130_ef_sc_hd__decap_12
|
||||
Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Generating output for cell sky130_fd_sc_hd__diode_2
|
||||
Generating output for cell sky130_fd_sc_hd__fill_2
|
||||
Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Generating output for cell sky130_fd_sc_hd__decap_6
|
||||
Generating output for cell sky130_fd_sc_hd__decap_8
|
||||
Generating output for cell buff_flash_clkrst
|
||||
[INFO]: GDS Write Complete
|
||||
|
|
@ -42,32 +42,44 @@ LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignori
|
|||
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
|
||||
LEF read: Processed 797 lines.
|
||||
[INFO]: Writing abstract LEF
|
||||
Generating LEF output /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.lef for cell buff_flash_clkrst:
|
||||
Generating LEF output /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.lef for cell buff_flash_clkrst:
|
||||
Diagnostic: Write LEF header for cell buff_flash_clkrst
|
||||
Diagnostic: Writing LEF output for cell buff_flash_clkrst
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_8" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__clkbuf_8.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_8.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_8" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__clkbuf_8.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_8.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_4" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__decap_4.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_4.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_4" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__decap_4.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_4.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_1" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__fill_1.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_1.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_1" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__fill_1.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_1.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_3" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__decap_3.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_3.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_3" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__decap_3.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_3.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_8" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__decap_8.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_8.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__diode_2.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__diode_2" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__diode_2.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__diode_2.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_ef_sc_hd__decap_12" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_ef_sc_hd__decap_12.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_ef_sc_hd__decap_12.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_2.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_2" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__fill_2.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_2.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__tapvpwrvgnd_1" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__tapvpwrvgnd_1.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__tapvpwrvgnd_1" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
|
||||
The discovered version will be used.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_2" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__fill_2.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_2.mag.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_6.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_6" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__decap_6.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_6.mag.
|
||||
The discovered version will be used.
|
||||
File </home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_8.mag> is already locked by another process. Opening read-only.
|
||||
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_8" at bad file path /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/sky130_fd_sc_hd__decap_8.mag.
|
||||
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_8.mag.
|
||||
The discovered version will be used.
|
||||
Diagnostic: Scale value is 0.005000
|
||||
[INFO]: LEF Write Complete
|
||||
|
|
@ -12,7 +12,7 @@ The following types are not handled by extraction and will be treated as non-ele
|
|||
Scaled tech values by 2 / 1 to match internal grid scaling
|
||||
Loading sky130A Device Generator Menu ...
|
||||
Using technology "sky130A", version 1.0.341-2-gde752ec
|
||||
Reading LEF data from file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.lef.
|
||||
Reading LEF data from file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.lef.
|
||||
This action cannot be undone.
|
||||
LEF read: Processed 335 lines.
|
||||
[INFO]: DONE GENERATING MAGLEF VIEW
|
||||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
Input: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
Output: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds
|
||||
Input: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
Output: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.klayout.gds
|
||||
Design: buff_flash_clkrst
|
||||
Technology File: /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt
|
||||
GDS File List: ['/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds']
|
||||
LEF File: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
LEF File: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
|
||||
[INFO] Clearing cells...
|
||||
[INFO] Merging GDS files...
|
||||
|
|
@ -13,5 +13,5 @@ LEF File: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_
|
|||
WARNING: no fill config file specified
|
||||
[INFO] Checking for missing GDS...
|
||||
[INFO] All LEF cells have matching GDS cells
|
||||
[INFO] Writing out GDS '/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds'
|
||||
[INFO] Writing out GDS '/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.klayout.gds'
|
||||
[INFO] Done.
|
||||
|
|
@ -1,16 +1,16 @@
|
|||
First Layout: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.gds
|
||||
Second Layout: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds
|
||||
First Layout: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.gds
|
||||
Second Layout: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.klayout.gds
|
||||
Design Name: buff_flash_clkrst
|
||||
Output GDS will be: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/buff_flash_clkrst.xor.xml
|
||||
Reading /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.gds ..
|
||||
Reading /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds ..
|
||||
Output GDS will be: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/buff_flash_clkrst.xor.xml
|
||||
Reading /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.gds ..
|
||||
Reading /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.klayout.gds ..
|
||||
--- Running XOR for 10/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 4 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 4 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -27,7 +27,7 @@ XOR differences: 96
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 32 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 32
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 32 (flat) 9 (hierarchical)
|
||||
|
|
@ -41,7 +41,7 @@ XOR differences: 32
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -55,18 +55,18 @@ XOR differences: 0
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 8 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 8
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 8 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 122/16 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 66 (flat) 7 (hierarchical)
|
||||
Polygons (raw): 91 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 66 (flat) 7 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Polygons (raw): 91 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -80,7 +80,7 @@ XOR differences: 0
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 1 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 1 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -101,13 +101,13 @@ XOR differences: 1
|
|||
XOR differences: 1
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 1 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 236/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 48 (flat) 5 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 68 (flat) 6 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 48 (flat) 5 (hierarchical)
|
||||
Polygons (raw): 68 (flat) 6 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -121,77 +121,77 @@ XOR differences: 0
|
|||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 30 (flat) 1 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 30 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 30
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 30 (flat) 1 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 45
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 45 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
--- Running XOR for 4/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
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|
||||
Polygons (raw): 30 (flat) 1 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
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|
||||
Polygons (raw): 30 (flat) 1 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 30
|
||||
XOR differences: 45
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 30 (flat) 1 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 5/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 126 (flat) 45 (hierarchical)
|
||||
Polygons (raw): 172 (flat) 62 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 126 (flat) 45 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 126
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 126 (flat) 45 (hierarchical)
|
||||
Polygons (raw): 172 (flat) 62 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 172
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 172 (flat) 62 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
--- Running XOR for 6/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 150 (flat) 6 (hierarchical)
|
||||
Polygons (raw): 164 (flat) 6 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 150 (flat) 6 (hierarchical)
|
||||
Polygons (raw): 164 (flat) 6 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 150
|
||||
XOR differences: 164
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 150 (flat) 6 (hierarchical)
|
||||
Polygons (raw): 164 (flat) 6 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 64/16 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 66 (flat) 7 (hierarchical)
|
||||
Polygons (raw): 91 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 66 (flat) 7 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Polygons (raw): 91 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 64/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 73 (flat) 8 (hierarchical)
|
||||
Polygons (raw): 98 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 73 (flat) 8 (hierarchical)
|
||||
Polygons (raw): 98 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -203,7 +203,7 @@ XOR differences: 0
|
|||
--- Running XOR for 64/5 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -227,13 +227,13 @@ XOR differences: 0
|
|||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
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|
||||
--- Running XOR for 65/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 121 (flat) 11 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 10 (hierarchical)
|
||||
Polygons (raw): 121 (flat) 11 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -251,17 +251,17 @@ XOR differences: 0
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
--- Running XOR for 66/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 10 (hierarchical)
|
||||
Polygons (raw): 106 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 10 (hierarchical)
|
||||
Polygons (raw): 106 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -272,11 +272,11 @@ XOR differences: 0
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 66/44 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 827 (flat) 73 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 827 (flat) 73 (hierarchical)
|
||||
Polygons (raw): 937 (flat) 81 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 937 (flat) 81 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -286,11 +286,11 @@ XOR differences: 0
|
|||
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|
||||
--- Running XOR for 67/16 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 120 (flat) 8 (hierarchical)
|
||||
Polygons (raw): 300 (flat) 20 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 120 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 300 (flat) 20 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -300,10 +300,10 @@ XOR differences: 0
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 67/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 293 (flat) 57 (hierarchical)
|
||||
Polygons (raw): 345 (flat) 71 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 263 (flat) 27 (hierarchical)
|
||||
Polygons (raw): 300 (flat) 26 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
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|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 67/44 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 810 (flat) 114 (hierarchical)
|
||||
Polygons (raw): 825 (flat) 121 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 780 (flat) 84 (hierarchical)
|
||||
Polygons (raw): 780 (flat) 76 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 30 (flat) 30 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 45 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 30
|
||||
XOR differences: 45
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 30 (flat) 30 (hierarchical)
|
||||
Polygons (raw): 45 (flat) 45 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 67/5 ---
|
||||
"input" in: xor.drc:38
|
||||
|
|
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|
|||
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|
||||
--- Running XOR for 68/16 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 146 (flat) 16 (hierarchical)
|
||||
Polygons (raw): 196 (flat) 18 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 146 (flat) 16 (hierarchical)
|
||||
Polygons (raw): 196 (flat) 18 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
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|
|||
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|
||||
--- Running XOR for 68/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 296 (flat) 166 (hierarchical)
|
||||
Polygons (raw): 404 (flat) 226 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 146 (flat) 16 (hierarchical)
|
||||
Polygons (raw): 196 (flat) 18 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 33 (flat) 33 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 33
|
||||
Polygons (raw): 43 (flat) 43 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 43
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 33 (flat) 33 (hierarchical)
|
||||
Polygons (raw): 43 (flat) 43 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 68/44 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 150 (flat) 150 (hierarchical)
|
||||
Polygons (raw): 164 (flat) 164 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 150 (flat) 150 (hierarchical)
|
||||
Polygons (raw): 164 (flat) 164 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 150
|
||||
XOR differences: 164
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 150 (flat) 150 (hierarchical)
|
||||
Polygons (raw): 164 (flat) 164 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 68/5 ---
|
||||
"input" in: xor.drc:38
|
||||
|
|
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|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
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|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 69/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 158 (flat) 158 (hierarchical)
|
||||
Polygons (raw): 192 (flat) 192 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 158 (flat) 158 (hierarchical)
|
||||
Polygons (raw): 192 (flat) 192 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 158
|
||||
XOR differences: 192
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 158 (flat) 158 (hierarchical)
|
||||
Polygons (raw): 192 (flat) 192 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 69/44 ---
|
||||
"input" in: xor.drc:38
|
||||
|
|
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|
|||
"output" in: xor.drc:40
|
||||
Polygons (raw): 96 (flat) 96 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 69/5 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
--- Running XOR for 7/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 165 (flat) 90 (hierarchical)
|
||||
Polygons (raw): 199 (flat) 110 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 165 (flat) 90 (hierarchical)
|
||||
Polygons (raw): 199 (flat) 110 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 165
|
||||
XOR differences: 199
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 165 (flat) 90 (hierarchical)
|
||||
Polygons (raw): 199 (flat) 110 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 7/1 ---
|
||||
"input" in: xor.drc:38
|
||||
|
|
@ -469,7 +483,7 @@ XOR differences: 0
|
|||
--- Running XOR for 7/2 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 30 (flat) 30 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -489,11 +503,11 @@ XOR differences: 30
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 24 (flat) 24 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 24
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 24 (flat) 24 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 70/44 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 96 (flat) 96 (hierarchical)
|
||||
|
|
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|
|||
XOR differences: 8
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 8 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 71/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 8 (flat) 8 (hierarchical)
|
||||
|
|
@ -538,14 +552,14 @@ XOR differences: 8
|
|||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 78/44 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 73 (flat) 8 (hierarchical)
|
||||
Polygons (raw): 98 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 73 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 98 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -564,13 +578,27 @@ XOR differences: 96
|
|||
"output" in: xor.drc:40
|
||||
Polygons (raw): 96 (flat) 4 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 81/23 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 15 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 15 (flat) 1 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 81/4 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 73 (flat) 8 (hierarchical)
|
||||
Polygons (raw): 98 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 73 (flat) 8 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Polygons (raw): 98 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
|
|
@ -595,23 +623,23 @@ XOR differences: 0
|
|||
--- Running XOR for 9/0 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 72 (flat) 26 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 72 (flat) 26 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
XOR differences: 72
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 72 (flat) 26 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 93/44 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 80 (flat) 9 (hierarchical)
|
||||
Polygons (raw): 105 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 80 (flat) 9 (hierarchical)
|
||||
Polygons (raw): 105 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
|
|
@ -619,34 +647,34 @@ XOR differences: 72
|
|||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
--- Running XOR for 94/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 80 (flat) 9 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 105 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.010s Memory: 345.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 80 (flat) 9 (hierarchical)
|
||||
Polygons (raw): 105 (flat) 10 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 346.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 346.00M
|
||||
--- Running XOR for 95/20 ---
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 48 (flat) 5 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 53 (flat) 5 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 346.00M
|
||||
"input" in: xor.drc:38
|
||||
Polygons (raw): 48 (flat) 5 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Polygons (raw): 53 (flat) 5 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 346.00M
|
||||
"^" in: xor.drc:38
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Elapsed: 0.000s Memory: 346.00M
|
||||
XOR differences: 0
|
||||
"output" in: xor.drc:40
|
||||
Polygons (raw): 0 (flat) 0 (hierarchical)
|
||||
Elapsed: 0.000s Memory: 345.00M
|
||||
Writing report database: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/buff_flash_clkrst.xor.xml ..
|
||||
Total elapsed: 0.290s Memory: 345.00M
|
||||
Elapsed: 0.010s Memory: 346.00M
|
||||
Writing report database: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/buff_flash_clkrst.xor.xml ..
|
||||
Total elapsed: 0.310s Memory: 346.00M
|
||||
|
|
@ -19,19 +19,21 @@ Reading "sky130_fd_sc_hd__clkbuf_8".
|
|||
Reading "sky130_fd_sc_hd__decap_4".
|
||||
Reading "sky130_fd_sc_hd__fill_1".
|
||||
Reading "sky130_fd_sc_hd__decap_3".
|
||||
Reading "sky130_fd_sc_hd__decap_8".
|
||||
Reading "sky130_ef_sc_hd__decap_12".
|
||||
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
|
||||
Reading "sky130_fd_sc_hd__diode_2".
|
||||
Reading "sky130_fd_sc_hd__fill_2".
|
||||
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
|
||||
Reading "sky130_fd_sc_hd__decap_6".
|
||||
Reading "sky130_fd_sc_hd__decap_8".
|
||||
Reading "buff_flash_clkrst".
|
||||
Processing sky130_fd_sc_hd__clkbuf_8
|
||||
Processing sky130_fd_sc_hd__decap_4
|
||||
Processing sky130_fd_sc_hd__fill_1
|
||||
Processing sky130_fd_sc_hd__decap_3
|
||||
Processing sky130_fd_sc_hd__decap_8
|
||||
Processing sky130_ef_sc_hd__decap_12
|
||||
Processing sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Processing sky130_fd_sc_hd__diode_2
|
||||
Processing sky130_fd_sc_hd__fill_2
|
||||
Processing sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Processing sky130_fd_sc_hd__decap_6
|
||||
Processing sky130_fd_sc_hd__decap_8
|
||||
Processing buff_flash_clkrst
|
||||
Extracting sky130_fd_sc_hd__clkbuf_8 into sky130_fd_sc_hd__clkbuf_8.ext:
|
||||
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
|
||||
|
|
@ -39,12 +41,13 @@ sky130_fd_sc_hd__decap_4: 2 warnings
|
|||
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
|
||||
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
|
||||
sky130_fd_sc_hd__decap_3: 2 warnings
|
||||
Extracting sky130_fd_sc_hd__diode_2 into sky130_fd_sc_hd__diode_2.ext:
|
||||
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
|
||||
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
|
||||
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
|
||||
sky130_fd_sc_hd__decap_6: 2 warnings
|
||||
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
|
||||
sky130_fd_sc_hd__decap_8: 2 warnings
|
||||
Extracting sky130_ef_sc_hd__decap_12 into sky130_ef_sc_hd__decap_12.ext:
|
||||
sky130_ef_sc_hd__decap_12: 2 warnings
|
||||
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
|
||||
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
|
||||
Extracting buff_flash_clkrst into buff_flash_clkrst.ext:
|
||||
Total of 8 warnings.
|
||||
exttospice finished.
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
LVS reports no net, device, pin, or property mismatches.
|
||||
|
||||
Total errors = 0
|
||||
|
|
@ -1,25 +1,25 @@
|
|||
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
|
||||
The LEF parser will ignore this statement.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
|
||||
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef at line 930.
|
||||
|
||||
[INFO ODB-0223] Created 13 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0225] Created 441 library cells
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef
|
||||
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0128] Design: buff_flash_clkrst
|
||||
[INFO ODB-0130] Created 32 pins.
|
||||
[INFO ODB-0131] Created 73 components and 308 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 278 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 30 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
|
||||
[INFO ODB-0131] Created 98 components and 423 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 378 connections.
|
||||
[INFO ODB-0133] Created 30 nets and 45 connections.
|
||||
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
Top-level design name: buff_flash_clkrst
|
||||
Found default power net 'VPWR'
|
||||
Found default ground net 'VGND'
|
||||
Found 1 power ports.
|
||||
Found 1 ground ports.
|
||||
Modified power connections of 73/73 cells.
|
||||
Modified power connections of 98/98 cells.
|
||||
|
|
@ -3,5 +3,5 @@ This program is licensed under the BSD-3 license. See the LICENSE file for detai
|
|||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
Setting global connections for newly added cells...
|
||||
[WARNING] Did not save OpenROAD database!
|
||||
Writing netlist to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/25-buff_flash_clkrst.nl.v...
|
||||
Writing powered netlist to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/25-buff_flash_clkrst.pnl.v...
|
||||
Writing netlist to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.nl.v...
|
||||
Writing powered netlist to /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.pnl.v...
|
||||
|
|
@ -70,24 +70,45 @@
|
|||
]
|
||||
},
|
||||
{
|
||||
"name": [
|
||||
"sky130_fd_sc_hd__diode_2",
|
||||
"sky130_fd_sc_hd__diode_2"
|
||||
],
|
||||
"devices": [
|
||||
[
|
||||
["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
|
||||
], [
|
||||
["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
|
||||
]
|
||||
],
|
||||
"nets": [
|
||||
2,
|
||||
2
|
||||
],
|
||||
"badnets": [
|
||||
],
|
||||
"badelements": [
|
||||
],
|
||||
"pins": [
|
||||
[
|
||||
"VNB",
|
||||
"DIODE",
|
||||
"VGND",
|
||||
"VPWR",
|
||||
"VNB",
|
||||
"VPB"
|
||||
], [
|
||||
"VNB",
|
||||
"DIODE",
|
||||
"VGND",
|
||||
"VPWR",
|
||||
"VNB",
|
||||
"VPB"
|
||||
]
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": [
|
||||
"sky130_fd_sc_hd__decap_4",
|
||||
"sky130_fd_sc_hd__decap_4"
|
||||
"sky130_fd_sc_hd__decap_3",
|
||||
"sky130_fd_sc_hd__decap_3"
|
||||
],
|
||||
"devices": [
|
||||
[
|
||||
|
|
@ -122,8 +143,8 @@
|
|||
},
|
||||
{
|
||||
"name": [
|
||||
"sky130_fd_sc_hd__decap_3",
|
||||
"sky130_fd_sc_hd__decap_3"
|
||||
"sky130_fd_sc_hd__decap_4",
|
||||
"sky130_fd_sc_hd__decap_4"
|
||||
],
|
||||
"devices": [
|
||||
[
|
||||
|
|
@ -192,6 +213,42 @@
|
|||
]
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": [
|
||||
"sky130_fd_sc_hd__decap_6",
|
||||
"sky130_fd_sc_hd__decap_6"
|
||||
],
|
||||
"devices": [
|
||||
[
|
||||
["sky130_fd_pr__pfet_01v8_hvt", 1],
|
||||
["sky130_fd_pr__nfet_01v8", 1 ]
|
||||
], [
|
||||
["sky130_fd_pr__pfet_01v8_hvt", 1 ],
|
||||
["sky130_fd_pr__nfet_01v8", 1 ]
|
||||
]
|
||||
],
|
||||
"nets": [
|
||||
4,
|
||||
4
|
||||
],
|
||||
"badnets": [
|
||||
],
|
||||
"badelements": [
|
||||
],
|
||||
"pins": [
|
||||
[
|
||||
"VPB",
|
||||
"VNB",
|
||||
"VPWR",
|
||||
"VGND"
|
||||
], [
|
||||
"VPB",
|
||||
"VNB",
|
||||
"VPWR",
|
||||
"VGND"
|
||||
]
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": [
|
||||
"buff_flash_clkrst",
|
||||
|
|
@ -200,16 +257,18 @@
|
|||
"devices": [
|
||||
[
|
||||
["sky130_fd_sc_hd__clkbuf_8", 15],
|
||||
["sky130_ef_sc_hd__decap_12", 1],
|
||||
["sky130_fd_sc_hd__decap_4", 1],
|
||||
["sky130_fd_sc_hd__diode_2", 15],
|
||||
["sky130_fd_sc_hd__decap_3", 1],
|
||||
["sky130_fd_sc_hd__decap_8", 1 ]
|
||||
["sky130_fd_sc_hd__decap_4", 1],
|
||||
["sky130_fd_sc_hd__decap_8", 1],
|
||||
["sky130_fd_sc_hd__decap_6", 1 ]
|
||||
], [
|
||||
["sky130_fd_sc_hd__clkbuf_8", 15 ],
|
||||
["sky130_ef_sc_hd__decap_12", 1 ],
|
||||
["sky130_fd_sc_hd__decap_4", 1 ],
|
||||
["sky130_fd_sc_hd__diode_2", 15 ],
|
||||
["sky130_fd_sc_hd__decap_3", 1 ],
|
||||
["sky130_fd_sc_hd__decap_8", 1 ]
|
||||
["sky130_fd_sc_hd__decap_4", 1 ],
|
||||
["sky130_fd_sc_hd__decap_8", 1 ],
|
||||
["sky130_fd_sc_hd__decap_6", 1 ]
|
||||
]
|
||||
],
|
||||
"nets": [
|
||||
|
|
@ -224,69 +283,69 @@
|
|||
[
|
||||
"VGND",
|
||||
"VPWR",
|
||||
"in_n[4]",
|
||||
"in_n[9]",
|
||||
"in_n[11]",
|
||||
"in_n[6]",
|
||||
"in_s[0]",
|
||||
"in_s[2]",
|
||||
"in_n[1]",
|
||||
"in_n[8]",
|
||||
"in_n[3]",
|
||||
"in_n[5]",
|
||||
"in_n[10]",
|
||||
"in_s[1]",
|
||||
"in_n[0]",
|
||||
"in_n[2]",
|
||||
"in_n[7]",
|
||||
"out_s[4]",
|
||||
"out_s[9]",
|
||||
"out_s[11]",
|
||||
"out_s[6]",
|
||||
"out_n[0]",
|
||||
"out_n[2]",
|
||||
"out_s[1]",
|
||||
"out_s[8]",
|
||||
"out_s[3]",
|
||||
"out_s[5]",
|
||||
"out_s[10]",
|
||||
"out_n[1]",
|
||||
"out_s[0]",
|
||||
"out_s[2]",
|
||||
"out_s[7]"
|
||||
"in_e[9]",
|
||||
"in_e[4]",
|
||||
"in_e[1]",
|
||||
"in_w[2]",
|
||||
"in_e[10]",
|
||||
"in_e[5]",
|
||||
"in_e[11]",
|
||||
"in_e[6]",
|
||||
"in_e[8]",
|
||||
"in_e[3]",
|
||||
"in_w[1]",
|
||||
"in_e[0]",
|
||||
"in_w[0]",
|
||||
"in_e[7]",
|
||||
"in_e[2]",
|
||||
"out_w[9]",
|
||||
"out_w[4]",
|
||||
"out_w[11]",
|
||||
"out_w[6]",
|
||||
"out_e[0]",
|
||||
"out_e[2]",
|
||||
"out_w[1]",
|
||||
"out_w[8]",
|
||||
"out_w[3]",
|
||||
"out_w[10]",
|
||||
"out_w[5]",
|
||||
"out_e[1]",
|
||||
"out_w[0]",
|
||||
"out_w[7]",
|
||||
"out_w[2]"
|
||||
], [
|
||||
"VGND",
|
||||
"VPWR",
|
||||
"in_n[4]",
|
||||
"in_n[9]",
|
||||
"in_n[11]",
|
||||
"in_n[6]",
|
||||
"in_s[0]",
|
||||
"in_s[2]",
|
||||
"in_n[1]",
|
||||
"in_n[8]",
|
||||
"in_n[3]",
|
||||
"in_n[5]",
|
||||
"in_n[10]",
|
||||
"in_s[1]",
|
||||
"in_n[0]",
|
||||
"in_n[2]",
|
||||
"in_n[7]",
|
||||
"out_s[4]",
|
||||
"out_s[9]",
|
||||
"out_s[11]",
|
||||
"out_s[6]",
|
||||
"out_n[0]",
|
||||
"out_n[2]",
|
||||
"out_s[1]",
|
||||
"out_s[8]",
|
||||
"out_s[3]",
|
||||
"out_s[5]",
|
||||
"out_s[10]",
|
||||
"out_n[1]",
|
||||
"out_s[0]",
|
||||
"out_s[2]",
|
||||
"out_s[7]"
|
||||
"in_e[9]",
|
||||
"in_e[4]",
|
||||
"in_e[1]",
|
||||
"in_w[2]",
|
||||
"in_e[10]",
|
||||
"in_e[5]",
|
||||
"in_e[11]",
|
||||
"in_e[6]",
|
||||
"in_e[8]",
|
||||
"in_e[3]",
|
||||
"in_w[1]",
|
||||
"in_e[0]",
|
||||
"in_w[0]",
|
||||
"in_e[7]",
|
||||
"in_e[2]",
|
||||
"out_w[9]",
|
||||
"out_w[4]",
|
||||
"out_w[11]",
|
||||
"out_w[6]",
|
||||
"out_e[0]",
|
||||
"out_e[2]",
|
||||
"out_w[1]",
|
||||
"out_w[8]",
|
||||
"out_w[3]",
|
||||
"out_w[10]",
|
||||
"out_w[5]",
|
||||
"out_e[1]",
|
||||
"out_w[0]",
|
||||
"out_w[7]",
|
||||
"out_w[2]"
|
||||
]
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
|
||||
Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
|
||||
Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
|
||||
Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
|
||||
-------------------------------------------|-------------------------------------------
|
||||
1 |1
|
||||
2 |2
|
||||
3 |3
|
||||
4 |4
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
|
||||
|
||||
Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
|
||||
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
|
||||
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
|
||||
-------------------------------------------|-------------------------------------------
|
||||
1 |1
|
||||
2 |2
|
||||
3 |3
|
||||
4 |4
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
|
||||
|
||||
Class sky130_fd_sc_hd__clkbuf_8 (0): Merged 16 parallel devices.
|
||||
Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices.
|
||||
Subcircuit summary:
|
||||
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
|
||||
sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
|
||||
Number of devices: 4 |Number of devices: 4
|
||||
Number of nets: 7 |Number of nets: 7
|
||||
---------------------------------------------------------------------------------------
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
|
||||
-------------------------------------------|-------------------------------------------
|
||||
X |X
|
||||
VGND |VGND
|
||||
VNB |VNB
|
||||
A |A
|
||||
VPWR |VPWR
|
||||
VPB |VPB
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
|
||||
|
||||
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
|
||||
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
|
||||
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
|
||||
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
|
||||
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
|
||||
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
|
||||
Subcircuit summary:
|
||||
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
|
||||
Number of devices: 1 |Number of devices: 1
|
||||
Number of nets: 2 |Number of nets: 2
|
||||
---------------------------------------------------------------------------------------
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
|
||||
-------------------------------------------|-------------------------------------------
|
||||
VNB |VNB
|
||||
DIODE |DIODE
|
||||
VGND |VGND
|
||||
VPWR |VPWR
|
||||
VPB |VPB
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
|
||||
|
||||
Subcircuit summary:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
||||
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
||||
Number of devices: 2 |Number of devices: 2
|
||||
Number of nets: 4 |Number of nets: 4
|
||||
---------------------------------------------------------------------------------------
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
|
||||
-------------------------------------------|-------------------------------------------
|
||||
VPB |VPB
|
||||
VNB |VNB
|
||||
VPWR |VPWR
|
||||
VGND |VGND
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
|
||||
|
||||
Subcircuit summary:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
||||
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
||||
Number of devices: 2 |Number of devices: 2
|
||||
Number of nets: 4 |Number of nets: 4
|
||||
---------------------------------------------------------------------------------------
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
|
||||
-------------------------------------------|-------------------------------------------
|
||||
VPB |VPB
|
||||
VNB |VNB
|
||||
VPWR |VPWR
|
||||
VGND |VGND
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
|
||||
|
||||
Subcircuit summary:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
||||
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
||||
Number of devices: 2 |Number of devices: 2
|
||||
Number of nets: 4 |Number of nets: 4
|
||||
---------------------------------------------------------------------------------------
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
|
||||
-------------------------------------------|-------------------------------------------
|
||||
VPB |VPB
|
||||
VNB |VNB
|
||||
VPWR |VPWR
|
||||
VGND |VGND
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
|
||||
|
||||
Subcircuit summary:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
||||
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
||||
Number of devices: 2 |Number of devices: 2
|
||||
Number of nets: 4 |Number of nets: 4
|
||||
---------------------------------------------------------------------------------------
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
|
||||
-------------------------------------------|-------------------------------------------
|
||||
VPB |VPB
|
||||
VNB |VNB
|
||||
VPWR |VPWR
|
||||
VGND |VGND
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
|
||||
|
||||
Class buff_flash_clkrst (0): Merged 34 parallel devices.
|
||||
Class buff_flash_clkrst (1): Merged 34 parallel devices.
|
||||
Subcircuit summary:
|
||||
Circuit 1: buff_flash_clkrst |Circuit 2: buff_flash_clkrst
|
||||
-------------------------------------------|-------------------------------------------
|
||||
sky130_fd_sc_hd__clkbuf_8 (15) |sky130_fd_sc_hd__clkbuf_8 (15)
|
||||
sky130_fd_sc_hd__diode_2 (15) |sky130_fd_sc_hd__diode_2 (15)
|
||||
sky130_fd_sc_hd__decap_3 (13->1) |sky130_fd_sc_hd__decap_3 (13->1)
|
||||
sky130_fd_sc_hd__decap_4 (21->1) |sky130_fd_sc_hd__decap_4 (21->1)
|
||||
sky130_fd_sc_hd__decap_8 (2->1) |sky130_fd_sc_hd__decap_8 (2->1)
|
||||
sky130_fd_sc_hd__decap_6 (2->1) |sky130_fd_sc_hd__decap_6 (2->1)
|
||||
Number of devices: 34 |Number of devices: 34
|
||||
Number of nets: 32 |Number of nets: 32
|
||||
---------------------------------------------------------------------------------------
|
||||
Resolving automorphisms by property value.
|
||||
Resolving automorphisms by pin name.
|
||||
Netlists match uniquely.
|
||||
|
||||
Subcircuit pins:
|
||||
Circuit 1: buff_flash_clkrst |Circuit 2: buff_flash_clkrst
|
||||
-------------------------------------------|-------------------------------------------
|
||||
VGND |VGND
|
||||
VPWR |VPWR
|
||||
in_e[9] |in_e[9]
|
||||
in_e[4] |in_e[4]
|
||||
in_e[1] |in_e[1]
|
||||
in_w[2] |in_w[2]
|
||||
in_e[10] |in_e[10]
|
||||
in_e[5] |in_e[5]
|
||||
in_e[11] |in_e[11]
|
||||
in_e[6] |in_e[6]
|
||||
in_e[8] |in_e[8]
|
||||
in_e[3] |in_e[3]
|
||||
in_w[1] |in_w[1]
|
||||
in_e[0] |in_e[0]
|
||||
in_w[0] |in_w[0]
|
||||
in_e[7] |in_e[7]
|
||||
in_e[2] |in_e[2]
|
||||
out_w[9] |out_w[9]
|
||||
out_w[4] |out_w[4]
|
||||
out_w[11] |out_w[11]
|
||||
out_w[6] |out_w[6]
|
||||
out_e[0] |out_e[0]
|
||||
out_e[2] |out_e[2]
|
||||
out_w[1] |out_w[1]
|
||||
out_w[8] |out_w[8]
|
||||
out_w[3] |out_w[3]
|
||||
out_w[10] |out_w[10]
|
||||
out_w[5] |out_w[5]
|
||||
out_e[1] |out_e[1]
|
||||
out_w[0] |out_w[0]
|
||||
out_w[7] |out_w[7]
|
||||
out_w[2] |out_w[2]
|
||||
---------------------------------------------------------------------------------------
|
||||
Cell pin lists are equivalent.
|
||||
Device classes buff_flash_clkrst and buff_flash_clkrst are equivalent.
|
||||
|
||||
Final result: Circuits match uniquely.
|
||||
.
|
||||
|
|
@ -11,14 +11,13 @@ Creating placeholder cell definition.
|
|||
Call to undefined subcircuit sky130_fd_sc_hd__nor2_2
|
||||
Creating placeholder cell definition.
|
||||
Generating JSON file result
|
||||
Reading netlist file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.gds.spice
|
||||
Reading netlist file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.gds.spice
|
||||
Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
|
||||
Creating placeholder cell definition.
|
||||
Call to undefined subcircuit sky130_fd_pr__nfet_01v8
|
||||
Creating placeholder cell definition.
|
||||
Reading netlist file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/25-buff_flash_clkrst.pnl.v
|
||||
Reading netlist file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.pnl.v
|
||||
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
|
||||
Creating placeholder cell definition for module sky130_ef_sc_hd__decap_12.
|
||||
Reading setup file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl
|
||||
Model sky130_fd_pr__res_generic_po pin end_a == end_b
|
||||
No property mult found for device sky130_fd_pr__res_generic_po
|
||||
|
|
@ -77,8 +76,11 @@ No property topography found for device sky130_fd_pr__pfet_01v8_hvt
|
|||
No property value found for device sky130_fd_pr__diode_pw2nd_05v5
|
||||
No property mult found for device sky130_fd_pr__diode_pw2nd_05v5
|
||||
No property perim found for device sky130_fd_pr__diode_pw2nd_05v5
|
||||
Comparison output logged to file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/logs/signoff/28-buff_flash_clkrst.gds.log
|
||||
Logging to file "/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/logs/signoff/28-buff_flash_clkrst.gds.log" enabled
|
||||
No property value found for device sky130_fd_pr__diode_pw2nd_05v5
|
||||
No property mult found for device sky130_fd_pr__diode_pw2nd_05v5
|
||||
No property perim found for device sky130_fd_pr__diode_pw2nd_05v5
|
||||
Comparison output logged to file /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/signoff/30-buff_flash_clkrst.gds.lvs.log
|
||||
Logging to file "/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/signoff/30-buff_flash_clkrst.gds.lvs.log" enabled
|
||||
Circuit sky130_fd_pr__pfet_01v8_hvt contains no devices.
|
||||
Circuit sky130_fd_pr__nfet_01v8 contains no devices.
|
||||
|
||||
|
|
@ -110,21 +112,18 @@ Circuit contains 7 nets.
|
|||
Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
|
||||
Circuit 1 contains 7 nets, Circuit 2 contains 7 nets.
|
||||
|
||||
Circuit sky130_ef_sc_hd__decap_12 contains no devices.
|
||||
|
||||
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_4'
|
||||
Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
|
||||
Circuit contains 4 nets.
|
||||
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_4'
|
||||
Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
|
||||
Circuit contains 4 nets.
|
||||
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__diode_2'
|
||||
Circuit sky130_fd_sc_hd__diode_2 contains 1 device instances.
|
||||
Class: sky130_fd_pr__diode_pw2nd_05v5 instances: 1
|
||||
Circuit contains 2 nets, and 3 disconnected pins.
|
||||
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__diode_2'
|
||||
Circuit sky130_fd_sc_hd__diode_2 contains 1 device instances.
|
||||
Class: sky130_fd_pr__diode_pw2nd_05v5 instances: 1
|
||||
Circuit contains 2 nets, and 3 disconnected pins.
|
||||
|
||||
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
|
||||
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
|
||||
Circuit 1 contains 1 devices, Circuit 2 contains 1 devices.
|
||||
Circuit 1 contains 2 nets, Circuit 2 contains 2 nets.
|
||||
|
||||
|
||||
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_3'
|
||||
|
|
@ -142,6 +141,21 @@ Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
|
|||
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
|
||||
|
||||
|
||||
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_4'
|
||||
Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
|
||||
Circuit contains 4 nets.
|
||||
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_4'
|
||||
Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
|
||||
Circuit contains 4 nets.
|
||||
|
||||
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
|
||||
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
|
||||
|
||||
|
||||
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_8'
|
||||
Circuit sky130_fd_sc_hd__decap_8 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
|
|
@ -157,49 +171,68 @@ Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
|
|||
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
|
||||
|
||||
|
||||
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_6'
|
||||
Circuit sky130_fd_sc_hd__decap_6 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
|
||||
Circuit contains 4 nets.
|
||||
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_6'
|
||||
Circuit sky130_fd_sc_hd__decap_6 contains 2 device instances.
|
||||
Class: sky130_fd_pr__nfet_01v8 instances: 1
|
||||
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
|
||||
Circuit contains 4 nets.
|
||||
|
||||
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
|
||||
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
|
||||
|
||||
|
||||
Contents of circuit 1: Circuit: 'buff_flash_clkrst'
|
||||
Circuit buff_flash_clkrst contains 48 device instances.
|
||||
Class: sky130_ef_sc_hd__decap_12 instances: 7
|
||||
Circuit buff_flash_clkrst contains 68 device instances.
|
||||
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
|
||||
Class: sky130_fd_sc_hd__decap_3 instances: 12
|
||||
Class: sky130_fd_sc_hd__decap_4 instances: 10
|
||||
Class: sky130_fd_sc_hd__decap_8 instances: 4
|
||||
Class: sky130_fd_sc_hd__decap_3 instances: 13
|
||||
Class: sky130_fd_sc_hd__decap_4 instances: 21
|
||||
Class: sky130_fd_sc_hd__decap_6 instances: 2
|
||||
Class: sky130_fd_sc_hd__decap_8 instances: 2
|
||||
Class: sky130_fd_sc_hd__diode_2 instances: 15
|
||||
Circuit contains 32 nets.
|
||||
Contents of circuit 2: Circuit: 'buff_flash_clkrst'
|
||||
Circuit buff_flash_clkrst contains 48 device instances.
|
||||
Class: sky130_ef_sc_hd__decap_12 instances: 7
|
||||
Circuit buff_flash_clkrst contains 68 device instances.
|
||||
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
|
||||
Class: sky130_fd_sc_hd__decap_3 instances: 12
|
||||
Class: sky130_fd_sc_hd__decap_4 instances: 10
|
||||
Class: sky130_fd_sc_hd__decap_8 instances: 4
|
||||
Class: sky130_fd_sc_hd__decap_3 instances: 13
|
||||
Class: sky130_fd_sc_hd__decap_4 instances: 21
|
||||
Class: sky130_fd_sc_hd__decap_6 instances: 2
|
||||
Class: sky130_fd_sc_hd__decap_8 instances: 2
|
||||
Class: sky130_fd_sc_hd__diode_2 instances: 15
|
||||
Circuit contains 32 nets.
|
||||
|
||||
Circuit was modified by parallel/series device merging.
|
||||
New circuit summary:
|
||||
|
||||
Contents of circuit 1: Circuit: 'buff_flash_clkrst'
|
||||
Circuit buff_flash_clkrst contains 19 device instances.
|
||||
Class: sky130_ef_sc_hd__decap_12 instances: 1
|
||||
Circuit buff_flash_clkrst contains 34 device instances.
|
||||
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
|
||||
Class: sky130_fd_sc_hd__decap_3 instances: 1
|
||||
Class: sky130_fd_sc_hd__decap_4 instances: 1
|
||||
Class: sky130_fd_sc_hd__decap_6 instances: 1
|
||||
Class: sky130_fd_sc_hd__decap_8 instances: 1
|
||||
Class: sky130_fd_sc_hd__diode_2 instances: 15
|
||||
Circuit contains 32 nets.
|
||||
Contents of circuit 2: Circuit: 'buff_flash_clkrst'
|
||||
Circuit buff_flash_clkrst contains 19 device instances.
|
||||
Class: sky130_ef_sc_hd__decap_12 instances: 1
|
||||
Circuit buff_flash_clkrst contains 34 device instances.
|
||||
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
|
||||
Class: sky130_fd_sc_hd__decap_3 instances: 1
|
||||
Class: sky130_fd_sc_hd__decap_4 instances: 1
|
||||
Class: sky130_fd_sc_hd__decap_6 instances: 1
|
||||
Class: sky130_fd_sc_hd__decap_8 instances: 1
|
||||
Class: sky130_fd_sc_hd__diode_2 instances: 15
|
||||
Circuit contains 32 nets.
|
||||
|
||||
Circuit 1 contains 19 devices, Circuit 2 contains 19 devices.
|
||||
Circuit 1 contains 34 devices, Circuit 2 contains 34 devices.
|
||||
Circuit 1 contains 32 nets, Circuit 2 contains 32 nets.
|
||||
|
||||
|
||||
Final result:
|
||||
Circuits match uniquely.
|
||||
.
|
||||
Logging to file "/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/logs/signoff/28-buff_flash_clkrst.gds.log" disabled
|
||||
Logging to file "/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/signoff/30-buff_flash_clkrst.gds.lvs.log" disabled
|
||||
LVS Done.
|
||||
|
|
@ -19,10 +19,11 @@ Reading "sky130_fd_sc_hd__clkbuf_8".
|
|||
Reading "sky130_fd_sc_hd__decap_4".
|
||||
Reading "sky130_fd_sc_hd__fill_1".
|
||||
Reading "sky130_fd_sc_hd__decap_3".
|
||||
Reading "sky130_fd_sc_hd__decap_8".
|
||||
Reading "sky130_ef_sc_hd__decap_12".
|
||||
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
|
||||
Reading "sky130_fd_sc_hd__diode_2".
|
||||
Reading "sky130_fd_sc_hd__fill_2".
|
||||
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
|
||||
Reading "sky130_fd_sc_hd__decap_6".
|
||||
Reading "sky130_fd_sc_hd__decap_8".
|
||||
Reading "buff_flash_clkrst".
|
||||
[INFO]: Loading buff_flash_clkrst
|
||||
|
||||
|
|
@ -31,6 +32,6 @@ Loading DRC CIF style.
|
|||
No errors found.
|
||||
[INFO]: COUNT: 0
|
||||
[INFO]: Should be divided by 3 or 4
|
||||
[INFO]: DRC Checking DONE (/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/drc.rpt)
|
||||
[INFO]: Saving mag view with DRC errors (/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.drc.mag)
|
||||
[INFO]: DRC Checking DONE (/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/drc.rpt)
|
||||
[INFO]: Saving mag view with DRC errors (/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.drc.mag)
|
||||
[INFO]: Saved
|
||||
|
|
@ -0,0 +1,746 @@
|
|||
# Run configs
|
||||
set ::env(PDK_ROOT) {/home/hosni/OL_LATEST/OpenLane/pdks}
|
||||
set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
|
||||
set ::env(BOTTOM_MARGIN_MULT) {2}
|
||||
set ::env(CARRY_SELECT_ADDER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v}
|
||||
set ::env(CELLS_LEF) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELLS_LEF_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELL_CLK_PORT) {CLK}
|
||||
set ::env(CELL_PAD_EXCLUDE) {sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*}
|
||||
set ::env(CHECK_ASSIGN_STATEMENTS) {0}
|
||||
set ::env(CHECK_UNMAPPED_CELLS) {1}
|
||||
set ::env(CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
|
||||
set ::env(CLK_BUFFER_INPUT) {A}
|
||||
set ::env(CLK_BUFFER_OUTPUT) {X}
|
||||
set ::env(CLOCK_BUFFER_FANOUT) {16}
|
||||
set ::env(CLOCK_PERIOD) {8}
|
||||
set ::env(CLOCK_PORT) {}
|
||||
set ::env(CLOCK_TREE_SYNTH) {0}
|
||||
set ::env(CLOCK_WIRE_RC_LAYER) {met5}
|
||||
set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
|
||||
set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2}
|
||||
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
|
||||
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
|
||||
set ::env(CTS_MAX_CAP) {1.53169}
|
||||
set ::env(CTS_REPORT_TIMING) {1}
|
||||
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
|
||||
set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
|
||||
set ::env(CTS_SQR_CAP) {0.258e-3}
|
||||
set ::env(CTS_SQR_RES) {0.125}
|
||||
set ::env(CTS_TARGET_SKEW) {200}
|
||||
set ::env(CTS_TECH_DIR) {N/A}
|
||||
set ::env(CTS_TOLERANCE) {100}
|
||||
set ::env(CVC_SCRIPTS_DIR) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/cvc}
|
||||
set ::env(DATA_WIRE_RC_LAYER) {met2}
|
||||
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
|
||||
set ::env(DEFAULT_MAX_TRAN) {0.75}
|
||||
set ::env(DEF_UNITS_PER_MICRON) {1000}
|
||||
set ::env(DESIGN_CONFIG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/config.tcl}
|
||||
set ::env(DESIGN_IS_CORE) {0}
|
||||
set ::env(DESIGN_NAME) {buff_flash_clkrst}
|
||||
set ::env(DETAILED_ROUTER) {tritonroute}
|
||||
set ::env(DIE_AREA) {0 0 40 25}
|
||||
set ::env(DIODE_CELL) {sky130_fd_sc_hd__diode_2}
|
||||
set ::env(DIODE_CELL_PIN) {DIODE}
|
||||
set ::env(DIODE_INSERTION_STRATEGY) {3}
|
||||
set ::env(DIODE_PADDING) {2}
|
||||
set ::env(DPL_CELL_PADDING) {4}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/drc_exclude.list}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
|
||||
set ::env(DRT_OPT_ITERS) {64}
|
||||
set ::env(ECO_ENABLE) {0}
|
||||
set ::env(ECO_FINISH) {0}
|
||||
set ::env(ECO_ITER) {0}
|
||||
set ::env(ECO_SKIP_PIN) {1}
|
||||
set ::env(FAKEDIODE_CELL) {sky130_ef_sc_hd__fakediode_2}
|
||||
set ::env(FILL_CELL) {sky130_fd_sc_hd__fill*}
|
||||
set ::env(FILL_INSERTION) {1}
|
||||
set ::env(FP_ASPECT_RATIO) {1}
|
||||
set ::env(FP_CORE_UTIL) {50}
|
||||
set ::env(FP_ENDCAP_CELL) {sky130_fd_sc_hd__decap_3}
|
||||
set ::env(FP_IO_HEXTEND) {-1}
|
||||
set ::env(FP_IO_HLAYER) {met3}
|
||||
set ::env(FP_IO_HLENGTH) {4}
|
||||
set ::env(FP_IO_HTHICKNESS_MULT) {2}
|
||||
set ::env(FP_IO_MIN_DISTANCE) {3}
|
||||
set ::env(FP_IO_MODE) {1}
|
||||
set ::env(FP_IO_UNMATCHED_ERROR) {1}
|
||||
set ::env(FP_IO_VEXTEND) {-1}
|
||||
set ::env(FP_IO_VLAYER) {met2}
|
||||
set ::env(FP_IO_VLENGTH) {4}
|
||||
set ::env(FP_IO_VTHICKNESS_MULT) {2}
|
||||
set ::env(FP_PDN_AUTO_ADJUST) {1}
|
||||
set ::env(FP_PDN_CHECK_NODES) {1}
|
||||
set ::env(FP_PDN_CORE_RING) {0}
|
||||
set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
|
||||
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
|
||||
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
|
||||
set ::env(FP_PDN_ENABLE_RAILS) {1}
|
||||
set ::env(FP_PDN_HOFFSET) {16.65}
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_PDN_HPITCH) {153.18}
|
||||
set ::env(FP_PDN_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_IRDROP) {1}
|
||||
set ::env(FP_PDN_LOWER_LAYER) {met4}
|
||||
set ::env(FP_PDN_RAILS_LAYER) {met1}
|
||||
set ::env(FP_PDN_RAIL_OFFSET) {0}
|
||||
set ::env(FP_PDN_RAIL_WIDTH) {0.48}
|
||||
set ::env(FP_PDN_SKIPTRIM) {0}
|
||||
set ::env(FP_PDN_UPPER_LAYER) {met5}
|
||||
set ::env(FP_PDN_VERTICAL_HALO) {10}
|
||||
set ::env(FP_PDN_VOFFSET) {2}
|
||||
set ::env(FP_PDN_VPITCH) {7}
|
||||
set ::env(FP_PDN_VSPACING) {2}
|
||||
set ::env(FP_PDN_VWIDTH) {1.6}
|
||||
set ::env(FP_PIN_ORDER_CFG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/pin_order.cfg}
|
||||
set ::env(FP_SIZING) {absolute}
|
||||
set ::env(FP_TAPCELL_DIST) {13}
|
||||
set ::env(FP_TAP_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_TAP_VERTICAL_HALO) {10}
|
||||
set ::env(FP_WELLTAP_CELL) {sky130_fd_sc_hd__tapvpwrvgnd_1}
|
||||
set ::env(FULL_ADDER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v}
|
||||
set ::env(GDS_FILES) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GDS_FILES_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
|
||||
set ::env(GLB_CFG_FILE) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/config.tcl}
|
||||
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
|
||||
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(GLOBAL_ROUTER) {fastroute}
|
||||
set ::env(GND_PIN) {VGND}
|
||||
set ::env(GPIO_PADS_LEF) { /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef }
|
||||
set ::env(GPIO_PADS_LEF_CORE_SIDE) { /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef }
|
||||
set ::env(GPIO_PADS_VERILOG) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/verilog/sky130_fd_io/sky130_ef_io.v}
|
||||
set ::env(GPL_CELL_PADDING) {0}
|
||||
set ::env(GRT_ADJUSTMENT) {0.3}
|
||||
set ::env(GRT_ALLOW_CONGESTION) {0}
|
||||
set ::env(GRT_ANT_ITERS) {3}
|
||||
set ::env(GRT_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(GRT_LAYER_ADJUSTMENTS) {0.99,0,0,0,0,0}
|
||||
set ::env(GRT_MACRO_EXTENSION) {0}
|
||||
set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
|
||||
set ::env(GRT_OVERFLOW_ITERS) {50}
|
||||
set ::env(IO_PCT) {0.2}
|
||||
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
|
||||
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/drc/sky130A_mr.drc}
|
||||
set ::env(KLAYOUT_PROPERTIES) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp}
|
||||
set ::env(KLAYOUT_TECH) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt}
|
||||
set ::env(KLAYOUT_XOR_GDS) {1}
|
||||
set ::env(KLAYOUT_XOR_XML) {1}
|
||||
set ::env(LEC_ENABLE) {0}
|
||||
set ::env(LEFT_MARGIN_MULT) {4}
|
||||
set ::env(LIB_FASTEST) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib}
|
||||
set ::env(LIB_SLOWEST) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SLOWEST_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SYNTH) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LIB_TYPICAL) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LOGS_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs}
|
||||
set ::env(LVS_CONNECT_BY_LABEL) {0}
|
||||
set ::env(LVS_INSERT_POWER_PINS) {1}
|
||||
set ::env(MACRO_BLOCKAGES_LAYER) {li1 met1 met2 met3 met4}
|
||||
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
|
||||
set ::env(MAGIC_DEF_LABELS) {1}
|
||||
set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
|
||||
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
|
||||
set ::env(MAGIC_DRC_USE_GDS) {1}
|
||||
set ::env(MAGIC_EXT_USE_GDS) {1}
|
||||
set ::env(MAGIC_GENERATE_GDS) {1}
|
||||
set ::env(MAGIC_GENERATE_LEF) {1}
|
||||
set ::env(MAGIC_GENERATE_MAGLEF) {1}
|
||||
set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
|
||||
set ::env(MAGIC_MAGICRC) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc}
|
||||
set ::env(MAGIC_PAD) {0}
|
||||
set ::env(MAGIC_TECH_FILE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech}
|
||||
set ::env(MAGIC_WRITE_FULL_LEF) {0}
|
||||
set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
|
||||
set ::env(NETGEN_SETUP_FILE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl}
|
||||
set ::env(NO_SYNTH_CELL_LIST) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells}
|
||||
set ::env(OPENLANE_VERBOSE) {1}
|
||||
set ::env(PDKPATH) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A}
|
||||
set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
|
||||
set ::env(PLACE_SITE) {unithd}
|
||||
set ::env(PLACE_SITE_HEIGHT) {2.720}
|
||||
set ::env(PLACE_SITE_WIDTH) {0.460}
|
||||
set ::env(PL_BASIC_PLACEMENT) {0}
|
||||
set ::env(PL_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(PL_LIB) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(PL_MACRO_CHANNEL) {0 0}
|
||||
set ::env(PL_MACRO_HALO) {0 0}
|
||||
set ::env(PL_MAX_DISPLACEMENT_X) {500}
|
||||
set ::env(PL_MAX_DISPLACEMENT_Y) {100}
|
||||
set ::env(PL_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
|
||||
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
|
||||
set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
|
||||
set ::env(PL_RESIZER_TIE_SEPERATION) {0}
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_ROUTABILITY_DRIVEN) {1}
|
||||
set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_TARGET_DENSITY) {0.96}
|
||||
set ::env(PL_TIME_DRIVEN) {1}
|
||||
set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
|
||||
set ::env(PROCESS) {130}
|
||||
set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
|
||||
set ::env(QUIT_ON_LVS_ERROR) {1}
|
||||
set ::env(QUIT_ON_MAGIC_DRC) {1}
|
||||
set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TR_DRC) {1}
|
||||
set ::env(RCX_CC_MODEL) {10}
|
||||
set ::env(RCX_CONTEXT_DEPTH) {5}
|
||||
set ::env(RCX_CORNER_COUNT) {1}
|
||||
set ::env(RCX_COUPLING_THRESHOLD) {0.1}
|
||||
set ::env(RCX_MAX_RESISTANCE) {50}
|
||||
set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
|
||||
set ::env(RCX_RULES) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre}
|
||||
set ::env(RCX_RULES_MAX) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre}
|
||||
set ::env(RCX_RULES_MIN) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre}
|
||||
set ::env(REPORTS_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports}
|
||||
set ::env(RESULTS_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results}
|
||||
set ::env(RE_BUFFER_CELL) {sky130_fd_sc_hd__buf_4}
|
||||
set ::env(RIGHT_MARGIN_MULT) {4}
|
||||
set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v}
|
||||
set ::env(ROOT_CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(ROUTING_CORES) {2}
|
||||
set ::env(RSZ_DONT_TOUCH_RX) {$^}
|
||||
set ::env(RSZ_USE_OLD_REMOVER) {0}
|
||||
set ::env(RT_MAX_LAYER) {met5}
|
||||
set ::env(RT_MIN_LAYER) {met1}
|
||||
set ::env(RUN_CVC) {1}
|
||||
set ::env(RUN_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27}
|
||||
set ::env(RUN_DRT) {1}
|
||||
set ::env(RUN_IRDROP_REPORT) {1}
|
||||
set ::env(RUN_KLAYOUT) {1}
|
||||
set ::env(RUN_KLAYOUT_DRC) {0}
|
||||
set ::env(RUN_KLAYOUT_XOR) {1}
|
||||
set ::env(RUN_LVS) {1}
|
||||
set ::env(RUN_MAGIC) {1}
|
||||
set ::env(RUN_MAGIC_DRC) {1}
|
||||
set ::env(RUN_SPEF_EXTRACTION) {1}
|
||||
set ::env(RUN_TAG) {22_10_15_06_27}
|
||||
set ::env(SPEF_EXTRACTOR) {openrcx}
|
||||
set ::env(START_TIME) {2022.10.15_13.27.23}
|
||||
set ::env(STA_REPORT_POWER) {1}
|
||||
set ::env(STA_WRITE_LIB) {1}
|
||||
set ::env(STD_CELL_GROUND_PINS) {VGND VNB}
|
||||
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_CDL) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_LIBRARY_OPT) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_OPT_CDL) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_POWER_PINS) {VPWR VPB}
|
||||
set ::env(SYNTH_ADDER_TYPE) {YOSYS}
|
||||
set ::env(SYNTH_BIN) {yosys}
|
||||
set ::env(SYNTH_BUFFERING) {0}
|
||||
set ::env(SYNTH_CAP_LOAD) {33.442}
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
|
||||
set ::env(SYNTH_DRIVING_CELL) {sky130_fd_sc_hd__inv_2}
|
||||
set ::env(SYNTH_DRIVING_CELL_PIN) {Y}
|
||||
set ::env(SYNTH_ELABORATE_ONLY) {0}
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
|
||||
set ::env(SYNTH_FLAT_TOP) {0}
|
||||
set ::env(SYNTH_LATCH_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v}
|
||||
set ::env(SYNTH_MAX_FANOUT) {10}
|
||||
set ::env(SYNTH_MIN_BUF_PORT) {sky130_fd_sc_hd__buf_2 A X}
|
||||
set ::env(SYNTH_MUX4_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v}
|
||||
set ::env(SYNTH_MUX_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v}
|
||||
set ::env(SYNTH_NO_FLAT) {0}
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) {1}
|
||||
set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
|
||||
set ::env(SYNTH_SHARE_RESOURCES) {1}
|
||||
set ::env(SYNTH_SIZING) {0}
|
||||
set ::env(SYNTH_STRATEGY) {AREA 0}
|
||||
set ::env(SYNTH_TIEHI_PORT) {sky130_fd_sc_hd__conb_1 HI}
|
||||
set ::env(SYNTH_TIELO_PORT) {sky130_fd_sc_hd__conb_1 LO}
|
||||
set ::env(SYNTH_TIMING_DERATE) {0.05}
|
||||
set ::env(TAKE_LAYOUT_SCROT) {0}
|
||||
set ::env(TAP_DECAP_INSERTION) {1}
|
||||
set ::env(TECH_LEF) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TECH_LEF_MAX) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef}
|
||||
set ::env(TECH_LEF_MIN) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef}
|
||||
set ::env(TECH_LEF_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TERMINAL_OUTPUT) {/dev/null}
|
||||
set ::env(TMP_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp}
|
||||
set ::env(TOP_MARGIN_MULT) {2}
|
||||
set ::env(TRACKS_INFO_FILE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info}
|
||||
set ::env(TRISTATE_BUFFER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v}
|
||||
set ::env(USE_ARC_ANTENNA_CHECK) {1}
|
||||
set ::env(USE_GPIO_PADS) {0}
|
||||
set ::env(VDD_PIN) {VPWR}
|
||||
set ::env(VERILOG_FILES) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/../../verilog/rtl/buff_flash_clkrst.v}
|
||||
set ::env(WIRE_RC_LAYER) {met1}
|
||||
set ::env(YOSYS_REWRITE_VERILOG) {0}
|
||||
set ::env(cts_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/cts}
|
||||
set ::env(cts_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/cts}
|
||||
set ::env(cts_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/cts}
|
||||
set ::env(cts_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/cts}
|
||||
set ::env(eco_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/eco}
|
||||
set ::env(eco_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/eco}
|
||||
set ::env(eco_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/eco}
|
||||
set ::env(eco_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/eco}
|
||||
set ::env(floorplan_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/floorplan}
|
||||
set ::env(floorplan_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/floorplan}
|
||||
set ::env(floorplan_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/floorplan}
|
||||
set ::env(floorplan_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/floorplan}
|
||||
set ::env(placement_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/placement}
|
||||
set ::env(placement_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/placement}
|
||||
set ::env(placement_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/placement}
|
||||
set ::env(placement_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/placement}
|
||||
set ::env(routing_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/routing}
|
||||
set ::env(routing_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/routing}
|
||||
set ::env(routing_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing}
|
||||
set ::env(routing_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/routing}
|
||||
set ::env(signoff_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/signoff}
|
||||
set ::env(signoff_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff}
|
||||
set ::env(signoff_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff}
|
||||
set ::env(signoff_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff}
|
||||
set ::env(synthesis_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/synthesis}
|
||||
set ::env(synthesis_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/synthesis}
|
||||
set ::env(synthesis_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/synthesis}
|
||||
set ::env(synthesis_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis}
|
||||
set ::env(SYNTH_MAX_TRAN) {0.75}
|
||||
set ::env(CURRENT_INDEX) 32
|
||||
set ::env(CURRENT_DEF) /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def
|
||||
set ::env(CURRENT_GUIDE) /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/routing/12-global.guide
|
||||
set ::env(CURRENT_NETLIST) /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.nl.v
|
||||
set ::env(CURRENT_POWERED_NETLIST) {0}
|
||||
set ::env(CURRENT_ODB) /home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.odb
|
||||
set ::env(PDK_ROOT) {/home/hosni/OL_LATEST/OpenLane/pdks}
|
||||
set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.p.def}
|
||||
set ::env(ANTENNA_VIOLATOR_LIST) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/32-antenna_violators.rpt}
|
||||
set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
|
||||
set ::env(BASIC_PREP_COMPLETE) {1}
|
||||
set ::env(BOTTOM_MARGIN_MULT) {2}
|
||||
set ::env(CARAVEL_ROOT) {}
|
||||
set ::env(CARRY_SELECT_ADDER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v}
|
||||
set ::env(CELLS_LEF) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELLS_LEF_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELL_CLK_PORT) {CLK}
|
||||
set ::env(CELL_PAD_EXCLUDE) {sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*}
|
||||
set ::env(CHECK_ASSIGN_STATEMENTS) {0}
|
||||
set ::env(CHECK_UNMAPPED_CELLS) {1}
|
||||
set ::env(CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
|
||||
set ::env(CLK_BUFFER_INPUT) {A}
|
||||
set ::env(CLK_BUFFER_OUTPUT) {X}
|
||||
set ::env(CLOCK_BUFFER_FANOUT) {16}
|
||||
set ::env(CLOCK_PERIOD) {8}
|
||||
set ::env(CLOCK_PORT) {}
|
||||
set ::env(CLOCK_TREE_SYNTH) {0}
|
||||
set ::env(CLOCK_WIRE_RC_LAYER) {met5}
|
||||
set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
|
||||
set ::env(CORE_AREA) {1.84 5.44 37.72 19.04}
|
||||
set ::env(CORE_HEIGHT) {13.6}
|
||||
set ::env(CORE_WIDTH) {35.88}
|
||||
set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2}
|
||||
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(CTS_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/placement/buff_flash_clkrst.def}
|
||||
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
|
||||
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
|
||||
set ::env(CTS_MAX_CAP) {1.53169}
|
||||
set ::env(CTS_REPORT_TIMING) {1}
|
||||
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
|
||||
set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
|
||||
set ::env(CTS_SQR_CAP) {0.258e-3}
|
||||
set ::env(CTS_SQR_RES) {0.125}
|
||||
set ::env(CTS_TARGET_SKEW) {200}
|
||||
set ::env(CTS_TECH_DIR) {N/A}
|
||||
set ::env(CTS_TOLERANCE) {100}
|
||||
set ::env(CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.p.def}
|
||||
set ::env(CURRENT_GDS) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.gds}
|
||||
set ::env(CURRENT_GUIDE) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/routing/12-global.guide}
|
||||
set ::env(CURRENT_INDEX) {32}
|
||||
set ::env(CURRENT_LIB) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.lib}
|
||||
set ::env(CURRENT_NETLIST) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.nl.v}
|
||||
set ::env(CURRENT_ODB) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.odb}
|
||||
set ::env(CURRENT_POWERED_NETLIST) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.pnl.v}
|
||||
set ::env(CURRENT_SDC) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/floorplan/3-initial_fp.sdc}
|
||||
set ::env(CURRENT_SDF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.sdf}
|
||||
set ::env(CURRENT_SPEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef}
|
||||
set ::env(CURRENT_STEP) {}
|
||||
set ::env(CVC_SCRIPTS_DIR) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/cvc}
|
||||
set ::env(DATA_WIRE_RC_LAYER) {met2}
|
||||
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
|
||||
set ::env(DEFAULT_MAX_TRAN) {0.75}
|
||||
set ::env(DEF_UNITS_PER_MICRON) {1000}
|
||||
set ::env(DESIGN_CONFIG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/config.tcl}
|
||||
set ::env(DESIGN_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst}
|
||||
set ::env(DESIGN_IS_CORE) {0}
|
||||
set ::env(DESIGN_NAME) {buff_flash_clkrst}
|
||||
set ::env(DETAILED_ROUTER) {tritonroute}
|
||||
set ::env(DIE_AREA) {0.0 0.0 40.0 25.0}
|
||||
set ::env(DIODE_CELL) {sky130_fd_sc_hd__diode_2}
|
||||
set ::env(DIODE_CELL_PIN) {DIODE}
|
||||
set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def}
|
||||
set ::env(DIODE_INSERTION_STRATEGY) {3}
|
||||
set ::env(DIODE_PADDING) {2}
|
||||
set ::env(DONT_USE_CELLS) {sky130_fd_sc_hd__a2111oi_0 sky130_fd_sc_hd__a21boi_0 sky130_fd_sc_hd__and2_0 sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__clkdlybuf4s15_1 sky130_fd_sc_hd__clkdlybuf4s18_1 sky130_fd_sc_hd__fa_4 sky130_fd_sc_hd__lpflow_bleeder_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_16 sky130_fd_sc_hd__lpflow_clkbufkapwr_2 sky130_fd_sc_hd__lpflow_clkbufkapwr_4 sky130_fd_sc_hd__lpflow_clkbufkapwr_8 sky130_fd_sc_hd__lpflow_clkinvkapwr_1 sky130_fd_sc_hd__lpflow_clkinvkapwr_16 sky130_fd_sc_hd__lpflow_clkinvkapwr_2 sky130_fd_sc_hd__lpflow_clkinvkapwr_4 sky130_fd_sc_hd__lpflow_clkinvkapwr_8 sky130_fd_sc_hd__lpflow_decapkapwr_12 sky130_fd_sc_hd__lpflow_decapkapwr_3 sky130_fd_sc_hd__lpflow_decapkapwr_4 sky130_fd_sc_hd__lpflow_decapkapwr_6 sky130_fd_sc_hd__lpflow_decapkapwr_8 sky130_fd_sc_hd__lpflow_inputiso0n_1 sky130_fd_sc_hd__lpflow_inputiso0p_1 sky130_fd_sc_hd__lpflow_inputiso1n_1 sky130_fd_sc_hd__lpflow_inputiso1p_1 sky130_fd_sc_hd__lpflow_inputisolatch_1 sky130_fd_sc_hd__lpflow_isobufsrc_1 sky130_fd_sc_hd__lpflow_isobufsrc_16 sky130_fd_sc_hd__lpflow_isobufsrc_2 sky130_fd_sc_hd__lpflow_isobufsrc_4 sky130_fd_sc_hd__lpflow_isobufsrc_8 sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 sky130_fd_sc_hd__mux4_4 sky130_fd_sc_hd__o21ai_0 sky130_fd_sc_hd__o311ai_0 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__probe_p_8 sky130_fd_sc_hd__probec_p_8 sky130_fd_sc_hd__xor3_1 sky130_fd_sc_hd__xor3_2 sky130_fd_sc_hd__xor3_4 sky130_fd_sc_hd__xnor3_1 sky130_fd_sc_hd__xnor3_2 sky130_fd_sc_hd__xnor3_4 sky130_fd_sc_hd__clkbuf_1 sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_12 sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkdlybuf4s15_1 sky130_fd_sc_hd__clkdlybuf4s15_2 sky130_fd_sc_hd__clkdlybuf4s18_1 sky130_fd_sc_hd__clkdlybuf4s18_2 sky130_fd_sc_hd__clkdlybuf4s25_1 sky130_fd_sc_hd__clkdlybuf4s25_2 sky130_fd_sc_hd__clkdlybuf4s50_1 sky130_fd_sc_hd__clkdlybuf4s50_2 sky130_fd_sc_hd__dlygate4sd1_1 sky130_fd_sc_hd__dlygate4sd2_1 sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__dlymetal6s2s_1 sky130_fd_sc_hd__dlymetal6s4s_1 sky130_fd_sc_hd__dlymetal6s6s_1 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_12 sky130_fd_sc_hd__decap_3 sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_3 sky130_fd_sc_hd__decap_6 }
|
||||
set ::env(DPL_CELL_PADDING) {4}
|
||||
set ::env(DRC_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff/27-buff_flash_clkrst.p.def}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/drc_exclude.list}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
|
||||
set ::env(DRT_OPT_ITERS) {64}
|
||||
set ::env(ECO_ENABLE) {0}
|
||||
set ::env(ECO_FINISH) {0}
|
||||
set ::env(ECO_ITER) {0}
|
||||
set ::env(ECO_SKIP_PIN) {1}
|
||||
set ::env(EXT_NETLIST) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.gds.spice}
|
||||
set ::env(FAKEDIODE_CELL) {sky130_ef_sc_hd__fakediode_2}
|
||||
set ::env(FILL_CELL) {sky130_fd_sc_hd__fill*}
|
||||
set ::env(FILL_INSERTION) {1}
|
||||
set ::env(FP_ASPECT_RATIO) {1}
|
||||
set ::env(FP_CORE_UTIL) {50}
|
||||
set ::env(FP_ENDCAP_CELL) {sky130_fd_sc_hd__decap_3}
|
||||
set ::env(FP_IO_HEXTEND) {-1}
|
||||
set ::env(FP_IO_HLAYER) {met3}
|
||||
set ::env(FP_IO_HLENGTH) {4}
|
||||
set ::env(FP_IO_HTHICKNESS_MULT) {2}
|
||||
set ::env(FP_IO_MIN_DISTANCE) {3}
|
||||
set ::env(FP_IO_MODE) {1}
|
||||
set ::env(FP_IO_UNMATCHED_ERROR) {1}
|
||||
set ::env(FP_IO_VEXTEND) {-1}
|
||||
set ::env(FP_IO_VLAYER) {met2}
|
||||
set ::env(FP_IO_VLENGTH) {4}
|
||||
set ::env(FP_IO_VTHICKNESS_MULT) {2}
|
||||
set ::env(FP_PDN_AUTO_ADJUST) {1}
|
||||
set ::env(FP_PDN_CHECK_NODES) {1}
|
||||
set ::env(FP_PDN_CORE_RING) {0}
|
||||
set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
|
||||
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
|
||||
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
|
||||
set ::env(FP_PDN_ENABLE_RAILS) {1}
|
||||
set ::env(FP_PDN_HOFFSET) {1.695}
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_PDN_HPITCH) {3.395}
|
||||
set ::env(FP_PDN_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_IRDROP) {1}
|
||||
set ::env(FP_PDN_LOWER_LAYER) {met4}
|
||||
set ::env(FP_PDN_RAILS_LAYER) {met1}
|
||||
set ::env(FP_PDN_RAIL_OFFSET) {0}
|
||||
set ::env(FP_PDN_RAIL_WIDTH) {0.48}
|
||||
set ::env(FP_PDN_SKIPTRIM) {0}
|
||||
set ::env(FP_PDN_UPPER_LAYER) {met5}
|
||||
set ::env(FP_PDN_VERTICAL_HALO) {10}
|
||||
set ::env(FP_PDN_VOFFSET) {4.480}
|
||||
set ::env(FP_PDN_VPITCH) {8.965}
|
||||
set ::env(FP_PDN_VSPACING) {2}
|
||||
set ::env(FP_PDN_VWIDTH) {1.6}
|
||||
set ::env(FP_PIN_ORDER_CFG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/pin_order.cfg}
|
||||
set ::env(FP_SIZING) {absolute}
|
||||
set ::env(FP_TAPCELL_DIST) {13}
|
||||
set ::env(FP_TAP_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_TAP_VERTICAL_HALO) {10}
|
||||
set ::env(FP_WELLTAP_CELL) {sky130_fd_sc_hd__tapvpwrvgnd_1}
|
||||
set ::env(FULL_ADDER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v}
|
||||
set ::env(GDS_FILES) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GDS_FILES_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
|
||||
set ::env(GLB_CFG_FILE) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/config.tcl}
|
||||
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
|
||||
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(GLOBAL_ROUTER) {fastroute}
|
||||
set ::env(GND_NET) {VGND}
|
||||
set ::env(GND_NETS) {VGND}
|
||||
set ::env(GND_PIN) {VGND}
|
||||
set ::env(GPIO_PADS_LEF) { /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef }
|
||||
set ::env(GPIO_PADS_LEF_CORE_SIDE) { /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef }
|
||||
set ::env(GPIO_PADS_VERILOG) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/verilog/sky130_fd_io/sky130_ef_io.v}
|
||||
set ::env(GPL_CELL_PADDING) {0}
|
||||
set ::env(GRT_ADJUSTMENT) {0.3}
|
||||
set ::env(GRT_ALLOW_CONGESTION) {0}
|
||||
set ::env(GRT_ANT_ITERS) {3}
|
||||
set ::env(GRT_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(GRT_LAYER_ADJUSTMENTS) {0.99,0,0,0,0,0}
|
||||
set ::env(GRT_MACRO_EXTENSION) {0}
|
||||
set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
|
||||
set ::env(GRT_OVERFLOW_ITERS) {50}
|
||||
set ::env(HOME) {/}
|
||||
set ::env(HOSTNAME) {06e0f21373be}
|
||||
set ::env(IO_PCT) {0.2}
|
||||
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
|
||||
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/drc/sky130A_mr.drc}
|
||||
set ::env(KLAYOUT_PROPERTIES) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp}
|
||||
set ::env(KLAYOUT_TECH) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt}
|
||||
set ::env(KLAYOUT_XOR_GDS) {1}
|
||||
set ::env(KLAYOUT_XOR_XML) {1}
|
||||
set ::env(LANG) {en_US.UTF-8}
|
||||
set ::env(LAST_TIMING_REPORT_TAG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/22-rcx_sta}
|
||||
set ::env(LC_ALL) {en_US.UTF-8}
|
||||
set ::env(LC_CTYPE) {en_US.UTF-8}
|
||||
set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
|
||||
set ::env(LEC_ENABLE) {0}
|
||||
set ::env(LEFT_MARGIN_MULT) {4}
|
||||
set ::env(LIB_CTS) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/cts/cts.lib}
|
||||
set ::env(LIB_FASTEST) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib}
|
||||
set ::env(LIB_SLOWEST) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SLOWEST_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SYNTH) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis/trimmed.lib}
|
||||
set ::env(LIB_SYNTH_COMPLETE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis/1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib}
|
||||
set ::env(LIB_SYNTH_MERGED) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis/merged.lib}
|
||||
set ::env(LIB_SYNTH_NO_PG) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis/1-trimmed.no_pg.lib}
|
||||
set ::env(LIB_TYPICAL) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LOGS_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs}
|
||||
set ::env(LVS_CONNECT_BY_LABEL) {0}
|
||||
set ::env(LVS_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def}
|
||||
set ::env(LVS_INSERT_POWER_PINS) {1}
|
||||
set ::env(MACRO_BLOCKAGES_LAYER) {li1 met1 met2 met3 met4}
|
||||
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
|
||||
set ::env(MAGIC_DEF_LABELS) {1}
|
||||
set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
|
||||
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
|
||||
set ::env(MAGIC_DRC_USE_GDS) {1}
|
||||
set ::env(MAGIC_EXT_USE_GDS) {1}
|
||||
set ::env(MAGIC_GDS) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff/buff_flash_clkrst.magic.gds}
|
||||
set ::env(MAGIC_GENERATE_GDS) {1}
|
||||
set ::env(MAGIC_GENERATE_LEF) {1}
|
||||
set ::env(MAGIC_GENERATE_MAGLEF) {1}
|
||||
set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
|
||||
set ::env(MAGIC_MAGICRC) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc}
|
||||
set ::env(MAGIC_PAD) {0}
|
||||
set ::env(MAGIC_TECH_FILE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech}
|
||||
set ::env(MAGIC_WRITE_FULL_LEF) {0}
|
||||
set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
|
||||
set ::env(MAGTYPE) {maglef}
|
||||
set ::env(MANPATH) {/build//share/man:}
|
||||
set ::env(MAX_METAL_LAYER) {6}
|
||||
set ::env(MC_SDF_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/sdf}
|
||||
set ::env(MC_SPEF_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/mca/spef}
|
||||
set ::env(MERGED_LEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.nom.lef}
|
||||
set ::env(MERGED_LEF_MAX) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.max.lef}
|
||||
set ::env(MERGED_LEF_MIN) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/merged.min.lef}
|
||||
set ::env(MISMATCHES_OK) {1}
|
||||
set ::env(NETGEN_SETUP_FILE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl}
|
||||
set ::env(NO_SYNTH_CELL_LIST) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells}
|
||||
set ::env(OPENLANE_MOUNTED_SCRIPTS_VERSION) {32da932761213af689f10088d671e1e3dc38f273}
|
||||
set ::env(OPENLANE_ROOT) {/openlane}
|
||||
set ::env(OPENLANE_RUN_TAG) {22_10_15_06_27}
|
||||
set ::env(OPENLANE_VERBOSE) {1}
|
||||
set ::env(OPENLANE_VERSION) {e3a5189a1b0fc4290686fcf2ae46cd6d7947cf9f}
|
||||
set ::env(OPENROAD) {/build/}
|
||||
set ::env(OPENROAD_BIN) {openroad}
|
||||
set ::env(PARSITICS_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing/buff_flash_clkrst.def}
|
||||
set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
|
||||
set ::env(PDK) {sky130A}
|
||||
set ::env(PDKPATH) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A}
|
||||
set ::env(PDK_ROOT) {/home/hosni/OL_LATEST/OpenLane/pdks}
|
||||
set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
|
||||
set ::env(PLACEMENT_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/floorplan/6-pdn.def}
|
||||
set ::env(PLACE_SITE) {unithd}
|
||||
set ::env(PLACE_SITE_HEIGHT) {2.720}
|
||||
set ::env(PLACE_SITE_WIDTH) {0.460}
|
||||
set ::env(PL_BASIC_PLACEMENT) {0}
|
||||
set ::env(PL_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(PL_INIT_COEFF) {0.00002}
|
||||
set ::env(PL_IO_ITER) {5}
|
||||
set ::env(PL_LIB) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(PL_MACRO_CHANNEL) {0 0}
|
||||
set ::env(PL_MACRO_HALO) {0 0}
|
||||
set ::env(PL_MAX_DISPLACEMENT_X) {500}
|
||||
set ::env(PL_MAX_DISPLACEMENT_Y) {100}
|
||||
set ::env(PL_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
|
||||
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
|
||||
set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
|
||||
set ::env(PL_RESIZER_TIE_SEPERATION) {0}
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_ROUTABILITY_DRIVEN) {1}
|
||||
set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_TARGET_DENSITY) {0.96}
|
||||
set ::env(PL_TIME_DRIVEN) {1}
|
||||
set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
|
||||
set ::env(PROCESS) {130}
|
||||
set ::env(PWD) {/home/hosni/My_forks/marwan/caravel/openlane}
|
||||
set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
|
||||
set ::env(QUIT_ON_LVS_ERROR) {1}
|
||||
set ::env(QUIT_ON_MAGIC_DRC) {1}
|
||||
set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TR_DRC) {1}
|
||||
set ::env(RCX_CC_MODEL) {10}
|
||||
set ::env(RCX_CONTEXT_DEPTH) {5}
|
||||
set ::env(RCX_CORNER_COUNT) {1}
|
||||
set ::env(RCX_COUPLING_THRESHOLD) {0.1}
|
||||
set ::env(RCX_MAX_RESISTANCE) {50}
|
||||
set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
|
||||
set ::env(RCX_RULES) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre}
|
||||
set ::env(RCX_RULES_MAX) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre}
|
||||
set ::env(RCX_RULES_MIN) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre}
|
||||
set ::env(RCX_SDC_FILE) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/floorplan/3-initial_fp.sdc}
|
||||
set ::env(REPORTS_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports}
|
||||
set ::env(RESULTS_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results}
|
||||
set ::env(RE_BUFFER_CELL) {sky130_fd_sc_hd__buf_4}
|
||||
set ::env(RIGHT_MARGIN_MULT) {4}
|
||||
set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v}
|
||||
set ::env(ROOT_CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(ROUTING_CORES) {2}
|
||||
set ::env(ROUTING_CURRENT_DEF) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/placement/buff_flash_clkrst.def}
|
||||
set ::env(RSZ_DONT_TOUCH_RX) {\$^}
|
||||
set ::env(RSZ_LIB) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis/resizer_sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(RSZ_USE_OLD_REMOVER) {0}
|
||||
set ::env(RT_MAX_LAYER) {met5}
|
||||
set ::env(RT_MIN_LAYER) {met1}
|
||||
set ::env(RUN_CVC) {1}
|
||||
set ::env(RUN_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27}
|
||||
set ::env(RUN_DRT) {1}
|
||||
set ::env(RUN_IRDROP_REPORT) {1}
|
||||
set ::env(RUN_KLAYOUT) {1}
|
||||
set ::env(RUN_KLAYOUT_DRC) {0}
|
||||
set ::env(RUN_KLAYOUT_XOR) {1}
|
||||
set ::env(RUN_LVS) {1}
|
||||
set ::env(RUN_MAGIC) {1}
|
||||
set ::env(RUN_MAGIC_DRC) {1}
|
||||
set ::env(RUN_SPEF_EXTRACTION) {1}
|
||||
set ::env(RUN_STANDALONE) {1}
|
||||
set ::env(RUN_TAG) {22_10_15_06_27}
|
||||
set ::env(SCRIPTS_DIR) {/openlane/scripts}
|
||||
set ::env(SHLVL) {1}
|
||||
set ::env(SPEF_EXTRACTOR) {openrcx}
|
||||
set ::env(START_TIME) {2022.10.15_13.27.23}
|
||||
set ::env(STA_PRE_CTS) {0}
|
||||
set ::env(STA_REPORT_POWER) {1}
|
||||
set ::env(STA_WRITE_LIB) {1}
|
||||
set ::env(STD_CELL_GROUND_PINS) {VGND VNB}
|
||||
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_CDL) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_LIBRARY_OPT) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_OPT_CDL) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_POWER_PINS) {VPWR VPB}
|
||||
set ::env(SYNTH_ADDER_TYPE) {YOSYS}
|
||||
set ::env(SYNTH_BIN) {yosys}
|
||||
set ::env(SYNTH_BUFFERING) {0}
|
||||
set ::env(SYNTH_CAP_LOAD) {33.442}
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
|
||||
set ::env(SYNTH_DRIVING_CELL) {sky130_fd_sc_hd__inv_2}
|
||||
set ::env(SYNTH_DRIVING_CELL_PIN) {Y}
|
||||
set ::env(SYNTH_ELABORATE_ONLY) {0}
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
|
||||
set ::env(SYNTH_FLAT_TOP) {0}
|
||||
set ::env(SYNTH_LATCH_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v}
|
||||
set ::env(SYNTH_MAX_FANOUT) {10}
|
||||
set ::env(SYNTH_MAX_TRAN) {0.75}
|
||||
set ::env(SYNTH_MIN_BUF_PORT) {sky130_fd_sc_hd__buf_2 A X}
|
||||
set ::env(SYNTH_MUX4_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v}
|
||||
set ::env(SYNTH_MUX_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v}
|
||||
set ::env(SYNTH_NO_FLAT) {0}
|
||||
set ::env(SYNTH_OPT) {0}
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) {1}
|
||||
set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
|
||||
set ::env(SYNTH_SHARE_RESOURCES) {1}
|
||||
set ::env(SYNTH_SIZING) {0}
|
||||
set ::env(SYNTH_STRATEGY) {AREA 0}
|
||||
set ::env(SYNTH_TIEHI_PORT) {sky130_fd_sc_hd__conb_1 HI}
|
||||
set ::env(SYNTH_TIELO_PORT) {sky130_fd_sc_hd__conb_1 LO}
|
||||
set ::env(SYNTH_TIMING_DERATE) {0.05}
|
||||
set ::env(TAKE_LAYOUT_SCROT) {0}
|
||||
set ::env(TAP_DECAP_INSERTION) {1}
|
||||
set ::env(TECH_LEF) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TECH_LEF_MAX) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef}
|
||||
set ::env(TECH_LEF_MIN) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef}
|
||||
set ::env(TECH_LEF_OPT) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TECH_METAL_LAYERS) {li1 met1 met2 met3 met4 met5}
|
||||
set ::env(TERM) {xterm}
|
||||
set ::env(TERMINAL_OUTPUT) {/dev/null}
|
||||
set ::env(TMP_DIR) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp}
|
||||
set ::env(TOP_MARGIN_MULT) {2}
|
||||
set ::env(TRACKS_INFO_FILE) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info}
|
||||
set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/routing/config.tracks}
|
||||
set ::env(TRISTATE_BUFFER_MAP) {/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v}
|
||||
set ::env(USE_ARC_ANTENNA_CHECK) {1}
|
||||
set ::env(USE_GPIO_PADS) {0}
|
||||
set ::env(VCHECK_OUTPUT) {}
|
||||
set ::env(VDD_NET) {VPWR}
|
||||
set ::env(VDD_NETS) {VPWR}
|
||||
set ::env(VDD_PIN) {VPWR}
|
||||
set ::env(VERILOG_FILES) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/../../verilog/rtl/buff_flash_clkrst.v}
|
||||
set ::env(WIRE_RC_LAYER) {met1}
|
||||
set ::env(YOSYS_REWRITE_VERILOG) {0}
|
||||
set ::env(_) {/openlane/flow.tcl}
|
||||
set ::env(cts_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/cts}
|
||||
set ::env(cts_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/cts}
|
||||
set ::env(cts_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/cts}
|
||||
set ::env(cts_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/cts}
|
||||
set ::env(drc_prefix) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff/drc}
|
||||
set ::env(eco_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/eco}
|
||||
set ::env(eco_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/eco}
|
||||
set ::env(eco_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/eco}
|
||||
set ::env(eco_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/eco}
|
||||
set ::env(floorplan_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/floorplan}
|
||||
set ::env(floorplan_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/floorplan}
|
||||
set ::env(floorplan_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/floorplan}
|
||||
set ::env(floorplan_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/floorplan}
|
||||
set ::env(fp_report_prefix) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/floorplan/3-initial_fp}
|
||||
set ::env(placement_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/placement}
|
||||
set ::env(placement_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/placement}
|
||||
set ::env(placement_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/placement}
|
||||
set ::env(placement_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/placement}
|
||||
set ::env(routing_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/routing}
|
||||
set ::env(routing_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/routing}
|
||||
set ::env(routing_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/routing}
|
||||
set ::env(routing_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/routing}
|
||||
set ::env(signoff_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/signoff}
|
||||
set ::env(signoff_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/signoff}
|
||||
set ::env(signoff_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/signoff}
|
||||
set ::env(signoff_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/signoff}
|
||||
set ::env(synth_report_prefix) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/synthesis/1-synthesis}
|
||||
set ::env(synthesis_logs) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/logs/synthesis}
|
||||
set ::env(synthesis_reports) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/reports/synthesis}
|
||||
set ::env(synthesis_results) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/results/synthesis}
|
||||
set ::env(synthesis_tmpfiles) {/home/hosni/My_forks/marwan/caravel/openlane/buff_flash_clkrst/runs/22_10_15_06_27/tmp/synthesis}
|
||||
set ::env(timer_end) {1665840472}
|
||||
set ::env(timer_routed) {1665840456}
|
||||
set ::env(timer_start) {1665840443}
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "buff_flash_clkrst")
|
||||
(DATE "Thu Oct 13 17:29:04 2022")
|
||||
(DATE "Sat Oct 15 13:27:41 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
|
@ -15,36 +15,51 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT in_n[0] BUF\[3\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[10] BUF\[13\].A (0.012:0.012:0.012) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[11] BUF\[14\].A (0.019:0.019:0.019) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_n[1] BUF\[4\].A (0.015:0.015:0.015) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_n[2] BUF\[5\].A (0.017:0.017:0.017) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_n[3] BUF\[6\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[4] BUF\[7\].A (0.015:0.015:0.015) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[5] BUF\[8\].A (0.014:0.014:0.014) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[6] BUF\[9\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_n[7] BUF\[10\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_n[8] BUF\[11\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[9] BUF\[12\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_s[0] BUF\[0\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_s[1] BUF\[1\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_s[2] BUF\[2\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
|
||||
(INTERCONNECT BUF\[0\].X out_n[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[10\].X out_s[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[11\].X out_s[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_s[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[14\].X out_s[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[1\].X out_n[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[2\].X out_n[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[3\].X out_s[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[4\].X out_s[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[5\].X out_s[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[6\].X out_s[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[7\].X out_s[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[8\].X out_s[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[9\].X out_s[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT in_e[0] BUF\[3\].A (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[0] ANTENNA_BUF\[3\]_A.DIODE (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[10] BUF\[13\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[10] ANTENNA_BUF\[13\]_A.DIODE (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[11] BUF\[14\].A (0.028:0.028:0.028) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[11] ANTENNA_BUF\[14\]_A.DIODE (0.028:0.028:0.028) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[1] BUF\[4\].A (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[1] ANTENNA_BUF\[4\]_A.DIODE (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[2] BUF\[5\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[2] ANTENNA_BUF\[5\]_A.DIODE (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[3] BUF\[6\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[3] ANTENNA_BUF\[6\]_A.DIODE (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[4] BUF\[7\].A (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[4] ANTENNA_BUF\[7\]_A.DIODE (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[5] BUF\[8\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[5] ANTENNA_BUF\[8\]_A.DIODE (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[6] BUF\[9\].A (0.020:0.020:0.020) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_e[6] ANTENNA_BUF\[9\]_A.DIODE (0.020:0.020:0.020) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_e[7] BUF\[10\].A (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[7] ANTENNA_BUF\[10\]_A.DIODE (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[8] BUF\[11\].A (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[8] ANTENNA_BUF\[11\]_A.DIODE (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_e[9] BUF\[12\].A (0.025:0.025:0.025) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_e[9] ANTENNA_BUF\[12\]_A.DIODE (0.025:0.025:0.025) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_w[0] BUF\[0\].A (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_w[0] ANTENNA_BUF\[0\]_A.DIODE (0.018:0.018:0.018) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_w[1] BUF\[1\].A (0.021:0.021:0.021) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_w[1] ANTENNA_BUF\[1\]_A.DIODE (0.021:0.021:0.021) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_w[2] BUF\[2\].A (0.017:0.017:0.017) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_w[2] ANTENNA_BUF\[2\]_A.DIODE (0.017:0.017:0.017) (0.005:0.005:0.005))
|
||||
(INTERCONNECT BUF\[0\].X out_e[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[10\].X out_w[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[11\].X out_w[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[12\].X out_w[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_w[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[14\].X out_w[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[1\].X out_e[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[2\].X out_e[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[3\].X out_w[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[4\].X out_w[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[5\].X out_w[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[6\].X out_w[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[7\].X out_w[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[8\].X out_w[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[9\].X out_w[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
(INSTANCE BUF\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.102:0.102:0.102) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -62,7 +77,7 @@
|
|||
(INSTANCE BUF\[10\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.101:0.101:0.101) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -71,7 +86,7 @@
|
|||
(INSTANCE BUF\[11\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.101:0.101:0.101) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
(INSTANCE BUF\[12\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.103:0.103:0.103) (0.100:0.100:0.100))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
(INSTANCE BUF\[13\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.101:0.101:0.101) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
(INSTANCE BUF\[14\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.102:0.102:0.102) (0.099:0.099:0.099))
|
||||
(IOPATH A X (0.105:0.105:0.105) (0.101:0.101:0.101))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
(INSTANCE BUF\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.101:0.101:0.101) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
(INSTANCE BUF\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
(INSTANCE BUF\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.101:0.101:0.101) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
(INSTANCE BUF\[6\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
(INSTANCE BUF\[7\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
(INSTANCE BUF\[8\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
(INSTANCE BUF\[9\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.102:0.102:0.102) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "buff_flash_clkrst")
|
||||
(DATE "Thu Oct 13 17:29:04 2022")
|
||||
(DATE "Sat Oct 15 13:27:41 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
|
@ -15,36 +15,51 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT in_n[0] BUF\[3\].A (0.027:0.027:0.027) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_n[10] BUF\[13\].A (0.026:0.026:0.026) (0.014:0.014:0.014))
|
||||
(INTERCONNECT in_n[11] BUF\[14\].A (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_n[1] BUF\[4\].A (0.031:0.031:0.031) (0.017:0.017:0.017))
|
||||
(INTERCONNECT in_n[2] BUF\[5\].A (0.035:0.035:0.035) (0.019:0.019:0.019))
|
||||
(INTERCONNECT in_n[3] BUF\[6\].A (0.027:0.027:0.027) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_n[4] BUF\[7\].A (0.031:0.031:0.031) (0.017:0.017:0.017))
|
||||
(INTERCONNECT in_n[5] BUF\[8\].A (0.029:0.029:0.029) (0.016:0.016:0.016))
|
||||
(INTERCONNECT in_n[6] BUF\[9\].A (0.033:0.033:0.033) (0.018:0.018:0.018))
|
||||
(INTERCONNECT in_n[7] BUF\[10\].A (0.034:0.034:0.034) (0.019:0.019:0.019))
|
||||
(INTERCONNECT in_n[8] BUF\[11\].A (0.028:0.028:0.028) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_n[9] BUF\[12\].A (0.034:0.034:0.034) (0.019:0.019:0.019))
|
||||
(INTERCONNECT in_s[0] BUF\[0\].A (0.026:0.026:0.026) (0.014:0.014:0.014))
|
||||
(INTERCONNECT in_s[1] BUF\[1\].A (0.034:0.034:0.034) (0.019:0.019:0.019))
|
||||
(INTERCONNECT in_s[2] BUF\[2\].A (0.027:0.027:0.027) (0.015:0.015:0.015))
|
||||
(INTERCONNECT BUF\[0\].X out_n[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[10\].X out_s[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[11\].X out_s[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_s[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[14\].X out_s[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[1\].X out_n[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[2\].X out_n[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[3\].X out_s[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[4\].X out_s[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[5\].X out_s[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[6\].X out_s[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[7\].X out_s[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[8\].X out_s[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[9\].X out_s[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT in_e[0] BUF\[3\].A (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[0] ANTENNA_BUF\[3\]_A.DIODE (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[10] BUF\[13\].A (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[10] ANTENNA_BUF\[13\]_A.DIODE (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[11] BUF\[14\].A (0.058:0.058:0.058) (0.034:0.034:0.034))
|
||||
(INTERCONNECT in_e[11] ANTENNA_BUF\[14\]_A.DIODE (0.058:0.058:0.058) (0.034:0.034:0.034))
|
||||
(INTERCONNECT in_e[1] BUF\[4\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[1] ANTENNA_BUF\[4\]_A.DIODE (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[2] BUF\[5\].A (0.037:0.037:0.037) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[2] ANTENNA_BUF\[5\]_A.DIODE (0.037:0.037:0.037) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[3] BUF\[6\].A (0.037:0.037:0.037) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[3] ANTENNA_BUF\[6\]_A.DIODE (0.037:0.037:0.037) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[4] BUF\[7\].A (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[4] ANTENNA_BUF\[7\]_A.DIODE (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[5] BUF\[8\].A (0.037:0.037:0.037) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[5] ANTENNA_BUF\[8\]_A.DIODE (0.037:0.037:0.037) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[6] BUF\[9\].A (0.042:0.042:0.042) (0.024:0.024:0.024))
|
||||
(INTERCONNECT in_e[6] ANTENNA_BUF\[9\]_A.DIODE (0.042:0.042:0.042) (0.024:0.024:0.024))
|
||||
(INTERCONNECT in_e[7] BUF\[10\].A (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[7] ANTENNA_BUF\[10\]_A.DIODE (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[8] BUF\[11\].A (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[8] ANTENNA_BUF\[11\]_A.DIODE (0.039:0.039:0.039) (0.022:0.022:0.022))
|
||||
(INTERCONNECT in_e[9] BUF\[12\].A (0.053:0.053:0.053) (0.030:0.030:0.030))
|
||||
(INTERCONNECT in_e[9] ANTENNA_BUF\[12\]_A.DIODE (0.053:0.053:0.053) (0.030:0.030:0.030))
|
||||
(INTERCONNECT in_w[0] BUF\[0\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_w[0] ANTENNA_BUF\[0\]_A.DIODE (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_w[1] BUF\[1\].A (0.046:0.046:0.046) (0.026:0.026:0.026))
|
||||
(INTERCONNECT in_w[1] ANTENNA_BUF\[1\]_A.DIODE (0.046:0.046:0.046) (0.026:0.026:0.026))
|
||||
(INTERCONNECT in_w[2] BUF\[2\].A (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_w[2] ANTENNA_BUF\[2\]_A.DIODE (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT BUF\[0\].X out_e[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[10\].X out_w[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[11\].X out_w[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[12\].X out_w[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_w[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[14\].X out_w[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[1\].X out_e[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[2\].X out_e[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[3\].X out_w[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[4\].X out_w[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[5\].X out_w[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[6\].X out_w[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[7\].X out_w[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[8\].X out_w[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[9\].X out_w[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
(INSTANCE BUF\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.259:0.259:0.259) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.267:0.267:0.267) (0.268:0.268:0.268))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -62,7 +77,7 @@
|
|||
(INSTANCE BUF\[10\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.261:0.261:0.261) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.265:0.265:0.265) (0.267:0.267:0.267))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -71,7 +86,7 @@
|
|||
(INSTANCE BUF\[11\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.265:0.265:0.265) (0.267:0.267:0.267))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
(INSTANCE BUF\[12\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.260:0.260:0.260) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.271:0.271:0.271) (0.271:0.271:0.271))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
(INSTANCE BUF\[13\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
(INSTANCE BUF\[14\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.267:0.267:0.267) (0.268:0.268:0.268))
|
||||
(IOPATH A X (0.277:0.277:0.277) (0.274:0.274:0.274))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
(INSTANCE BUF\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.260:0.260:0.260) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.267:0.267:0.267) (0.268:0.268:0.268))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
(INSTANCE BUF\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
(INSTANCE BUF\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.257:0.257:0.257) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.259:0.259:0.259) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -143,7 +158,7 @@
|
|||
(INSTANCE BUF\[5\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.261:0.261:0.261) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
(INSTANCE BUF\[6\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.257:0.257:0.257) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.263:0.263:0.263) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
(INSTANCE BUF\[7\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.263:0.263:0.263) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
(INSTANCE BUF\[8\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
(INSTANCE BUF\[9\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
(IOPATH A X (0.267:0.267:0.267) (0.268:0.268:0.268))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "buff_flash_clkrst")
|
||||
(DATE "Thu Oct 13 17:29:04 2022")
|
||||
(DATE "Sat Oct 15 13:27:41 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
|
@ -15,36 +15,51 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT in_n[0] BUF\[3\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[10] BUF\[13\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[11] BUF\[14\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_n[1] BUF\[4\].A (0.020:0.020:0.020) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_n[2] BUF\[5\].A (0.022:0.022:0.022) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_n[3] BUF\[6\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[4] BUF\[7\].A (0.020:0.020:0.020) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_n[5] BUF\[8\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_n[6] BUF\[9\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_n[7] BUF\[10\].A (0.022:0.022:0.022) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_n[8] BUF\[11\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[9] BUF\[12\].A (0.022:0.022:0.022) (0.009:0.009:0.009))
|
||||
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||||
(INTERCONNECT in_s[1] BUF\[1\].A (0.022:0.022:0.022) (0.010:0.010:0.010))
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||||
(INTERCONNECT in_s[2] BUF\[2\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
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||||
(INTERCONNECT BUF\[0\].X out_n[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[10\].X out_s[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[11\].X out_s[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_s[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[14\].X out_s[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[1\].X out_n[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[2\].X out_n[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[3\].X out_s[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[4\].X out_s[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[5\].X out_s[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[6\].X out_s[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[7\].X out_s[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[8\].X out_s[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[9\].X out_s[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT in_e[0] BUF\[3\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[0] ANTENNA_BUF\[3\]_A.DIODE (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[10] BUF\[13\].A (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[10] ANTENNA_BUF\[13\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[11] BUF\[14\].A (0.038:0.038:0.038) (0.017:0.017:0.017))
|
||||
(INTERCONNECT in_e[11] ANTENNA_BUF\[14\]_A.DIODE (0.038:0.038:0.038) (0.017:0.017:0.017))
|
||||
(INTERCONNECT in_e[1] BUF\[4\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[1] ANTENNA_BUF\[4\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[2] BUF\[5\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[2] ANTENNA_BUF\[5\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[3] BUF\[6\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[3] ANTENNA_BUF\[6\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[4] BUF\[7\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[4] ANTENNA_BUF\[7\]_A.DIODE (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[5] BUF\[8\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[5] ANTENNA_BUF\[8\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[6] BUF\[9\].A (0.027:0.027:0.027) (0.012:0.012:0.012))
|
||||
(INTERCONNECT in_e[6] ANTENNA_BUF\[9\]_A.DIODE (0.027:0.027:0.027) (0.012:0.012:0.012))
|
||||
(INTERCONNECT in_e[7] BUF\[10\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[7] ANTENNA_BUF\[10\]_A.DIODE (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[8] BUF\[11\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[8] ANTENNA_BUF\[11\]_A.DIODE (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[9] BUF\[12\].A (0.034:0.034:0.034) (0.016:0.016:0.016))
|
||||
(INTERCONNECT in_e[9] ANTENNA_BUF\[12\]_A.DIODE (0.034:0.034:0.034) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_w[0] BUF\[0\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_w[0] ANTENNA_BUF\[0\]_A.DIODE (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_w[1] BUF\[1\].A (0.029:0.029:0.029) (0.013:0.013:0.013))
|
||||
(INTERCONNECT in_w[1] ANTENNA_BUF\[1\]_A.DIODE (0.029:0.029:0.029) (0.013:0.013:0.013))
|
||||
(INTERCONNECT in_w[2] BUF\[2\].A (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_w[2] ANTENNA_BUF\[2\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT BUF\[0\].X out_e[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[10\].X out_w[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[11\].X out_w[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[12\].X out_w[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_w[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[14\].X out_w[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[1\].X out_e[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[2\].X out_e[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[3\].X out_w[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[4\].X out_w[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[5\].X out_w[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[6\].X out_w[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[7\].X out_w[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[8\].X out_w[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
(INTERCONNECT BUF\[9\].X out_w[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
(INSTANCE BUF\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -62,7 +77,7 @@
|
|||
(INSTANCE BUF\[10\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.148:0.148:0.148) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -71,7 +86,7 @@
|
|||
(INSTANCE BUF\[11\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.148:0.148:0.148) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
(INSTANCE BUF\[12\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.151:0.151:0.151) (0.148:0.148:0.148))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
(INSTANCE BUF\[13\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
(INSTANCE BUF\[14\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
(IOPATH A X (0.154:0.154:0.154) (0.150:0.150:0.150))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
(INSTANCE BUF\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
(INSTANCE BUF\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
(INSTANCE BUF\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
(INSTANCE BUF\[6\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
(INSTANCE BUF\[7\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
(INSTANCE BUF\[8\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.144:0.144:0.144))
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
(INSTANCE BUF\[9\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "buff_flash_clkrst")
|
||||
(DATE "Thu Oct 13 17:29:02 2022")
|
||||
(DATE "Sat Oct 15 13:27:38 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
|
@ -15,36 +15,51 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
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|
||||
(INTERCONNECT in_n[10] BUF\[13\].A (0.012:0.012:0.012) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[11] BUF\[14\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
|
||||
(INTERCONNECT in_n[1] BUF\[4\].A (0.014:0.014:0.014) (0.004:0.004:0.004))
|
||||
(INTERCONNECT in_n[2] BUF\[5\].A (0.015:0.015:0.015) (0.005:0.005:0.005))
|
||||
(INTERCONNECT in_n[3] BUF\[6\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
|
||||
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|
||||
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|
||||
(INTERCONNECT in_n[6] BUF\[9\].A (0.015:0.015:0.015) (0.005:0.005:0.005))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
(INTERCONNECT BUF\[9\].X out_s[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT in_e[0] BUF\[3\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
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||||
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||||
(INTERCONNECT in_e[10] BUF\[13\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
(INSTANCE BUF\[0\])
|
||||
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|
||||
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|
||||
(IOPATH A X (0.258:0.258:0.258) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.265:0.265:0.265) (0.267:0.267:0.267))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -62,7 +77,7 @@
|
|||
(INSTANCE BUF\[10\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.260:0.260:0.260) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -71,7 +86,7 @@
|
|||
(INSTANCE BUF\[11\])
|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.269:0.269:0.269) (0.269:0.269:0.269))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.263:0.263:0.263) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.274:0.274:0.274) (0.272:0.272:0.272))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.266:0.266:0.266) (0.267:0.267:0.267))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.263:0.263:0.263) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.263:0.263:0.263) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -143,7 +158,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
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|
||||
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||||
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||||
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|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
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|
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|
||||
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|
||||
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|
||||
|
|
@ -179,7 +194,7 @@
|
|||
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||||
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||||
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|
||||
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|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
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|
||||
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|
||||
(DESIGN "buff_flash_clkrst")
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
|
@ -15,36 +15,51 @@
|
|||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
|
|
@ -62,7 +77,7 @@
|
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|
||||
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|
||||
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|
||||
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|
||||
|
|
@ -71,7 +86,7 @@
|
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
(INSTANCE BUF\[13\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
(INSTANCE BUF\[14\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
(IOPATH A X (0.153:0.153:0.153) (0.150:0.150:0.150))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
(INSTANCE BUF\[1\])
|
||||
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|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.148:0.148:0.148) (0.147:0.147:0.147))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
(INSTANCE BUF\[2\])
|
||||
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|
||||
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|
||||
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
(INSTANCE BUF\[3\])
|
||||
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|
||||
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|
||||
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -143,7 +158,7 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
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|
||||
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||||
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|
||||
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|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
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|
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
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||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
|
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|
|||
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||||
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||||
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|
||||
|
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@ -53,7 +68,7 @@
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||||
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||||
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||||
|
|
@ -62,7 +77,7 @@
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||||
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||||
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|
||||
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|
||||
|
|
@ -71,7 +86,7 @@
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||||
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||||
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|
||||
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|
||||
|
|
@ -80,7 +95,7 @@
|
|||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
|
|
@ -89,7 +104,7 @@
|
|||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
|
|
@ -98,7 +113,7 @@
|
|||
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||||
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||||
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|
||||
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|
||||
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|
||||
|
|
@ -107,7 +122,7 @@
|
|||
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||||
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||||
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||||
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|
||||
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|
||||
|
|
@ -116,7 +131,7 @@
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||||
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|
||||
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|
||||
|
|
@ -125,7 +140,7 @@
|
|||
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|
||||
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|
||||
|
|
@ -134,7 +149,7 @@
|
|||
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|
||||
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|
||||
|
|
@ -152,7 +167,7 @@
|
|||
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||||
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|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
(INSTANCE BUF\[7\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
(INSTANCE BUF\[8\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
(INSTANCE BUF\[9\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
|
||||
(IOPATH A X (0.102:0.102:0.102) (0.099:0.099:0.099))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "buff_flash_clkrst")
|
||||
(DATE "Thu Oct 13 17:29:07 2022")
|
||||
(DATE "Sat Oct 15 13:27:43 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
|
@ -15,36 +15,51 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT in_n[0] BUF\[3\].A (0.027:0.027:0.027) (0.014:0.014:0.014))
|
||||
(INTERCONNECT in_n[10] BUF\[13\].A (0.026:0.026:0.026) (0.014:0.014:0.014))
|
||||
(INTERCONNECT in_n[11] BUF\[14\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_n[1] BUF\[4\].A (0.030:0.030:0.030) (0.016:0.016:0.016))
|
||||
(INTERCONNECT in_n[2] BUF\[5\].A (0.033:0.033:0.033) (0.018:0.018:0.018))
|
||||
(INTERCONNECT in_n[3] BUF\[6\].A (0.027:0.027:0.027) (0.014:0.014:0.014))
|
||||
(INTERCONNECT in_n[4] BUF\[7\].A (0.030:0.030:0.030) (0.016:0.016:0.016))
|
||||
(INTERCONNECT in_n[5] BUF\[8\].A (0.029:0.029:0.029) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_n[6] BUF\[9\].A (0.032:0.032:0.032) (0.018:0.018:0.018))
|
||||
(INTERCONNECT in_n[7] BUF\[10\].A (0.033:0.033:0.033) (0.018:0.018:0.018))
|
||||
(INTERCONNECT in_n[8] BUF\[11\].A (0.027:0.027:0.027) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_n[9] BUF\[12\].A (0.033:0.033:0.033) (0.018:0.018:0.018))
|
||||
(INTERCONNECT in_s[0] BUF\[0\].A (0.026:0.026:0.026) (0.014:0.014:0.014))
|
||||
(INTERCONNECT in_s[1] BUF\[1\].A (0.033:0.033:0.033) (0.018:0.018:0.018))
|
||||
(INTERCONNECT in_s[2] BUF\[2\].A (0.027:0.027:0.027) (0.014:0.014:0.014))
|
||||
(INTERCONNECT BUF\[0\].X out_n[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[10\].X out_s[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[11\].X out_s[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_s[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[14\].X out_s[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[1\].X out_n[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[2\].X out_n[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[3\].X out_s[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[4\].X out_s[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[5\].X out_s[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[6\].X out_s[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[7\].X out_s[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[8\].X out_s[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[9\].X out_s[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT in_e[0] BUF\[3\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[0] ANTENNA_BUF\[3\]_A.DIODE (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[10] BUF\[13\].A (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[10] ANTENNA_BUF\[13\]_A.DIODE (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[11] BUF\[14\].A (0.056:0.056:0.056) (0.032:0.032:0.032))
|
||||
(INTERCONNECT in_e[11] ANTENNA_BUF\[14\]_A.DIODE (0.056:0.056:0.056) (0.032:0.032:0.032))
|
||||
(INTERCONNECT in_e[1] BUF\[4\].A (0.037:0.037:0.037) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[1] ANTENNA_BUF\[4\]_A.DIODE (0.037:0.037:0.037) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[2] BUF\[5\].A (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[2] ANTENNA_BUF\[5\]_A.DIODE (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[3] BUF\[6\].A (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[3] ANTENNA_BUF\[6\]_A.DIODE (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[4] BUF\[7\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[4] ANTENNA_BUF\[7\]_A.DIODE (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[5] BUF\[8\].A (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[5] ANTENNA_BUF\[8\]_A.DIODE (0.036:0.036:0.036) (0.020:0.020:0.020))
|
||||
(INTERCONNECT in_e[6] BUF\[9\].A (0.041:0.041:0.041) (0.023:0.023:0.023))
|
||||
(INTERCONNECT in_e[6] ANTENNA_BUF\[9\]_A.DIODE (0.041:0.041:0.041) (0.023:0.023:0.023))
|
||||
(INTERCONNECT in_e[7] BUF\[10\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[7] ANTENNA_BUF\[10\]_A.DIODE (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[8] BUF\[11\].A (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[8] ANTENNA_BUF\[11\]_A.DIODE (0.038:0.038:0.038) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_e[9] BUF\[12\].A (0.051:0.051:0.051) (0.029:0.029:0.029))
|
||||
(INTERCONNECT in_e[9] ANTENNA_BUF\[12\]_A.DIODE (0.051:0.051:0.051) (0.029:0.029:0.029))
|
||||
(INTERCONNECT in_w[0] BUF\[0\].A (0.037:0.037:0.037) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_w[0] ANTENNA_BUF\[0\]_A.DIODE (0.037:0.037:0.037) (0.021:0.021:0.021))
|
||||
(INTERCONNECT in_w[1] BUF\[1\].A (0.044:0.044:0.044) (0.025:0.025:0.025))
|
||||
(INTERCONNECT in_w[1] ANTENNA_BUF\[1\]_A.DIODE (0.044:0.044:0.044) (0.025:0.025:0.025))
|
||||
(INTERCONNECT in_w[2] BUF\[2\].A (0.035:0.035:0.035) (0.019:0.019:0.019))
|
||||
(INTERCONNECT in_w[2] ANTENNA_BUF\[2\]_A.DIODE (0.035:0.035:0.035) (0.019:0.019:0.019))
|
||||
(INTERCONNECT BUF\[0\].X out_e[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[10\].X out_w[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[11\].X out_w[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[12\].X out_w[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_w[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[14\].X out_w[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[1\].X out_e[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[2\].X out_e[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[3\].X out_w[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[4\].X out_w[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[5\].X out_w[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[6\].X out_w[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[7\].X out_w[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[8\].X out_w[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[9\].X out_w[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
(INSTANCE BUF\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.259:0.259:0.259) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.266:0.266:0.266) (0.268:0.268:0.268))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -62,7 +77,7 @@
|
|||
(INSTANCE BUF\[10\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.261:0.261:0.261) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -71,7 +86,7 @@
|
|||
(INSTANCE BUF\[11\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.265:0.265:0.265) (0.267:0.267:0.267))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
(INSTANCE BUF\[12\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.260:0.260:0.260) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.270:0.270:0.270) (0.270:0.270:0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
(INSTANCE BUF\[13\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
(INSTANCE BUF\[14\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.266:0.266:0.266) (0.268:0.268:0.268))
|
||||
(IOPATH A X (0.275:0.275:0.275) (0.273:0.273:0.273))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
(INSTANCE BUF\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.260:0.260:0.260) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.266:0.266:0.266) (0.268:0.268:0.268))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
(INSTANCE BUF\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
(INSTANCE BUF\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.264:0.264:0.264) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.259:0.259:0.259) (0.263:0.263:0.263))
|
||||
(IOPATH A X (0.263:0.263:0.263) (0.266:0.266:0.266))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -143,7 +158,7 @@
|
|||
(INSTANCE BUF\[5\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.260:0.260:0.260) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
(INSTANCE BUF\[6\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.257:0.257:0.257) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
(INSTANCE BUF\[7\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.263:0.263:0.263) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
(INSTANCE BUF\[8\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.258:0.258:0.258) (0.262:0.262:0.262))
|
||||
(IOPATH A X (0.262:0.262:0.262) (0.265:0.265:0.265))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
(INSTANCE BUF\[9\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.261:0.261:0.261) (0.264:0.264:0.264))
|
||||
(IOPATH A X (0.266:0.266:0.266) (0.268:0.268:0.268))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "buff_flash_clkrst")
|
||||
(DATE "Thu Oct 13 17:29:07 2022")
|
||||
(DATE "Sat Oct 15 13:27:43 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
|
@ -15,36 +15,51 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT in_n[0] BUF\[3\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[10] BUF\[13\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[11] BUF\[14\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_n[1] BUF\[4\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_n[2] BUF\[5\].A (0.022:0.022:0.022) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_n[3] BUF\[6\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[4] BUF\[7\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_n[5] BUF\[8\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
|
||||
(INTERCONNECT in_n[6] BUF\[9\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_n[7] BUF\[10\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_n[8] BUF\[11\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_n[9] BUF\[12\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_s[0] BUF\[0\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
|
||||
(INTERCONNECT in_s[1] BUF\[1\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
|
||||
(INTERCONNECT in_s[2] BUF\[2\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
|
||||
(INTERCONNECT BUF\[0\].X out_n[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[10\].X out_s[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[11\].X out_s[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_s[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[14\].X out_s[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[1\].X out_n[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[2\].X out_n[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[3\].X out_s[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[4\].X out_s[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[5\].X out_s[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[6\].X out_s[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[7\].X out_s[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[8\].X out_s[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[9\].X out_s[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT in_e[0] BUF\[3\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[0] ANTENNA_BUF\[3\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[10] BUF\[13\].A (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[10] ANTENNA_BUF\[13\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[11] BUF\[14\].A (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT in_e[11] ANTENNA_BUF\[14\]_A.DIODE (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT in_e[1] BUF\[4\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[1] ANTENNA_BUF\[4\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[2] BUF\[5\].A (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[2] ANTENNA_BUF\[5\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[3] BUF\[6\].A (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[3] ANTENNA_BUF\[6\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[4] BUF\[7\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[4] ANTENNA_BUF\[7\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[5] BUF\[8\].A (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[5] ANTENNA_BUF\[8\]_A.DIODE (0.023:0.023:0.023) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[6] BUF\[9\].A (0.026:0.026:0.026) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[6] ANTENNA_BUF\[9\]_A.DIODE (0.026:0.026:0.026) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[7] BUF\[10\].A (0.024:0.024:0.024) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[7] ANTENNA_BUF\[10\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_e[8] BUF\[11\].A (0.024:0.024:0.024) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[8] ANTENNA_BUF\[11\]_A.DIODE (0.024:0.024:0.024) (0.011:0.011:0.011))
|
||||
(INTERCONNECT in_e[9] BUF\[12\].A (0.033:0.033:0.033) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_e[9] ANTENNA_BUF\[12\]_A.DIODE (0.033:0.033:0.033) (0.015:0.015:0.015))
|
||||
(INTERCONNECT in_w[0] BUF\[0\].A (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_w[0] ANTENNA_BUF\[0\]_A.DIODE (0.024:0.024:0.024) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_w[1] BUF\[1\].A (0.028:0.028:0.028) (0.012:0.012:0.012))
|
||||
(INTERCONNECT in_w[1] ANTENNA_BUF\[1\]_A.DIODE (0.028:0.028:0.028) (0.012:0.012:0.012))
|
||||
(INTERCONNECT in_w[2] BUF\[2\].A (0.022:0.022:0.022) (0.010:0.010:0.010))
|
||||
(INTERCONNECT in_w[2] ANTENNA_BUF\[2\]_A.DIODE (0.022:0.022:0.022) (0.010:0.010:0.010))
|
||||
(INTERCONNECT BUF\[0\].X out_e[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[10\].X out_w[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[11\].X out_w[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[12\].X out_w[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[13\].X out_w[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[14\].X out_w[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[1\].X out_e[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[2\].X out_e[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[3\].X out_w[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[4\].X out_w[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[5\].X out_w[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[6\].X out_w[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[7\].X out_w[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[8\].X out_w[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
(INTERCONNECT BUF\[9\].X out_w[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -53,7 +68,7 @@
|
|||
(INSTANCE BUF\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -62,7 +77,7 @@
|
|||
(INSTANCE BUF\[10\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
(IOPATH A X (0.148:0.148:0.148) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -71,7 +86,7 @@
|
|||
(INSTANCE BUF\[11\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.148:0.148:0.148) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -80,7 +95,7 @@
|
|||
(INSTANCE BUF\[12\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.151:0.151:0.151) (0.148:0.148:0.148))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -89,7 +104,7 @@
|
|||
(INSTANCE BUF\[13\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -98,7 +113,7 @@
|
|||
(INSTANCE BUF\[14\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.148:0.148:0.148))
|
||||
(IOPATH A X (0.154:0.154:0.154) (0.150:0.150:0.150))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -107,7 +122,7 @@
|
|||
(INSTANCE BUF\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -116,7 +131,7 @@
|
|||
(INSTANCE BUF\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -125,7 +140,7 @@
|
|||
(INSTANCE BUF\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.148:0.148:0.148) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -134,7 +149,7 @@
|
|||
(INSTANCE BUF\[4\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -143,7 +158,7 @@
|
|||
(INSTANCE BUF\[5\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -152,7 +167,7 @@
|
|||
(INSTANCE BUF\[6\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -161,7 +176,7 @@
|
|||
(INSTANCE BUF\[7\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -170,7 +185,7 @@
|
|||
(INSTANCE BUF\[8\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
|
||||
(IOPATH A X (0.147:0.147:0.147) (0.146:0.146:0.146))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -179,7 +194,7 @@
|
|||
(INSTANCE BUF\[9\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
|
||||
(IOPATH A X (0.149:0.149:0.149) (0.147:0.147:0.147))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,107 +1,107 @@
|
|||
module buff_flash_clkrst (VPWR,
|
||||
VGND,
|
||||
in_n,
|
||||
in_s,
|
||||
out_n,
|
||||
out_s);
|
||||
in_e,
|
||||
in_w,
|
||||
out_e,
|
||||
out_w);
|
||||
input VPWR;
|
||||
input VGND;
|
||||
input [11:0] in_n;
|
||||
input [2:0] in_s;
|
||||
output [2:0] out_n;
|
||||
output [11:0] out_s;
|
||||
input [11:0] in_e;
|
||||
input [2:0] in_w;
|
||||
output [2:0] out_e;
|
||||
output [11:0] out_w;
|
||||
|
||||
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[0] (.A(in_s[0]),
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[0] (.A(in_w[0]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_n[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[10] (.A(in_n[7]),
|
||||
.X(out_e[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[10] (.A(in_e[7]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[7]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[11] (.A(in_n[8]),
|
||||
.X(out_w[7]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[11] (.A(in_e[8]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[8]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[12] (.A(in_n[9]),
|
||||
.X(out_w[8]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[12] (.A(in_e[9]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[9]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[13] (.A(in_n[10]),
|
||||
.X(out_w[9]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[13] (.A(in_e[10]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[10]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[14] (.A(in_n[11]),
|
||||
.X(out_w[10]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[14] (.A(in_e[11]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[11]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[1] (.A(in_s[1]),
|
||||
.X(out_w[11]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[1] (.A(in_w[1]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_n[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[2] (.A(in_s[2]),
|
||||
.X(out_e[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[2] (.A(in_w[2]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_n[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[3] (.A(in_n[0]),
|
||||
.X(out_e[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[3] (.A(in_e[0]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[4] (.A(in_n[1]),
|
||||
.X(out_w[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[4] (.A(in_e[1]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[5] (.A(in_n[2]),
|
||||
.X(out_w[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[5] (.A(in_e[2]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[6] (.A(in_n[3]),
|
||||
.X(out_w[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[6] (.A(in_e[3]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[3]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[7] (.A(in_n[4]),
|
||||
.X(out_w[3]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[7] (.A(in_e[4]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[4]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[8] (.A(in_n[5]),
|
||||
.X(out_w[4]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[8] (.A(in_e[5]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[5]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[9] (.A(in_n[6]),
|
||||
.X(out_w[5]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[9] (.A(in_e[6]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[6]));
|
||||
.X(out_w[6]));
|
||||
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
|
|
@ -156,6 +156,81 @@ module buff_flash_clkrst (VPWR,
|
|||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[3]_A (.DIODE(in_e[0]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[13]_A (.DIODE(in_e[10]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[14]_A (.DIODE(in_e[11]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[4]_A (.DIODE(in_e[1]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[5]_A (.DIODE(in_e[2]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[6]_A (.DIODE(in_e[3]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[7]_A (.DIODE(in_e[4]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[8]_A (.DIODE(in_e[5]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[9]_A (.DIODE(in_e[6]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[10]_A (.DIODE(in_e[7]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[11]_A (.DIODE(in_e[8]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[12]_A (.DIODE(in_e[9]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[0]_A (.DIODE(in_w[0]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[1]_A (.DIODE(in_w[1]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__diode_2 \ANTENNA_BUF[2]_A (.DIODE(in_w[2]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
|
|
@ -164,19 +239,27 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_0_19 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_19 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_23 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_0_29 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_26 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_41 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_29 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_33 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_39 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
@ -208,11 +291,15 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_1_47 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_47 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_51 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_1_54 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
@ -228,7 +315,11 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_6 FILLER_2_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_11 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
@ -236,7 +327,11 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_2_29 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_2_33 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
@ -244,15 +339,19 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_2_67 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_67 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_3_3 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_2_73 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_15 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_3 FILLER_3_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_3_8 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
@ -260,7 +359,11 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_3_42 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_42 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_48 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
@ -288,23 +391,35 @@ module buff_flash_clkrst (VPWR,
|
|||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_19 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_19 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_27 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_3 FILLER_4_25 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_4_29 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_4_29 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_4_41 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__decap_6 FILLER_4_33 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_4_53 (.VGND(VGND),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_39 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_42 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_48 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_4_54 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
|
|
|
|||
|
|
@ -1,17 +1,22 @@
|
|||
module buff_flash_clkrst (
|
||||
input[11:0] in_n,
|
||||
input[2:0] in_s,
|
||||
output[11:0] out_s,
|
||||
output[2:0] out_n,
|
||||
input VPWR,
|
||||
input VGND);
|
||||
`ifdef USE_POWER_PINS
|
||||
inout VPWR,
|
||||
inout VGND,
|
||||
`endif
|
||||
input[11:0] in_e,
|
||||
input[2:0] in_w,
|
||||
output[11:0] out_w,
|
||||
output[2:0] out_e);
|
||||
|
||||
sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (
|
||||
.A({in_n, in_s}),
|
||||
.X({out_s, out_n}),
|
||||
`ifdef USE_POWER_PINS
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
.VPWR(VPWR)
|
||||
`endif
|
||||
.A({in_e, in_w}),
|
||||
.X({out_w, out_e})
|
||||
);
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue