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update hk_regs_wr_wb_cpu test to include all house keeping regs

This commit is contained in:
M0stafaRady 2022-10-06 11:16:07 -07:00
parent 7e407e1155
commit 4f483adb36
2 changed files with 137 additions and 46 deletions
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164
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c
View File

@ -7,45 +7,66 @@ void main(){
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// store RO value regs
int old_reg_hkspi_status = reg_hkspi_status;
int old_reg_hkspi_chip_id = reg_hkspi_chip_id;
int old_reg_hkspi_user_id = reg_hkspi_user_id;
int old_reg_hkspi_trap = reg_hkspi_trap;
int old_reg_hkspi_irq = reg_hkspi_irq;
// write 1 ones to all registers
reg_mprj_io_0 = 0x1FFF;
reg_mprj_io_1 = 0x1FFF;
reg_mprj_io_2 = 0x1FFF;
reg_mprj_io_3 = 0x1FFF;
reg_mprj_io_4 = 0x1FFF;
reg_mprj_io_5 = 0x1FFF;
reg_mprj_io_6 = 0x1FFF;
reg_mprj_io_7 = 0x1FFF;
reg_mprj_io_8 = 0x1FFF;
reg_mprj_io_9 = 0x1FFF;
reg_mprj_io_10 = 0x1FFF;
reg_mprj_io_11 = 0x1FFF;
reg_mprj_io_12 = 0x1FFF;
reg_mprj_io_13 = 0x1FFF;
reg_mprj_io_14 = 0x1FFF;
reg_mprj_io_15 = 0x1FFF;
reg_mprj_io_16 = 0x1FFF;
reg_mprj_io_17 = 0x1FFF;
reg_mprj_io_18 = 0x1FFF;
reg_mprj_io_19 = 0x1FFF;
reg_mprj_io_20 = 0x1FFF;
reg_mprj_io_21 = 0x1FFF;
reg_mprj_io_22 = 0x1FFF;
reg_mprj_io_23 = 0x1FFF;
reg_mprj_io_24 = 0x1FFF;
reg_mprj_io_25 = 0x1FFF;
reg_mprj_io_26 = 0x1FFF;
reg_mprj_io_27 = 0x1FFF;
reg_mprj_io_28 = 0x1FFF;
reg_mprj_io_29 = 0x1FFF;
reg_mprj_io_30 = 0x1FFF;
reg_mprj_io_31 = 0x1FFF;
reg_mprj_io_32 = 0x1FFF;
reg_mprj_io_33 = 0x1FFF;
reg_mprj_io_34 = 0x1FFF;
reg_mprj_io_35 = 0x1FFF;
reg_mprj_io_36 = 0x1FFF;
reg_mprj_io_37 = 0x1FFF;
reg_mprj_io_0 = 0xFFFFFFFF;
reg_mprj_io_1 = 0xFFFFFFFF;
reg_mprj_io_2 = 0xFFFFFFFF;
reg_mprj_io_3 = 0xFFFFFFFF;
reg_mprj_io_4 = 0xFFFFFFFF;
reg_mprj_io_5 = 0xFFFFFFFF;
reg_mprj_io_6 = 0xFFFFFFFF;
reg_mprj_io_7 = 0xFFFFFFFF;
reg_mprj_io_8 = 0xFFFFFFFF;
reg_mprj_io_9 = 0xFFFFFFFF;
reg_mprj_io_10 = 0xFFFFFFFF;
reg_mprj_io_11 = 0xFFFFFFFF;
reg_mprj_io_12 = 0xFFFFFFFF;
reg_mprj_io_13 = 0xFFFFFFFF;
reg_mprj_io_14 = 0xFFFFFFFF;
reg_mprj_io_15 = 0xFFFFFFFF;
reg_mprj_io_16 = 0xFFFFFFFF;
reg_mprj_io_17 = 0xFFFFFFFF;
reg_mprj_io_18 = 0xFFFFFFFF;
reg_mprj_io_19 = 0xFFFFFFFF;
reg_mprj_io_20 = 0xFFFFFFFF;
reg_mprj_io_21 = 0xFFFFFFFF;
reg_mprj_io_22 = 0xFFFFFFFF;
reg_mprj_io_23 = 0xFFFFFFFF;
reg_mprj_io_24 = 0xFFFFFFFF;
reg_mprj_io_25 = 0xFFFFFFFF;
reg_mprj_io_26 = 0xFFFFFFFF;
reg_mprj_io_27 = 0xFFFFFFFF;
reg_mprj_io_28 = 0xFFFFFFFF;
reg_mprj_io_29 = 0xFFFFFFFF;
reg_mprj_io_30 = 0xFFFFFFFF;
reg_mprj_io_31 = 0xFFFFFFFF;
reg_mprj_io_32 = 0xFFFFFFFF;
reg_mprj_io_33 = 0xFFFFFFFF;
reg_mprj_io_34 = 0xFFFFFFFF;
reg_mprj_io_35 = 0xFFFFFFFF;
reg_mprj_io_36 = 0xFFFFFFFF;
reg_mprj_io_37 = 0xFFFFFFFF;
// house keeping
reg_hkspi_status = 0xFFFFFFFF;
reg_hkspi_chip_id = 0xFFFFFFFF;
reg_hkspi_user_id = 0xFFFFFFFF;
reg_hkspi_pll_ena = 0xFFFFFFFF;
reg_hkspi_pll_bypass = 0xFFFFFFFF;
reg_hkspi_irq = 0xFFFFFFFF;
// reg_hkspi_reset = 0xFFFFFFFF; can't write 1 to it cpu would be reset
reg_hkspi_trap = 0xFFFFFFFF;
reg_hkspi_pll_trim = 0xFFFFFFFF;
reg_hkspi_pll_source = 0xFFFFFFFF;
reg_hkspi_pll_divider = 0xFFFFFFFF;
// sys
reg_clk_out_dest = 0xFFFFFFFF;
reg_hkspi_disable = 0xFFFFFFFF;
// read ones that has been written
if (reg_mprj_io_0 != 0x1FFF)
@ -124,8 +145,31 @@ void main(){
reg_debug_1 =0x25;
if (reg_mprj_io_37 != 0x1FFF)
reg_debug_1 =0x26;
// housekeeping
if (reg_hkspi_status != old_reg_hkspi_status) // RO
reg_debug_1 =0x27;
if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO
reg_debug_1 =0x28;
if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO
reg_debug_1 =0x29;
if (reg_hkspi_pll_ena != 0x3) // size =2
reg_debug_1 =0x2a;
if (reg_hkspi_pll_bypass != 0x1) // size = 1
reg_debug_1 = 0x2b;
if (reg_hkspi_irq != old_reg_hkspi_irq) // RO
reg_debug_1 = 0x2c;
if (reg_hkspi_trap != old_reg_hkspi_trap) // RO
reg_debug_1 =0x2d;
if (reg_hkspi_pll_trim != 0x3FFFFFF) // size 26
reg_debug_1 = 0x2f;
if (reg_hkspi_pll_source != 0x3F) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
reg_debug_1 =0x2f;
if (reg_hkspi_pll_divider != 0x1F) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider
reg_debug_1 =0x30;
if (reg_hkspi_disable != 0x1) // size 1
reg_debug_1 =0x31;
if (reg_clk_out_dest != 0x7) // trap and clocks redirect
reg_debug_1 =0x32;
// // write zeros to all registers
reg_mprj_io_0 = 0x0;
reg_mprj_io_1 = 0x0;
@ -165,6 +209,21 @@ void main(){
reg_mprj_io_35 = 0x0;
reg_mprj_io_36 = 0x0;
reg_mprj_io_37 = 0x0;
// house keeping
reg_hkspi_status = 0x0;
reg_hkspi_chip_id = 0x0;
reg_hkspi_user_id = 0x0;
reg_hkspi_pll_ena = 0x0;
reg_hkspi_pll_bypass = 0x0;
reg_hkspi_irq = 0x0;
reg_hkspi_reset = 0x0;
reg_hkspi_trap = 0x0;
reg_hkspi_pll_trim = 0x0;
reg_hkspi_pll_source = 0x0;
reg_hkspi_pll_divider = 0x0;
// sys
reg_clk_out_dest = 0x0;
reg_hkspi_disable = 0x0;
// // read zeros that has been written
if (reg_mprj_io_0 != 0x0)
@ -243,6 +302,31 @@ void main(){
reg_debug_2 =0x25;
if (reg_mprj_io_37 != 0x0)
reg_debug_2 =0x26;
// housekeeping
if (reg_hkspi_status != old_reg_hkspi_status) // RO
reg_debug_2 =0x27;
if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO
reg_debug_2 =0x28;
if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO
reg_debug_2 =0x29;
if (reg_hkspi_pll_ena != 0x0) // size =2
reg_debug_2 =0x2a;
if (reg_hkspi_pll_bypass != 0x0) // size = 1
reg_debug_2 = 0x2b;
if (reg_hkspi_irq != old_reg_hkspi_irq) // RO
reg_debug_2 = 0x2c;
if (reg_hkspi_trap != old_reg_hkspi_trap) // RO
reg_debug_2 =0x2d;
if (reg_hkspi_pll_trim != 0x0) // size 26
reg_debug_2 = 0x2f;
if (reg_hkspi_pll_source != 0x0) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
reg_debug_2 =0x2f;
if (reg_hkspi_pll_divider != 0x0) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider
reg_debug_2 =0x30;
if (reg_hkspi_disable != 0x0) // size 1
reg_debug_2 =0x31;
if (reg_clk_out_dest != 0x0) // trap and clocks redirect
reg_debug_2 =0x32;
reg_debug_2 = 0xFF;
}

15
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
View File

@ -70,22 +70,29 @@ async def hk_regs_wr_wb(dut):
@cocotb.test()
@repot_test
async def hk_regs_wr_wb_cpu(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=157521,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=198243,num_error=INFINITY)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
reg1 =0 # buffer
reg2 =0
regs_list = ("reg_hkspi_status","reg_hkspi_chip_id","reg_hkspi_user_id", "reg_hkspi_pll_ena","reg_hkspi_pll_bypass","reg_hkspi_irq","reg_hkspi_trap","reg_hkspi_pll_trim","reg_hkspi_pll_source","reg_hkspi_pll_divide","reg_clk_out_des","reg_hkspi_disable")
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
cocotb.log.error(f"[TEST] error while writing 0x1FFF to reg_mprj_io_{reg1-1}")
if reg1 < 38:
cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to reg_mprj_io_{reg1-1}")
else:
cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to {regs_list[reg1-39]}")
if reg2 != cpu.read_debug_reg2():
reg2 = cpu.read_debug_reg2()
cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}")
await ClockCycles(caravelEnv.clk,10)
if reg1 < 38:
cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}")
else:
cocotb.log.error(f"[TEST] error while writing 0x0 to {regs_list[reg1-39]}")
await ClockCycles(caravelEnv.clk,1)
'''randomly write then read housekeeping regs through SPI'''
@cocotb.test()