From 4cf7aa29838b256070f9a32f59606805f019e764 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Thu, 2 Dec 2021 14:26:59 -0500 Subject: [PATCH] Changed the synchronized reset to occur on the clock falling edge to give more timing margin when reset is released (note to self: shouldn't the ext_reset also be synchronized?). --- verilog/rtl/caravel_clocking.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v index 3f62e810..cd2c7aaa 100644 --- a/verilog/rtl/caravel_clocking.v +++ b/verilog/rtl/caravel_clocking.v @@ -97,7 +97,7 @@ module caravel_clocking( // Staged-delay reset reg [2:0] reset_delay; - always @(posedge core_clk or negedge resetb) begin + always @(negedge core_clk or negedge resetb) begin if (resetb == 1'b0) begin reset_delay <= 3'b111; end else begin