Added pins "vddio" and "vssio" to the openframe and openframe project

wrapper RTL netlists and and openframe project wrapper GL netlist.
This commit is contained in:
Tim Edwards 2023-10-18 12:47:56 -04:00
parent 15bd09f066
commit 4cd9d9cf2a
3 changed files with 10 additions and 2 deletions

View File

@ -1016,6 +1016,8 @@ module caravel_openframe(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd,
.resetb_h(rstb_h), .resetb_h(rstb_h),
.resetb_l(rstb_l), .resetb_l(rstb_l),
.vccd1(vccd1_core), .vccd1(vccd1_core),
.vssd1(vssd1_core) .vssd1(vssd1_core),
.vddio(vddio_core),
.vssio(vssio_core)
); );
endmodule endmodule

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@ -1026,6 +1026,8 @@ module caravel_openframe(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd,
.vssa2(vssa2_core), .vssa2(vssa2_core),
.vssd(vssd_core), .vssd(vssd_core),
.vssd1(vssd1_core), .vssd1(vssd1_core),
.vssd2(vssd2_core) .vssd2(vssd2_core),
.vddio(vddio_core),
.vssio(vssio_core)
); );
endmodule endmodule

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@ -43,6 +43,8 @@ module openframe_project_wrapper (
inout vssd, // Common digital ground inout vssd, // Common digital ground
inout vssd1, // User area 1 digital ground inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground inout vssd2, // User area 2 digital ground
inout vddio, // Common 3.3V ESD supply
inout vssio, // Common ESD ground
`endif `endif
/* Signals exported from the frame area to the user project */ /* Signals exported from the frame area to the user project */
@ -116,6 +118,8 @@ module openframe_project_wrapper (
.vssd(vssd), .vssd(vssd),
.vssd1(vssd1), .vssd1(vssd1),
.vssd2(vssd2), .vssd2(vssd2),
.vddio(vddio),
.vssio(vssio),
`endif `endif
.porb_h(porb_h), .porb_h(porb_h),
.porb_l(porb_l), .porb_l(porb_l),