From c7df730c0a379fea42b4b56c088cba34e12a6b89 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 18 Oct 2022 02:56:31 -0700 Subject: [PATCH 1/3] cocotb - ziping passed waves instead of removing them --- verilog/dv/cocotb/verify_cocotb.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index dd2dac95..0cb2e7fe 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -16,7 +16,7 @@ import shutil iverilog = True vcs = False coverage = False -remove_waves = True +zip_waves = True def go_up(path, n): for i in range(n): @@ -138,10 +138,9 @@ class RunTest: self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() #delete wave when passed - if self.passed == "passed" and remove_waves: - os.system(f'rm {self.cocotb_path}/{self.sim_path}*.vpd') - os.system(f'rm {self.cocotb_path}/{self.sim_path}*.vcd') - os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") + if self.passed == "passed" and zip_waves: + test_location = f'{self.cocotb_path}/{self.sim_path}' + os.system(f'zip -m {test_location}/waves_logs.zip {test_location}/*.log {test_location}/*.vpd {test_location}/*.vcd') if os.path.exists(f"{self.cocotb_path}/sdfAnnotateInfo"): shutil.move(f"{self.cocotb_path}/sdfAnnotateInfo", f"{self.sim_path}/sdfAnnotateInfo") shutil.copyfile(f'{self.cocotb_path}/hex_files/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex') @@ -411,7 +410,7 @@ parser.add_argument('-maxerr', help='max number of errors for every test before parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used') parser.add_argument('-cov',action='store_true', help='enable code coverage') parser.add_argument('-corner','-c', nargs='+' ,help='Corner type in case of GL_SDF run has to be provided') -parser.add_argument('-keep_pass_wave',action='store_true', help='Normally the waves of passed tests would be removed using this option will not remove them ') +parser.add_argument('-keep_pass_unzip',action='store_true', help='Normally the waves and logs of passed tests would be zipped. Using this option they wouldn\'t be zipped') args = parser.parse_args() if (args.vcs) : iverilog = False @@ -422,8 +421,8 @@ if args.sim == None: args.sim= ["RTL"] if args.corner == None: args.corner= ["nom-t"] -if args.keep_pass_wave: - remove_waves = False +if args.keep_pass_unzip: + zip_waves = False print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}") main(args) From 13c2f299d0dfdae6eee08d316f587d9ea858ab42 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 18 Oct 2022 03:12:58 -0700 Subject: [PATCH 2/3] cocotb - update script to keep the test log when test pass --- verilog/dv/cocotb/verify_cocotb.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index 0cb2e7fe..d68e6014 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -139,8 +139,9 @@ class RunTest: Path(f'{self.sim_path}/{self.passed}').touch() #delete wave when passed if self.passed == "passed" and zip_waves: - test_location = f'{self.cocotb_path}/{self.sim_path}' - os.system(f'zip -m {test_location}/waves_logs.zip {test_location}/*.log {test_location}/*.vpd {test_location}/*.vcd') + os.chdir(f'{self.cocotb_path}/{self.sim_path}') + os.system(f'zip -m waves_logs.zip analysis.log test.log *.vpd *.vcd') + self.cd_cocotb() if os.path.exists(f"{self.cocotb_path}/sdfAnnotateInfo"): shutil.move(f"{self.cocotb_path}/sdfAnnotateInfo", f"{self.sim_path}/sdfAnnotateInfo") shutil.copyfile(f'{self.cocotb_path}/hex_files/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex') From 2a05ee19ae98b00523e574bc7ac1a309cf616f91 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 18 Oct 2022 03:49:45 -0700 Subject: [PATCH 3/3] cocotb - fix bug at debug test for gate level --- verilog/dv/cocotb/tests/debug/debug.c | 6 ++---- verilog/dv/cocotb/tests/debug/debug.py | 4 ++-- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/verilog/dv/cocotb/tests/debug/debug.c b/verilog/dv/cocotb/tests/debug/debug.c index b54e35ff..33ed397e 100644 --- a/verilog/dv/cocotb/tests/debug/debug.c +++ b/verilog/dv/cocotb/tests/debug/debug.c @@ -32,14 +32,12 @@ void main() reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; - (*(volatile uint32_t*) CSR_DEBUG_MODE_OUT_ADDR ) = 1; // enable debug mode - - // Now, apply the configuration reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); + + (*(volatile uint32_t*) CSR_DEBUG_MODE_OUT_ADDR ) = 1; // enable debug mode - // reg_uart_enable = 1; // start of the test reg_debug_1 = 0xAA; diff --git a/verilog/dv/cocotb/tests/debug/debug.py b/verilog/dv/cocotb/tests/debug/debug.py index 7dbc900d..3b19f552 100644 --- a/verilog/dv/cocotb/tests/debug/debug.py +++ b/verilog/dv/cocotb/tests/debug/debug.py @@ -19,7 +19,7 @@ reg = Regs() @cocotb.test() @repot_test async def debug(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=375862) + caravelEnv,clock = await test_configure(dut,timeout_cycles=33840) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -82,7 +82,7 @@ async def uart_get_char(caravelEnv): async def wb_write(caravelEnv,addr,data): addr_bits = bin(addr)[2:].zfill(32)[::-1] data_bits = bin(data)[2:].zfill(32)[::-1] - cocotb.log.info(f"[TEST] address bits = {addr_bits} {type(addr_bits)}") + cocotb.log.debug(f"[TEST] address bits = {addr_bits} {type(addr_bits)}") await uart_send_char(caravelEnv, '10000000') # write cmd await uart_send_char(caravelEnv, '10000000') # size await uart_send_char(caravelEnv, addr_bits[24:32])