From d464a475e0b93e9c618dbbaae0e0a567cc5bad91 Mon Sep 17 00:00:00 2001
From: M0stafaRady <mostafa.rady@efabless.com>
Date: Wed, 12 Oct 2022 03:57:22 -0700
Subject: [PATCH] update gpio tests to release housekeeping spi csb

---
 verilog/dv/cocotb/tests.json              | 6 ------
 verilog/dv/cocotb/tests/gpio/gpio.py      | 6 ++++--
 verilog/dv/cocotb/tests/gpio/gpio_user.py | 6 ++++--
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json
index d93a6dc8..df9615aa 100644
--- a/verilog/dv/cocotb/tests.json
+++ b/verilog/dv/cocotb/tests.json
@@ -63,12 +63,6 @@
             "GL":["r_gl","push_gl","nightly","weekly","tape_out"],
             "GL_SDF":["r_sdf","weekly","tape_out"],
             "description":"configure all gpios as user input pull down using automatic approach firmware and check them"}
-        ,"gpio_all_bidir" :{"level":0, 
-            "SW":true,
-            "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
-            "GL":["r_gl","push_gl","nightly","weekly","tape_out"],
-            "GL_SDF":["r_sdf","weekly","tape_out"],
-            "description":"configure all gpios as mgmt bidir  using automatic approach firmware and check them"}
         ,"gpio_all_bidir_user" :{"level":0, 
             "SW":true,
             "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py
index 778a1bf3..a22d5533 100644
--- a/verilog/dv/cocotb/tests/gpio/gpio.py
+++ b/verilog/dv/cocotb/tests/gpio/gpio.py
@@ -21,6 +21,7 @@ async def gpio_all_o(dut):
     cpu.cpu_release_reset()
    
     await wait_reg1(cpu,caravelEnv,0xAA)
+    await caravelEnv.release_csb()
     cocotb.log.info("[TEST] finish configuring ")
     i= 0x20
     for j in range(5):
@@ -156,13 +157,13 @@ async def gpio_all_i(dut):
 @repot_test
 async def gpio_all_i_pu(dut):
     caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
-    await caravelEnv.release_csb()
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     uut = dut.uut
 
     await wait_reg1(cpu,caravelEnv,0xAA)
+    await caravelEnv.release_csb()
     # monitor the output of padframe module it suppose to be all ones  when no input is applied
     await ClockCycles(caravelEnv.clk,100) 
     gpio = dut.uut.padframe.mprj_io_in.value.binstr
@@ -258,13 +259,13 @@ async def gpio_all_i_pu(dut):
 @repot_test
 async def gpio_all_i_pd(dut):
     caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
-    await caravelEnv.release_csb()
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     uut = dut.uut
     
     await wait_reg1(cpu,caravelEnv,0xAA)
+    await caravelEnv.release_csb()
     # monitor the output of padframe module it suppose to be all ones  when no input is applied
     await ClockCycles(caravelEnv.clk,100) 
     gpio = dut.uut.padframe.mprj_io_in.value.binstr
@@ -365,6 +366,7 @@ async def gpio_all_bidir(dut):
     cpu.cpu_release_reset()
     uut = dut.uut
     await wait_reg1(cpu,caravelEnv,0x1A)
+    await caravelEnv.release_csb()
     cocotb.log.info("[TEST] finish configuring ")
     i= 0x20
     for j in range(5):
diff --git a/verilog/dv/cocotb/tests/gpio/gpio_user.py b/verilog/dv/cocotb/tests/gpio/gpio_user.py
index d8394e62..9b7ccee7 100644
--- a/verilog/dv/cocotb/tests/gpio/gpio_user.py
+++ b/verilog/dv/cocotb/tests/gpio/gpio_user.py
@@ -21,6 +21,7 @@ async def gpio_all_o_user(dut):
     cpu.cpu_release_reset()
    
     await wait_reg1(cpu,caravelEnv,0xAA)
+    await caravelEnv.release_csb()
     cocotb.log.info("[TEST] finish configuring as user output")
     i= 0x20
     for j in range(5):
@@ -155,13 +156,13 @@ async def gpio_all_i_user(dut):
 @repot_test
 async def gpio_all_i_pu_user(dut):
     caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
-    await caravelEnv.release_csb()
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     uut = dut.uut
 
     await wait_reg1(cpu,caravelEnv,0xAA)
+    await caravelEnv.release_csb()
     # monitor the output of padframe module it suppose to be all ones  when no input is applied
     await ClockCycles(caravelEnv.clk,100) 
     gpio = dut.uut.padframe.mprj_io_in.value.binstr
@@ -257,13 +258,13 @@ async def gpio_all_i_pu_user(dut):
 @repot_test
 async def gpio_all_i_pd_user(dut):
     caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
-    await caravelEnv.release_csb()
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     uut = dut.uut
     
     await wait_reg1(cpu,caravelEnv,0xAA)
+    await caravelEnv.release_csb()
     # monitor the output of padframe module it suppose to be all ones  when no input is applied
     await ClockCycles(caravelEnv.clk,100) 
     gpio = dut.uut.padframe.mprj_io_in.value.binstr
@@ -366,6 +367,7 @@ async def gpio_all_bidir_user(dut):
     cpu.cpu_release_reset()
     uut = dut.uut
     await wait_reg1(cpu,caravelEnv,0x1A)
+    await caravelEnv.release_csb()
     cocotb.log.info("[TEST] finish configuring ")
     i= 0x20
     for j in range(5):