From 37720ea216dd6ee304c3e68975677f4a908b6aeb Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 20 Sep 2022 16:00:09 -0400 Subject: [PATCH 01/22] Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module. --- verilog/rtl/caravan.v | 23 ++++--- verilog/rtl/caravel.v | 25 ++++--- verilog/rtl/chip_io.v | 33 +++++---- verilog/rtl/chip_io_alt.v | 31 +++++---- verilog/rtl/mprj_io.v | 9 +-- verilog/rtl/pads.v | 136 ++++++++++++++++++++------------------ 6 files changed, 136 insertions(+), 121 deletions(-) diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 6834a533..5e9c6189 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -165,6 +165,7 @@ module caravan ( wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in; wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3; wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out; + wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_one; // User Project Control (user-facing) // 27 GPIO bidirectional with in/out/oeb and a 3.3V copy of the input @@ -292,6 +293,9 @@ module caravan ( .vssd1 (vssd1_core), .vssd2 (vssd2_core), + // Connect 1.8V constant one to nearest GPIO control block + .vccd_const_one(mprj_io_one[`MPRJ_IO_PADS-`ANALOG_PADS-1]), + .gpio(gpio), .mprj_io(mprj_io), .clock(clock), @@ -325,6 +329,7 @@ module caravan ( .flash_io1_do_core(flash_io1_do), .flash_io0_di_core(flash_io0_di), .flash_io1_di_core(flash_io1_di), + .mprj_io_one(mprj_io_one), .mprj_io_in(mprj_io_in), .mprj_io_in_3v3(mprj_io_in_3v3), .mprj_io_out(mprj_io_out), @@ -1099,7 +1104,7 @@ module caravan ( .mgmt_gpio_out(mgmt_io_out[1:0]), .mgmt_gpio_oeb(mgmt_io_oeb[1:0]), - .one(), + .one(mprj_io_one[1:0]), .zero(), // Serial data chain for pad configuration @@ -1127,7 +1132,6 @@ module caravan ( ); /* Section 1 GPIOs (GPIO 0 to 18) */ - wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:0] one_loop1; /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */ @@ -1153,9 +1157,9 @@ module caravan ( .mgmt_gpio_in(mgmt_io_in[7:2]), .mgmt_gpio_out(mgmt_io_in[7:2]), - .mgmt_gpio_oeb(one_loop1[5:0]), + .mgmt_gpio_oeb(mprj_io_one[7:2]), - .one(one_loop1[5:0]), + .one(mprj_io_one[7:2]), .zero(), // Serial data chain for pad configuration @@ -1205,9 +1209,9 @@ module caravan ( .mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]), .mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]), - .mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]), - .one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]), + .one(mprj_io_one[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]), .zero(), // Serial data chain for pad configuration @@ -1260,7 +1264,7 @@ module caravan ( .mgmt_gpio_out(mgmt_io_out[4:2]), .mgmt_gpio_oeb(mgmt_io_oeb[4:2]), - .one(), + .one(mprj_io_one[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]), .zero(), // Serial data chain for pad configuration @@ -1288,7 +1292,6 @@ module caravan ( ); /* Section 2 GPIOs (GPIO 19 to 37) */ - wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] one_loop2; gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] ( `ifdef USE_POWER_PINS @@ -1312,9 +1315,9 @@ module caravan ( .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]), .mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]), - .mgmt_gpio_oeb(one_loop2), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]), - .one(one_loop2), + .one(mprj_io_one[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]), .zero(), // Serial data chain for pad configuration diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 706cb21a..5ee33bdc 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -142,6 +142,7 @@ module caravel ( wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm; wire [`MPRJ_IO_PADS-1:0] mprj_io_in; wire [`MPRJ_IO_PADS-1:0] mprj_io_out; + wire [`MPRJ_IO_PADS-1:0] mprj_io_one; // User Project Control (user-facing) wire [`MPRJ_IO_PADS-1:0] user_io_oeb; @@ -252,7 +253,8 @@ module caravel ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - + // Connect 1.8V constant one to nearest GPIO control block + .vccd_const_one(mprj_io_one[`MPRJ_IO_PADS-1]), .gpio(gpio), .mprj_io(mprj_io), .clock(clock), @@ -286,6 +288,7 @@ module caravel ( .flash_io1_do_core(flash_io1_do), .flash_io0_di_core(flash_io0_di), .flash_io1_di_core(flash_io1_di), + .mprj_io_one(mprj_io_one), .mprj_io_in(mprj_io_in), .mprj_io_out(mprj_io_out), .mprj_io_oeb(mprj_io_oeb), @@ -1152,7 +1155,7 @@ module caravel ( .mgmt_gpio_out(mgmt_io_out[1:0]), .mgmt_gpio_oeb(mgmt_io_oeb[1:0]), - .one(), + .one(mprj_io_one[1:0]), .zero(), // Serial data chain for pad configuration @@ -1179,9 +1182,6 @@ module caravel ( .pad_gpio_in(mprj_io_in[1:0]) ); - /* Section 1 GPIOs (GPIO 0 to 18) */ - wire [`MPRJ_IO_PADS_1-1:2] one_loop1; - /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */ gpio_control_block gpio_control_in_1a [5:0] ( @@ -1206,9 +1206,9 @@ module caravel ( .mgmt_gpio_in(mgmt_io_in[7:2]), .mgmt_gpio_out(mgmt_io_in[7:2]), - .mgmt_gpio_oeb(one_loop1[7:2]), + .mgmt_gpio_oeb(mprj_io_one[7:2]), - .one(one_loop1[7:2]), + .one(mprj_io_one[7:2]), .zero(), // Serial data chain for pad configuration @@ -1259,9 +1259,9 @@ module caravel ( .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]), .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]), - .mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]), - .one(one_loop1[(`MPRJ_IO_PADS_1-1):8]), + .one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]), .zero(), // Serial data chain for pad configuration @@ -1314,7 +1314,7 @@ module caravel ( .mgmt_gpio_out(mgmt_io_out[4:2]), .mgmt_gpio_oeb(mgmt_io_oeb[4:2]), - .one(), + .one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]), .zero(), // Serial data chain for pad configuration @@ -1342,7 +1342,6 @@ module caravel ( ); /* Section 2 GPIOs (GPIO 19 to 34) */ - wire [`MPRJ_IO_PADS_2-4:0] one_loop2; gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] ( `ifdef USE_POWER_PINS @@ -1366,9 +1365,9 @@ module caravel ( .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), - .mgmt_gpio_oeb(one_loop2), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), - .one(one_loop2), + .one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), .zero(), // Serial data chain for pad configuration diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 8ae69d11..6d2b3d07 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -61,6 +61,7 @@ module chip_io( // Chip Core Interface input porb_h, input por, + input vccd_const_one, output resetb_core_h, output clock_core, input gpio_out_core, @@ -97,6 +98,8 @@ module chip_io( input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol, input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm, output [`MPRJ_IO_PADS-1:0] mprj_io_in, + // Loopbacks to constant value 1 in the 1.8V domain + input [`MPRJ_IO_PADS-1:0] mprj_io_one, // User project direct access to gpio pad connections for analog // (all but the lowest-numbered 7 pads) inout [`MPRJ_IO_PADS-10:0] mprj_analog_io @@ -274,18 +277,18 @@ module chip_io( {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; // Management clock input pad - `INPUT_PAD(clock, clock_core); + `INPUT_PAD(clock, clock_core, vccd_const_one); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one, flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one, flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -293,6 +296,7 @@ module chip_io( // free reset. wire xresloop; + wire xres_vss_loop; sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING @@ -300,16 +304,16 @@ module chip_io( `endif .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h .TIE_HI_ESD(), - .TIE_LO_ESD(), + .TIE_LO_ESD(xres_vss_loop), .PAD_A_ESD_H(xresloop), .XRES_H_N(resetb_core_h), - .DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad - .ENABLE_H(porb_h), // Power-on-reset - .EN_VDDIO_SIG_H(vssio), // No idea. - .INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input - .FILT_IN_H(vssio), // Alternate input for glitch filter - .PULLUP_H(vssio), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd) + .DISABLE_PULLUP_H(xres_vss_loop), // 0 = enable pull-up on reset pad + .ENABLE_H(porb_h), // Power-on-reset + .EN_VDDIO_SIG_H(xres_vss_loop), // No idea. + .INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input + .FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter + .PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input + .ENABLE_VDDIO(vccd_const_one) ); // Corner cells (These are overlay cells; it is not clear what is normally @@ -378,6 +382,7 @@ module chip_io( .analog_a(analog_a), .analog_b(analog_b), .porb_h(porb_h), + .vccd_conb(mprj_io_one), .io(mprj_io), .io_out(mprj_io_out), .oeb(mprj_io_oeb), diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v index 0ea1fafa..b99afbac 100644 --- a/verilog/rtl/chip_io_alt.v +++ b/verilog/rtl/chip_io_alt.v @@ -116,6 +116,7 @@ module chip_io_alt #( input [(`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2)*3-1:0] mprj_io_dm, output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in, output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in_3v3, + input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_one, // User project direct access to gpio pad connections for analog // "analog" connects to the "esd_0" pin of the GPIO pad, and @@ -344,17 +345,17 @@ module chip_io_alt #( {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; // Management clock input pad - `INPUT_PAD(clock, clock_core); + `INPUT_PAD(clock, clock_core, vccd_const_one); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one, flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one, flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -362,6 +363,7 @@ module chip_io_alt #( // free reset. wire xresloop; + wire xres_zero_loop sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING @@ -369,16 +371,16 @@ module chip_io_alt #( `endif .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h .TIE_HI_ESD(), - .TIE_LO_ESD(), + .TIE_LO_ESD(xres_zero_loop), .PAD_A_ESD_H(xresloop), .XRES_H_N(resetb_core_h), - .DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad - .ENABLE_H(porb_h), // Power-on-reset - .EN_VDDIO_SIG_H(vssio), // No idea. - .INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input - .FILT_IN_H(vssio), // Alternate input for glitch filter - .PULLUP_H(vssio), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd) + .DISABLE_PULLUP_H(xres_zero_loop), // 0 = enable pull-up on reset pad + .ENABLE_H(porb_h), // Power-on-reset + .EN_VDDIO_SIG_H(xres_zero_loop), // No idea. + .INP_SEL_H(xres_zero_loop), // 1 = use filt_in_h else filter the pad input + .FILT_IN_H(xres_zero_loop), // Alternate input for glitch filter + .PULLUP_H(xres_zero_loop), // Pullup connection for alternate filter input + .ENABLE_VDDIO(vccd_const_one) ); // Corner cells (These are overlay cells; it is not clear what is normally @@ -451,6 +453,7 @@ module chip_io_alt #( .analog_a(analog_a), .analog_b(analog_b), .porb_h(porb_h), + .vccd_conb(mprj_io_one), .io({mprj_io[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS_1+ANALOG_PADS_2], mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}), diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v index ec4fdf99..f76cfc7a 100644 --- a/verilog/rtl/mprj_io.v +++ b/verilog/rtl/mprj_io.v @@ -44,6 +44,7 @@ module mprj_io #( input analog_a, input analog_b, input porb_h, + input [TOTAL_PADS-1:0] vccd_conb, inout [TOTAL_PADS-1:0] io, input [TOTAL_PADS-1:0] io_out, input [TOTAL_PADS-1:0] oeb, @@ -79,8 +80,8 @@ module mprj_io #( .ENABLE_H(enh[AREA1PADS - 1:0]), .ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]), .ENABLE_VDDA_H(porb_h), - .ENABLE_VSWITCH_H(vssio), - .ENABLE_VDDIO(vccd), + .ENABLE_VSWITCH_H(loop1_io[AREA1PADS - 1:0]), + .ENABLE_VDDIO(vccd_conb[AREA1PADS - 1:0]), .INP_DIS(inp_dis[AREA1PADS - 1:0]), .IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]), .VTRIP_SEL(vtrip_sel[AREA1PADS - 1:0]), @@ -110,8 +111,8 @@ module mprj_io #( .ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_VDDA_H(porb_h), - .ENABLE_VSWITCH_H(vssio), - .ENABLE_VDDIO(vccd), + .ENABLE_VSWITCH_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]), + .ENABLE_VDDIO(vccd_conb[TOTAL_PADS - 1:AREA1PADS]), .INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]), .IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]), .VTRIP_SEL(vtrip_sel[TOTAL_PADS - 1:AREA1PADS]), diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index 86e0be5d..3a09e243 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -73,40 +73,42 @@ .SRC_BDY_LVC1(L1), \ .SRC_BDY_LVC2(L2) -`define INPUT_PAD(X,Y) \ - wire loop_``X; \ +`define INPUT_PAD(X,Y,CONB_ONE) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ .PAD(X), \ `endif \ - .OUT(vssd), \ - .OE_N(vccd), \ - .HLD_H_N(vddio), \ + .OUT(loop_zero_``X), \ + .OE_N(CONB_ONE), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(por), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ - .DM({vssd, vssd, vccd}), \ + .IB_MODE_SEL(loop_zero_``X), \ + .VTRIP_SEL(loop_zero_``X), \ + .SLOW(loop_zero_``X), \ + .HLD_OVR(loop_zero_``X), \ + .ANALOG_EN(loop_zero_``X), \ + .ANALOG_SEL(loop_zero_``X), \ + .ANALOG_POL(loop_zero_``X), \ + .DM({loop_zero_``X, loop_zero_``X, vccd}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(Y), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X) ) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X) ) -`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \ - wire loop_``X; \ +`define OUTPUT_PAD(X,Y,CONB_ONE,INPUT_DIS,OUT_EN_N) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ @@ -114,31 +116,32 @@ `endif \ .OUT(Y), \ .OE_N(OUT_EN_N), \ - .HLD_H_N(vddio), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ - .DM({vccd, vccd, vssd}), \ + .IB_MODE_SEL(loop_zero_``X), \ + .VTRIP_SEL(loop_zero_``X), \ + .SLOW(loop_zero_``X), \ + .HLD_OVR(loop_zero_``X), \ + .ANALOG_EN(loop_zero_``X), \ + .ANALOG_SEL(loop_zero_``X), \ + .ANALOG_POL(loop_zero_``X), \ + .DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X)) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X)) -`define OUTPUT_NO_INP_DIS_PAD(X,Y,OUT_EN_N) \ - wire loop_``X; \ +`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,OUT_EN_N) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ @@ -146,31 +149,32 @@ `endif \ .OUT(Y), \ .OE_N(OUT_EN_N), \ - .HLD_H_N(vddio), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ - .INP_DIS(loop_``X), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ - .DM({vccd, vccd, vssd}), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ + .INP_DIS(loop_zero_``X), \ + .IB_MODE_SEL(loop_zero_``X), \ + .VTRIP_SEL(loop_zero_``X), \ + .SLOW(loop_zero_``X), \ + .HLD_OVR(loop_zero_``X), \ + .ANALOG_EN(loop_zero_``X), \ + .ANALOG_SEL(loop_zero_``X), \ + .ANALOG_POL(loop_zero_``X), \ + .DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X)) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X)) -`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ - wire loop_``X; \ +`define INOUT_PAD(X,Y,CONB_ONE,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ @@ -178,27 +182,27 @@ `endif \ .OUT(Y_OUT), \ .OE_N(OUT_EN_N), \ - .HLD_H_N(vddio), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ + .IB_MODE_SEL(loop_zero_``X), \ + .VTRIP_SEL(loop_zero_``X), \ + .SLOW(loop_zero_``X), \ + .HLD_OVR(loop_zero_``X), \ + .ANALOG_EN(loop_zero_``X), \ + .ANALOG_SEL(loop_zero_``X), \ + .ANALOG_POL(loop_zero_``X), \ .DM(MODE), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(Y), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X) ) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X) ) // `default_nettype wire From 3962b061f65fdf9c8d14195b902e1662900920d3 Mon Sep 17 00:00:00 2001 From: RTimothyEdwards Date: Tue, 20 Sep 2022 20:04:12 +0000 Subject: [PATCH 02/22] Apply automatic changes to Manifest and README.rst --- manifest | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/manifest b/manifest index af5987a9..839725da 100644 --- a/manifest +++ b/manifest @@ -2,14 +2,14 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -6576abded424d948d2a7e71c2b4a4df1eda77238 verilog/rtl/caravan.v +670031aa4d92dbf15054b698f859b01d35143aa9 verilog/rtl/caravan.v a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v +22c9fc7c6e9dccd4c8511d9d6ec63765dfaedf3a verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v -d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v -54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v +a0b12a4769db4cfa0cd340194af3429d3daedb51 verilog/rtl/chip_io.v +2b0bbaa63039534db811c82d808e885a1b9c20e3 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v @@ -21,9 +21,9 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v 9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v -9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v +d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v -6f490c83d6064c380a3f475823ef97f325d7f6c1 verilog/rtl/pads.v +770d418646d4f4f37a08b5de8308d33eafd7bde9 verilog/rtl/pads.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v 1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v From e1e23857ff766c114abb56539b9c04634f46caba Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 13:56:50 -0700 Subject: [PATCH 03/22] remove spare logic blocks in top level --- verilog/rtl/caravan.v | 3 +++ verilog/rtl/caravel.v | 2 ++ 2 files changed, 5 insertions(+) diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 6834a533..642a1e2c 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -1376,6 +1376,7 @@ module caravan ( .X(rstb_l) ); + `ifdef USE_SPARE_LOGIC // Spare logic for metal mask fixes wire [107:0] spare_xz_nc; wire [15:0] spare_xi_nc; @@ -1400,6 +1401,8 @@ module caravan ( .spare_xfq(spare_xfq_nc), .spare_xfqn(spare_xfqn_nc) ); + `endif + endmodule // `default_nettype wire diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 706cb21a..12f40581 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -1430,6 +1430,7 @@ module caravel ( .X(rstb_l) ); + `ifdef USE_SPARE_LOGIC // Spare logic for metal mask fixes wire [107:0] spare_xz_nc; wire [15:0] spare_xi_nc; @@ -1454,6 +1455,7 @@ module caravel ( .spare_xfq(spare_xfq_nc), .spare_xfqn(spare_xfqn_nc) ); + `endif endmodule // `default_nettype wire From e1d5dd75fec56548294eb922186869eca450fb49 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 20:57:55 +0000 Subject: [PATCH 04/22] Apply automatic changes to Manifest and README.rst --- manifest | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/manifest b/manifest index af5987a9..1e4e5dfe 100644 --- a/manifest +++ b/manifest @@ -2,10 +2,10 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -6576abded424d948d2a7e71c2b4a4df1eda77238 verilog/rtl/caravan.v +f2412513d519d07586462951e8458d6c52b9e901 verilog/rtl/caravan.v a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v +894ca71fbbf78411beb9a37060a70703bf0bc1e7 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v From 3f3c3db09940fe0e29cee4c2d4ad4d85c57b3115 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 14:41:43 -0700 Subject: [PATCH 05/22] update for dv simulations for mgmt core --- Makefile | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 73 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 2e7ea7d5..9a07a4d0 100644 --- a/Makefile +++ b/Makefile @@ -44,7 +44,7 @@ LARGE_FILES_GZ_SPLIT += $(addsuffix .00.split, $(ARCHIVES)) MCW_ROOT?=$(PWD)/mgmt_core_wrapper MCW ?=LITEX_VEXRISCV -MPW_TAG ?= mpw-5e +MPW_TAG ?= caravel_stanford # PDK switch varient export PDK?=sky130A @@ -201,15 +201,82 @@ clean: cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \ $(MAKE) -j$(THREADS) clean +######### +## Verify + + +#.PHONY: verify +#verify: +# cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \ +# $(MAKE) -j$(THREADS) all +# cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \ +# $(MAKE) -j$(THREADS) all + +.PHONY: simenv +simenv: + docker pull efabless/dv:latest + +dv_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-caravel && find * -maxdepth 0 -type d) +dv-targets-rtl=$(dv_patterns:%=verify-%-rtl) +dv-targets-gl=$(dv_patterns:%=verify-%-gl) +dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf) + +TARGET_PATH=$(shell pwd) +verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-caravel/$* && export SIM=${SIM} && make" +dv_base_dependencies=simenv +docker_run_verify=\ + docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ + -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ + -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ + -e CARAVEL_ROOT=${CARAVEL_ROOT} \ + -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \ + -e DESIGNS=$(TARGET_PATH) \ + -e PDK=$(PDK) \ + -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ + -e MCW_ROOT=$(MCW_ROOT) \ + -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \ + sh -c $(verify_command) + +.PHONY: harden +harden: $(blocks) .PHONY: verify -verify: - cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \ - $(MAKE) -j$(THREADS) all - cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \ - $(MAKE) -j$(THREADS) all +verify: $(dv-targets-rtl) +.PHONY: verify-all-rtl +verify-all-rtl: $(dv-targets-rtl) +.PHONY: verify-all-gl +verify-all-gl: $(dv-targets-gl) + +.PHONY: verify-all-gl-sdf +verify-all-gl-sdf: $(dv-targets-gl-sdf) + +$(dv-targets-rtl): SIM=RTL +$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies) + $(docker_run_verify) + +$(dv-targets-gl): SIM=GL +$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies) + $(docker_run_verify) + +$(dv-targets-gl-sdf): SIM=GL_SDF +$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) + $(docker_run_verify) + +clean-targets=$(blocks:%=clean-%) +.PHONY: $(clean-targets) +$(clean-targets): clean-% : + rm -f ./verilog/gl/$*.v + rm -f ./spef/$*.spef + rm -f ./sdc/$*.sdc + rm -f ./sdf/$*.sdf + rm -f ./gds/$*.gds + rm -f ./mag/$*.mag + rm -f ./lef/$*.lef + rm -f ./maglef/*.maglef + +############### ##### $(LARGE_FILES_GZ): %.$(ARCHIVE_EXT): % From 66fc0c6a066ab2d2bbc0d9937a3a58b0a703e472 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 20 Sep 2022 17:49:08 -0400 Subject: [PATCH 06/22] Modified the GPIO control block to buffer the constant high/low outputs. Corrected the pad constant connections to all be in the correct domain (1.8V or 3.3V). Created a new "constant_block" module that generates a single constant 1 and 0 value in the 1.8V domain, and used 7 of these in the chip_io (and chip_io_alt) modules to create the 1.8V domain constant signals for the seven pads belonging to the management (clock, reset, flash SPI, and management GPIO). --- verilog/rtl/caravan.v | 4 -- verilog/rtl/caravan_netlists.v | 2 + verilog/rtl/caravel.v | 2 - verilog/rtl/caravel_netlists.v | 10 +++++ verilog/rtl/chip_io.v | 25 +++++++---- verilog/rtl/chip_io_alt.v | 24 +++++++--- verilog/rtl/constant_block.v | 77 ++++++++++++++++++++++++++++++++ verilog/rtl/gpio_control_block.v | 36 +++++++++++++-- verilog/rtl/pads.v | 74 +++++++++++++++--------------- 9 files changed, 192 insertions(+), 62 deletions(-) create mode 100644 verilog/rtl/constant_block.v diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 5e9c6189..dcf4a9dc 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -292,10 +292,6 @@ module caravan ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - - // Connect 1.8V constant one to nearest GPIO control block - .vccd_const_one(mprj_io_one[`MPRJ_IO_PADS-`ANALOG_PADS-1]), - .gpio(gpio), .mprj_io(mprj_io), .clock(clock), diff --git a/verilog/rtl/caravan_netlists.v b/verilog/rtl/caravan_netlists.v index 8dc8a7eb..488fda46 100644 --- a/verilog/rtl/caravan_netlists.v +++ b/verilog/rtl/caravan_netlists.v @@ -58,6 +58,7 @@ `include "gl/mprj2_logic_high.v" `include "gl/mgmt_protect.v" `include "gl/mgmt_protect_hv.v" + `include "gl/constant_block.v" `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" @@ -83,6 +84,7 @@ `include "mprj2_logic_high.v" `include "mgmt_protect.v" `include "mgmt_protect_hv.v" + `include "constant_block.v" `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 5ee33bdc..315fbc30 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -253,8 +253,6 @@ module caravel ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - // Connect 1.8V constant one to nearest GPIO control block - .vccd_const_one(mprj_io_one[`MPRJ_IO_PADS-1]), .gpio(gpio), .mprj_io(mprj_io), .clock(clock), diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index c967700e..2a6d2d0a 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -56,6 +56,7 @@ `include "gl/mprj2_logic_high.v" `include "gl/mgmt_protect.v" `include "gl/mgmt_protect_hv.v" + `include "gl/constant_block.v" `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" @@ -65,6 +66,10 @@ `include "gl/spare_logic_block.v" `include "gl/mgmt_defines.v" `include "gl/mgmt_core_wrapper.v" + `include "gl/mgmt_core.v" + `include "gl/DFFRAM.v" + `include "gl/DFFRAMBB.v" + `include "gl/VexRiscv_LiteDebug.v" `include "gl/caravel.v" `else `include "digital_pll.v" @@ -81,12 +86,17 @@ `include "mprj2_logic_high.v" `include "mgmt_protect.v" `include "mgmt_protect_hv.v" + `include "constant_block.v" `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" `include "xres_buf.v" `include "spare_logic_block.v" `include "mgmt_core_wrapper.v" + `include "mgmt_core.v" + `include "DFFRAM.v" + `include "DFFRAMBB.v" + `include "VexRiscv_LiteDebug.v" `include "caravel.v" `endif diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 6d2b3d07..88087745 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -61,7 +61,6 @@ module chip_io( // Chip Core Interface input porb_h, input por, - input vccd_const_one, output resetb_core_h, output clock_core, input gpio_out_core, @@ -277,18 +276,28 @@ module chip_io( {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; // Management clock input pad - `INPUT_PAD(clock, clock_core, vccd_const_one); + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); + + wire [6:0] vccd_const_one; // Constant value for management pins + wire [6:0] vssd_const_zero; // Constant value for management pins + + constant_block constant_value_inst [6:0] ( + .vccd(vccd), + .vssd(vssd), + .one(vccd_const_one), + .zero(vssd_const_zero) + ); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, vccd_const_one, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -313,7 +322,7 @@ module chip_io( .INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input .FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter .PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd_const_one) + .ENABLE_VDDIO(vccd_const_one[6]) ); // Corner cells (These are overlay cells; it is not clear what is normally diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v index b99afbac..3b74b35d 100644 --- a/verilog/rtl/chip_io_alt.v +++ b/verilog/rtl/chip_io_alt.v @@ -344,18 +344,28 @@ module chip_io_alt #( wire[2:0] flash_io1_mode = {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; + wire [6:0] vccd_const_one; // Constant value for management pins + wire [6:0] vssd_const_zero; // Constant value for management pins + + constant_block constant_value_inst [6:0] ( + .vccd(vccd), + .vssd(vssd), + .one(vccd_const_one), + .zero(vssd_const_zero) + ); + // Management clock input pad - `INPUT_PAD(clock, clock_core, vccd_const_one); + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, vccd_const_one, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -380,7 +390,7 @@ module chip_io_alt #( .INP_SEL_H(xres_zero_loop), // 1 = use filt_in_h else filter the pad input .FILT_IN_H(xres_zero_loop), // Alternate input for glitch filter .PULLUP_H(xres_zero_loop), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd_const_one) + .ENABLE_VDDIO(vccd_const_one[6]) ); // Corner cells (These are overlay cells; it is not clear what is normally diff --git a/verilog/rtl/constant_block.v b/verilog/rtl/constant_block.v new file mode 100644 index 00000000..d6a03b3e --- /dev/null +++ b/verilog/rtl/constant_block.v @@ -0,0 +1,77 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *--------------------------------------------------------------------- + * A simple module that generates buffered high and low outputs + * in the 1.8V domain. + *--------------------------------------------------------------------- + */ + +module constant_block ( + `ifdef USE_POWER_PINS + inout vccd, + inout vssd, + `endif + + output one, + output zero +); + + wire one_unbuf; + wire zero_unbuf; + + sky130_fd_sc_hd__conb_1 const_source ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .HI(one_unbuf), + .LO(zero_unbuf) + ); + + /* Buffer the constant outputs (could be synthesized) */ + /* NOTE: Constant cell HI, LO outputs are connected to power */ + /* rails through an approximately 120 ohm resistor, which is not */ + /* enough to drive inputs in the I/O cells while ensuring ESD */ + /* requirements, without buffering. */ + + sky130_fd_sc_hd__buf_16 const_one_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(one_unbuf), + .X(one) + ); + + sky130_fd_sc_hd__buf_16 const_zero_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(zero_unbuf), + .X(zero) + ); + +endmodule +`default_nettype wire diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index 5bfdd24d..3a0d6ea9 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -135,8 +135,8 @@ module gpio_control_block #( wire pad_gpio_outenb; wire pad_gpio_out; wire pad_gpio_in; - wire one; - wire zero; + wire one_unbuf; + wire zero_unbuf; wire user_gpio_in; wire gpio_in_unbuf; @@ -280,8 +280,36 @@ module gpio_control_block #( .VPB(vccd), .VNB(vssd), `endif - .HI(one), - .LO(zero) + .HI(one_unbuf), + .LO(zero_unbuf) + ); + + /* Buffer the constant outputs (could be synthesized) */ + /* NOTE: Constant cell HI, LO outputs are connected to power */ + /* rails through an approximately 120 ohm resistor, which is not */ + /* enough to drive inputs in the I/O cells while ensuring ESD */ + /* requirements, without buffering. */ + + sky130_fd_sc_hd__buf_8 const_one_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(one_unbuf), + .X(one) + ); + + sky130_fd_sc_hd__buf_8 const_zero_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(zero_unbuf), + .X(zero) ); endmodule diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index 3a09e243..623fc818 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -73,7 +73,7 @@ .SRC_BDY_LVC1(L1), \ .SRC_BDY_LVC2(L2) -`define INPUT_PAD(X,Y,CONB_ONE) \ +`define INPUT_PAD(X,Y,CONB_ONE,CONB_ZERO) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -81,7 +81,7 @@ `ifndef TOP_ROUTING \ .PAD(X), \ `endif \ - .OUT(loop_zero_``X), \ + .OUT(CONB_ZERO), \ .OE_N(CONB_ONE), \ .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ @@ -90,14 +90,14 @@ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(por), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ - .DM({loop_zero_``X, loop_zero_``X, vccd}), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ZERO, CONB_ZERO, CONB_ONE}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ @@ -106,7 +106,7 @@ .TIE_HI_ESD(loop_one_``X), \ .TIE_LO_ESD(loop_zero_``X) ) -`define OUTPUT_PAD(X,Y,CONB_ONE,INPUT_DIS,OUT_EN_N) \ +`define OUTPUT_PAD(X,Y,CONB_ONE,CONB_ZERO,INPUT_DIS,OUT_EN_N) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -123,14 +123,14 @@ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ - .DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ @@ -139,7 +139,7 @@ .TIE_HI_ESD(loop_one_``X), \ .TIE_LO_ESD(loop_zero_``X)) -`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,OUT_EN_N) \ +`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,CONB_ZERO,OUT_EN_N) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -155,15 +155,15 @@ .ENABLE_VDDA_H(porb_h), \ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ - .INP_DIS(loop_zero_``X), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ - .DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \ + .INP_DIS(CONB_ZERO), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ @@ -172,7 +172,7 @@ .TIE_HI_ESD(loop_one_``X), \ .TIE_LO_ESD(loop_zero_``X)) -`define INOUT_PAD(X,Y,CONB_ONE,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ +`define INOUT_PAD(X,Y,CONB_ONE,CONB_ZERO,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ wire loop_zero_``X; \ wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ @@ -189,13 +189,13 @@ .ENABLE_VSWITCH_H(loop_zero_``X), \ .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(loop_zero_``X), \ - .VTRIP_SEL(loop_zero_``X), \ - .SLOW(loop_zero_``X), \ - .HLD_OVR(loop_zero_``X), \ - .ANALOG_EN(loop_zero_``X), \ - .ANALOG_SEL(loop_zero_``X), \ - .ANALOG_POL(loop_zero_``X), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ .DM(MODE), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ From b9a819634d5798ed8b2091e444b765fe5d4ceb7e Mon Sep 17 00:00:00 2001 From: RTimothyEdwards Date: Tue, 20 Sep 2022 21:56:37 +0000 Subject: [PATCH 07/22] Apply automatic changes to Manifest and README.rst --- manifest | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/manifest b/manifest index 839725da..7c568469 100644 --- a/manifest +++ b/manifest @@ -2,18 +2,19 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -670031aa4d92dbf15054b698f859b01d35143aa9 verilog/rtl/caravan.v -a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v +a349dd3c5fae352a0a89131bf65018650944977f verilog/rtl/caravan.v +a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -22c9fc7c6e9dccd4c8511d9d6ec63765dfaedf3a verilog/rtl/caravel.v +bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v -a0b12a4769db4cfa0cd340194af3429d3daedb51 verilog/rtl/chip_io.v -2b0bbaa63039534db811c82d808e885a1b9c20e3 verilog/rtl/chip_io_alt.v +cc983a39219a9211a3e360b77d3ba6e7e8f6bea8 verilog/rtl/chip_io.v +8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v +941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v -41f899d8a8510f933e08e41d1b4ac13d84191f38 verilog/rtl/gpio_control_block.v +6e1277baf7702168702ee5d4e373180c7d0b4631 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v 5469b880904d6dd5d1eba6f026b3582810df412c verilog/rtl/housekeeping.v @@ -23,7 +24,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v -770d418646d4f4f37a08b5de8308d33eafd7bde9 verilog/rtl/pads.v +4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v 1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v From 2606285b8c0c9b9ea5516aa338b36f8b8e4f5d29 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 20 Sep 2022 18:23:32 -0400 Subject: [PATCH 08/22] Flipped some lines where a wire was used before it was declared. --- verilog/rtl/chip_io.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 88087745..7aafd2db 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -275,9 +275,6 @@ module chip_io( wire[2:0] flash_io1_mode = {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; - // Management clock input pad - `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); - wire [6:0] vccd_const_one; // Constant value for management pins wire [6:0] vssd_const_zero; // Constant value for management pins @@ -288,6 +285,9 @@ module chip_io( .zero(vssd_const_zero) ); + // Management clock input pad + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); + // Management GPIO pad `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); From 19a7b303e9405422a14fbdda321b9c52493f613a Mon Sep 17 00:00:00 2001 From: RTimothyEdwards Date: Tue, 20 Sep 2022 22:25:10 +0000 Subject: [PATCH 09/22] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index 7c568469..6df8fb5e 100644 --- a/manifest +++ b/manifest @@ -8,7 +8,7 @@ a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v -cc983a39219a9211a3e360b77d3ba6e7e8f6bea8 verilog/rtl/chip_io.v +fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v 8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v From fdbe22567460bc6a3cc5a4e9c30100811e235996 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 15:31:51 -0700 Subject: [PATCH 10/22] update for dv simulations for mgmt core --- Makefile | 55 +++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index 9a07a4d0..9dfc59f5 100644 --- a/Makefile +++ b/Makefile @@ -216,13 +216,17 @@ clean: simenv: docker pull efabless/dv:latest -dv_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-caravel && find * -maxdepth 0 -type d) -dv-targets-rtl=$(dv_patterns:%=verify-%-rtl) -dv-targets-gl=$(dv_patterns:%=verify-%-gl) -dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf) +dv_caravel_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-caravel && find * -maxdepth 0 -type d) +dv_standalone_patterns+=$(shell cd mgmt_core_wrapper/verilog/dv/tests-standalone && find * -maxdepth 0 -type d) +dv-caravel-targets-rtl=$(dv_caravel_patterns:%=verify-%-rtl) +dv-standalone-targets-rtl=$(dv_standalone_patterns:%=verify-%-rtl) +dv-caravel-targets-gl=$(dv_caravel_patterns:%=verify-%-gl) +dv-standalone-targets-gl=$(dv_standalone_patterns:%=verify-%-gl) +dv-caravel-targets-gl-sdf=$(dv_caravel_patterns:%=verify-%-gl-sdf) +dv-standalone-targets-gl-sdf=$(dv_standalone_patterns:%=verify-%-gl-sdf) TARGET_PATH=$(shell pwd) -verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-caravel/$* && export SIM=${SIM} && make" +verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-${CONFIG}/$* && export SIM=${SIM} && make" dv_base_dependencies=simenv docker_run_verify=\ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ @@ -241,27 +245,42 @@ docker_run_verify=\ harden: $(blocks) .PHONY: verify -verify: $(dv-targets-rtl) +verify: $(dv-caravel-targets-rtl) -.PHONY: verify-all-rtl -verify-all-rtl: $(dv-targets-rtl) +.PHONY: verify-caravel-all-rtl verify-standalone-all-rtl +verify-caravel-all-rtl: $(dv-caravel-targets-rtl) +verify-standalone-all-rtl: $(dv-standalone-targets-rtl) -.PHONY: verify-all-gl -verify-all-gl: $(dv-targets-gl) +.PHONY: verify-caravel-all-gl verify-standalone-all-gl +verify-caravel-all-gl: $(dv-caravel-targets-gl) +verify-standalone-all-gl: $(dv-standalone-targets-gl) -.PHONY: verify-all-gl-sdf -verify-all-gl-sdf: $(dv-targets-gl-sdf) +.PHONY: verify-caravel-all-gl-sdf verify-standalone-all-gl-sdf +verify-caravel-all-gl-sdf: $(dv-targets-gl-sdf) +verify-standalone-all-gl-sdf: $(dv-targets-gl-sdf) -$(dv-targets-rtl): SIM=RTL -$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies) +$(dv-caravel-targets-rtl): SIM=RTL CONFIG=caravel +$(dv-caravel-targets-rtl): verify-%-rtl: $(dv_base_dependencies) $(docker_run_verify) -$(dv-targets-gl): SIM=GL -$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies) +$(dv-caravel-targets-gl): SIM=GL CONFIG=caravel +$(dv-caravel-targets-gl): verify-%-gl: $(dv_base_dependencies) $(docker_run_verify) -$(dv-targets-gl-sdf): SIM=GL_SDF -$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) +$(dv-caravel-targets-gl-sdf): SIM=GL_SDF CONFIG=caravel +$(dv-caravel-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) + $(docker_run_verify) + +$(dv-standalone-targets-rtl): SIM=RTL CONFIG=standalone +$(dv-standalone-targets-rtl): verify-%-rtl: $(dv_base_dependencies) + $(docker_run_verify) + +$(dv-standalone-targets-gl): SIM=GL CONFIG=standalone +$(dv-standalone-targets-gl): verify-%-gl: $(dv_base_dependencies) + $(docker_run_verify) + +$(dv-standalone-targets-gl-sdf): SIM=GL_SDF CONFIG=standalone +$(dv-standalone-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) $(docker_run_verify) clean-targets=$(blocks:%=clean-%) From a04966d62d00f0e3c1e99bab71ba498da71d59fe Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 16:36:00 -0700 Subject: [PATCH 11/22] update for dv simulations for mgmt core --- Makefile | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 9dfc59f5..a8400c0e 100644 --- a/Makefile +++ b/Makefile @@ -259,27 +259,33 @@ verify-standalone-all-gl: $(dv-standalone-targets-gl) verify-caravel-all-gl-sdf: $(dv-targets-gl-sdf) verify-standalone-all-gl-sdf: $(dv-targets-gl-sdf) -$(dv-caravel-targets-rtl): SIM=RTL CONFIG=caravel +$(dv-caravel-targets-rtl): SIM=RTL +$(dv-caravel-targets-rtl): CONFIG=caravel $(dv-caravel-targets-rtl): verify-%-rtl: $(dv_base_dependencies) $(docker_run_verify) -$(dv-caravel-targets-gl): SIM=GL CONFIG=caravel +$(dv-caravel-targets-gl): SIM=GL +$(dv-caravel-targets-gl): CONFIG=caravel $(dv-caravel-targets-gl): verify-%-gl: $(dv_base_dependencies) $(docker_run_verify) -$(dv-caravel-targets-gl-sdf): SIM=GL_SDF CONFIG=caravel +$(dv-caravel-targets-gl-sdf): SIM=GL_SDF +$(dv-caravel-targets-gl-sdf): CONFIG=caravel $(dv-caravel-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) $(docker_run_verify) -$(dv-standalone-targets-rtl): SIM=RTL CONFIG=standalone +$(dv-standalone-targets-rtl): SIM=RTL +$(dv-standalone-targets-rtl): CONFIG=standalone $(dv-standalone-targets-rtl): verify-%-rtl: $(dv_base_dependencies) $(docker_run_verify) -$(dv-standalone-targets-gl): SIM=GL CONFIG=standalone +$(dv-standalone-targets-gl): SIM=GL +$(dv-standalone-targets-gl): CONFIG=standalone $(dv-standalone-targets-gl): verify-%-gl: $(dv_base_dependencies) $(docker_run_verify) -$(dv-standalone-targets-gl-sdf): SIM=GL_SDF CONFIG=standalone +$(dv-standalone-targets-gl-sdf): SIM=GL_SDF +$(dv-standalone-targets-gl-sdf): CONFIG=standalone $(dv-standalone-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) $(docker_run_verify) From 85847dfe0522b37060f4880a9dd2094e96962f45 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 16:49:20 -0700 Subject: [PATCH 12/22] update for dv simulations for mgmt core --- Makefile | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index a8400c0e..4d0acf87 100644 --- a/Makefile +++ b/Makefile @@ -218,12 +218,12 @@ simenv: dv_caravel_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-caravel && find * -maxdepth 0 -type d) dv_standalone_patterns+=$(shell cd mgmt_core_wrapper/verilog/dv/tests-standalone && find * -maxdepth 0 -type d) -dv-caravel-targets-rtl=$(dv_caravel_patterns:%=verify-%-rtl) -dv-standalone-targets-rtl=$(dv_standalone_patterns:%=verify-%-rtl) -dv-caravel-targets-gl=$(dv_caravel_patterns:%=verify-%-gl) -dv-standalone-targets-gl=$(dv_standalone_patterns:%=verify-%-gl) -dv-caravel-targets-gl-sdf=$(dv_caravel_patterns:%=verify-%-gl-sdf) -dv-standalone-targets-gl-sdf=$(dv_standalone_patterns:%=verify-%-gl-sdf) +dv-caravel-targets-rtl=$(dv_caravel_patterns:%=verify-caravel-%-rtl) +dv-standalone-targets-rtl=$(dv_standalone_patterns:%=verify-standalone-%-rtl) +dv-caravel-targets-gl=$(dv_caravel_patterns:%=verify-caravel-%-gl) +dv-standalone-targets-gl=$(dv_standalone_patterns:%=verify-standalone-%-gl) +dv-caravel-targets-gl-sdf=$(dv_caravel_patterns:%=verify-caravel-%-gl-sdf) +dv-standalone-targets-gl-sdf=$(dv_standalone_patterns:%=verify-standalone-%-gl-sdf) TARGET_PATH=$(shell pwd) verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-${CONFIG}/$* && export SIM=${SIM} && make" @@ -261,32 +261,32 @@ verify-standalone-all-gl-sdf: $(dv-targets-gl-sdf) $(dv-caravel-targets-rtl): SIM=RTL $(dv-caravel-targets-rtl): CONFIG=caravel -$(dv-caravel-targets-rtl): verify-%-rtl: $(dv_base_dependencies) +$(dv-caravel-targets-rtl): verify-caravel-%-rtl: $(dv_base_dependencies) $(docker_run_verify) $(dv-caravel-targets-gl): SIM=GL $(dv-caravel-targets-gl): CONFIG=caravel -$(dv-caravel-targets-gl): verify-%-gl: $(dv_base_dependencies) +$(dv-caravel-targets-gl): verify-caravel-%-gl: $(dv_base_dependencies) $(docker_run_verify) $(dv-caravel-targets-gl-sdf): SIM=GL_SDF $(dv-caravel-targets-gl-sdf): CONFIG=caravel -$(dv-caravel-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) +$(dv-caravel-targets-gl-sdf): verify-caravel-%-gl-sdf: $(dv_base_dependencies) $(docker_run_verify) $(dv-standalone-targets-rtl): SIM=RTL $(dv-standalone-targets-rtl): CONFIG=standalone -$(dv-standalone-targets-rtl): verify-%-rtl: $(dv_base_dependencies) +$(dv-standalone-targets-rtl): verify-standalone-%-rtl: $(dv_base_dependencies) $(docker_run_verify) $(dv-standalone-targets-gl): SIM=GL $(dv-standalone-targets-gl): CONFIG=standalone -$(dv-standalone-targets-gl): verify-%-gl: $(dv_base_dependencies) +$(dv-standalone-targets-gl): verify-standalone-%-gl: $(dv_base_dependencies) $(docker_run_verify) $(dv-standalone-targets-gl-sdf): SIM=GL_SDF $(dv-standalone-targets-gl-sdf): CONFIG=standalone -$(dv-standalone-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) +$(dv-standalone-targets-gl-sdf): verify-standalone-%-gl-sdf: $(dv_base_dependencies) $(docker_run_verify) clean-targets=$(blocks:%=clean-%) From 3fd3107cae94c16c6d924d7dec3d5503094b4ab4 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 17:44:50 -0700 Subject: [PATCH 13/22] add log for verify simulation output --- Makefile | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 4d0acf87..2e7e22dd 100644 --- a/Makefile +++ b/Makefile @@ -225,6 +225,8 @@ dv-standalone-targets-gl=$(dv_standalone_patterns:%=verify-standalone-%-gl) dv-caravel-targets-gl-sdf=$(dv_caravel_patterns:%=verify-caravel-%-gl-sdf) dv-standalone-targets-gl-sdf=$(dv_standalone_patterns:%=verify-standalone-%-gl-sdf) +VERIFY_LOG = "verify-${CONFIG}-${SIM}.log" + TARGET_PATH=$(shell pwd) verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-${CONFIG}/$* && export SIM=${SIM} && make" dv_base_dependencies=simenv @@ -239,7 +241,7 @@ docker_run_verify=\ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ -e MCW_ROOT=$(MCW_ROOT) \ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \ - sh -c $(verify_command) + sh -c $(verify_command) | tee ${VERIFY_LOG} .PHONY: harden harden: $(blocks) @@ -247,6 +249,11 @@ harden: $(blocks) .PHONY: verify verify: $(dv-caravel-targets-rtl) +verify_log_header: + @echo "*************************************************************************" > ${VERIFY_LOG} + @echo "Verification Log: `date` ${CONFIG} ${SIM}" >> ${VERIFY_LOG} + @echo "*************************************************************************" >> ${VERIFY_LOG} + .PHONY: verify-caravel-all-rtl verify-standalone-all-rtl verify-caravel-all-rtl: $(dv-caravel-targets-rtl) verify-standalone-all-rtl: $(dv-standalone-targets-rtl) @@ -276,7 +283,7 @@ $(dv-caravel-targets-gl-sdf): verify-caravel-%-gl-sdf: $(dv_base_dependencies) $(dv-standalone-targets-rtl): SIM=RTL $(dv-standalone-targets-rtl): CONFIG=standalone -$(dv-standalone-targets-rtl): verify-standalone-%-rtl: $(dv_base_dependencies) +$(dv-standalone-targets-rtl): verify-standalone-%-rtl: $(dv_base_dependencies) verify_log_header $(docker_run_verify) $(dv-standalone-targets-gl): SIM=GL From d8399ae6f51b735053daa1a33a8871930c0945ca Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 18:12:58 -0700 Subject: [PATCH 14/22] add log for verify simulation output --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 2e7e22dd..8694934f 100644 --- a/Makefile +++ b/Makefile @@ -217,7 +217,7 @@ simenv: docker pull efabless/dv:latest dv_caravel_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-caravel && find * -maxdepth 0 -type d) -dv_standalone_patterns+=$(shell cd mgmt_core_wrapper/verilog/dv/tests-standalone && find * -maxdepth 0 -type d) +dv_standalone_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-standalone && find * -maxdepth 0 -type d) dv-caravel-targets-rtl=$(dv_caravel_patterns:%=verify-caravel-%-rtl) dv-standalone-targets-rtl=$(dv_standalone_patterns:%=verify-standalone-%-rtl) dv-caravel-targets-gl=$(dv_caravel_patterns:%=verify-caravel-%-gl) @@ -226,7 +226,6 @@ dv-caravel-targets-gl-sdf=$(dv_caravel_patterns:%=verify-caravel-%-gl-sdf) dv-standalone-targets-gl-sdf=$(dv_standalone_patterns:%=verify-standalone-%-gl-sdf) VERIFY_LOG = "verify-${CONFIG}-${SIM}.log" - TARGET_PATH=$(shell pwd) verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-${CONFIG}/$* && export SIM=${SIM} && make" dv_base_dependencies=simenv @@ -241,7 +240,7 @@ docker_run_verify=\ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ -e MCW_ROOT=$(MCW_ROOT) \ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \ - sh -c $(verify_command) | tee ${VERIFY_LOG} + sh -c $(verify_command) | tee -a ${VERIFY_LOG} .PHONY: harden harden: $(blocks) @@ -249,9 +248,10 @@ harden: $(blocks) .PHONY: verify verify: $(dv-caravel-targets-rtl) +.PHONY: verify_log_header verify_log_header: @echo "*************************************************************************" > ${VERIFY_LOG} - @echo "Verification Log: `date` ${CONFIG} ${SIM}" >> ${VERIFY_LOG} + @echo "Verification Log: `date` Configuration: ${CONFIG} ${SIM}" >> ${VERIFY_LOG} @echo "*************************************************************************" >> ${VERIFY_LOG} .PHONY: verify-caravel-all-rtl verify-standalone-all-rtl From baeb1cc55176e3155617af7783f562f1a88e178c Mon Sep 17 00:00:00 2001 From: jeffdi Date: Tue, 20 Sep 2022 18:27:21 -0700 Subject: [PATCH 15/22] add log for verify simulation output --- Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 8694934f..bd72d873 100644 --- a/Makefile +++ b/Makefile @@ -268,17 +268,17 @@ verify-standalone-all-gl-sdf: $(dv-targets-gl-sdf) $(dv-caravel-targets-rtl): SIM=RTL $(dv-caravel-targets-rtl): CONFIG=caravel -$(dv-caravel-targets-rtl): verify-caravel-%-rtl: $(dv_base_dependencies) +$(dv-caravel-targets-rtl): verify-caravel-%-rtl: $(dv_base_dependencies) verify_log_header $(docker_run_verify) $(dv-caravel-targets-gl): SIM=GL $(dv-caravel-targets-gl): CONFIG=caravel -$(dv-caravel-targets-gl): verify-caravel-%-gl: $(dv_base_dependencies) +$(dv-caravel-targets-gl): verify-caravel-%-gl: $(dv_base_dependencies) verify_log_header $(docker_run_verify) $(dv-caravel-targets-gl-sdf): SIM=GL_SDF $(dv-caravel-targets-gl-sdf): CONFIG=caravel -$(dv-caravel-targets-gl-sdf): verify-caravel-%-gl-sdf: $(dv_base_dependencies) +$(dv-caravel-targets-gl-sdf): verify-caravel-%-gl-sdf: $(dv_base_dependencies) verify_log_header $(docker_run_verify) $(dv-standalone-targets-rtl): SIM=RTL @@ -288,12 +288,12 @@ $(dv-standalone-targets-rtl): verify-standalone-%-rtl: $(dv_base_dependencies) v $(dv-standalone-targets-gl): SIM=GL $(dv-standalone-targets-gl): CONFIG=standalone -$(dv-standalone-targets-gl): verify-standalone-%-gl: $(dv_base_dependencies) +$(dv-standalone-targets-gl): verify-standalone-%-gl: $(dv_base_dependencies) verify_log_header $(docker_run_verify) $(dv-standalone-targets-gl-sdf): SIM=GL_SDF $(dv-standalone-targets-gl-sdf): CONFIG=standalone -$(dv-standalone-targets-gl-sdf): verify-standalone-%-gl-sdf: $(dv_base_dependencies) +$(dv-standalone-targets-gl-sdf): verify-standalone-%-gl-sdf: $(dv_base_dependencies) verify_log_header $(docker_run_verify) clean-targets=$(blocks:%=clean-%) From 74a9f24476120ef1e5b9fe66afacc3c80a3fd24e Mon Sep 17 00:00:00 2001 From: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com> Date: Wed, 21 Sep 2022 10:25:30 -0700 Subject: [PATCH 16/22] Update Makefile update open_pdks commit id --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index bd72d873..b9e2ad1f 100644 --- a/Makefile +++ b/Makefile @@ -86,7 +86,7 @@ SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl IO_LIBRARY ?= sky130_fd_io PRIMITIVES_LIBRARY ?= sky130_fd_pr SKYWATER_COMMIT ?= c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -OPEN_PDKS_COMMIT ?= 05af1d05227419f0955cd98610351f4680575b95 +OPEN_PDKS_COMMIT ?= 8f6aff1881e5feae49acb6d5be53c4acc91bb235 # = 1.0.303 PDK_MAGIC_COMMIT ?= fe2eb6d3906ed15ade0e7a51daea80dd4e3846e2 # = 8.3.294 From e3b2cd94589d2e5ab62c83b17b91e630ca8066df Mon Sep 17 00:00:00 2001 From: jeffdi Date: Wed, 21 Sep 2022 17:37:17 +0000 Subject: [PATCH 17/22] Apply automatic changes to Manifest and README.rst --- manifest | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/manifest b/manifest index 6df8fb5e..d5ec2e39 100644 --- a/manifest +++ b/manifest @@ -2,10 +2,10 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -a349dd3c5fae352a0a89131bf65018650944977f verilog/rtl/caravan.v +1cd495e2e1223a5fd549f10e613076679a83eac6 verilog/rtl/caravan.v a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v +a017c38ef9b280e55b1ced730e643300b66f2ab3 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v From 76627f546bc28d4db03f84973ed65d683ba8f485 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Wed, 5 Oct 2022 21:31:25 -0400 Subject: [PATCH 18/22] Reverting the Makefile, which somehow got picked up from the wrong branch and committed into this one. --- Makefile | 113 ++++--------------------------------------------------- 1 file changed, 7 insertions(+), 106 deletions(-) diff --git a/Makefile b/Makefile index b9e2ad1f..2e7ea7d5 100644 --- a/Makefile +++ b/Makefile @@ -44,7 +44,7 @@ LARGE_FILES_GZ_SPLIT += $(addsuffix .00.split, $(ARCHIVES)) MCW_ROOT?=$(PWD)/mgmt_core_wrapper MCW ?=LITEX_VEXRISCV -MPW_TAG ?= caravel_stanford +MPW_TAG ?= mpw-5e # PDK switch varient export PDK?=sky130A @@ -86,7 +86,7 @@ SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl IO_LIBRARY ?= sky130_fd_io PRIMITIVES_LIBRARY ?= sky130_fd_pr SKYWATER_COMMIT ?= c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -OPEN_PDKS_COMMIT ?= 8f6aff1881e5feae49acb6d5be53c4acc91bb235 +OPEN_PDKS_COMMIT ?= 05af1d05227419f0955cd98610351f4680575b95 # = 1.0.303 PDK_MAGIC_COMMIT ?= fe2eb6d3906ed15ade0e7a51daea80dd4e3846e2 # = 8.3.294 @@ -201,114 +201,15 @@ clean: cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \ $(MAKE) -j$(THREADS) clean -######### -## Verify - - -#.PHONY: verify -#verify: -# cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \ -# $(MAKE) -j$(THREADS) all -# cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \ -# $(MAKE) -j$(THREADS) all - -.PHONY: simenv -simenv: - docker pull efabless/dv:latest - -dv_caravel_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-caravel && find * -maxdepth 0 -type d) -dv_standalone_patterns=$(shell cd mgmt_core_wrapper/verilog/dv/tests-standalone && find * -maxdepth 0 -type d) -dv-caravel-targets-rtl=$(dv_caravel_patterns:%=verify-caravel-%-rtl) -dv-standalone-targets-rtl=$(dv_standalone_patterns:%=verify-standalone-%-rtl) -dv-caravel-targets-gl=$(dv_caravel_patterns:%=verify-caravel-%-gl) -dv-standalone-targets-gl=$(dv_standalone_patterns:%=verify-standalone-%-gl) -dv-caravel-targets-gl-sdf=$(dv_caravel_patterns:%=verify-caravel-%-gl-sdf) -dv-standalone-targets-gl-sdf=$(dv_standalone_patterns:%=verify-standalone-%-gl-sdf) - -VERIFY_LOG = "verify-${CONFIG}-${SIM}.log" -TARGET_PATH=$(shell pwd) -verify_command="source ~/.bashrc && cd ${TARGET_PATH}/mgmt_core_wrapper/verilog/dv/tests-${CONFIG}/$* && export SIM=${SIM} && make" -dv_base_dependencies=simenv -docker_run_verify=\ - docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ - -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ - -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ - -e CARAVEL_ROOT=${CARAVEL_ROOT} \ - -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \ - -e DESIGNS=$(TARGET_PATH) \ - -e PDK=$(PDK) \ - -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ - -e MCW_ROOT=$(MCW_ROOT) \ - -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \ - sh -c $(verify_command) | tee -a ${VERIFY_LOG} - -.PHONY: harden -harden: $(blocks) .PHONY: verify -verify: $(dv-caravel-targets-rtl) +verify: + cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \ + $(MAKE) -j$(THREADS) all + cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \ + $(MAKE) -j$(THREADS) all -.PHONY: verify_log_header -verify_log_header: - @echo "*************************************************************************" > ${VERIFY_LOG} - @echo "Verification Log: `date` Configuration: ${CONFIG} ${SIM}" >> ${VERIFY_LOG} - @echo "*************************************************************************" >> ${VERIFY_LOG} -.PHONY: verify-caravel-all-rtl verify-standalone-all-rtl -verify-caravel-all-rtl: $(dv-caravel-targets-rtl) -verify-standalone-all-rtl: $(dv-standalone-targets-rtl) - -.PHONY: verify-caravel-all-gl verify-standalone-all-gl -verify-caravel-all-gl: $(dv-caravel-targets-gl) -verify-standalone-all-gl: $(dv-standalone-targets-gl) - -.PHONY: verify-caravel-all-gl-sdf verify-standalone-all-gl-sdf -verify-caravel-all-gl-sdf: $(dv-targets-gl-sdf) -verify-standalone-all-gl-sdf: $(dv-targets-gl-sdf) - -$(dv-caravel-targets-rtl): SIM=RTL -$(dv-caravel-targets-rtl): CONFIG=caravel -$(dv-caravel-targets-rtl): verify-caravel-%-rtl: $(dv_base_dependencies) verify_log_header - $(docker_run_verify) - -$(dv-caravel-targets-gl): SIM=GL -$(dv-caravel-targets-gl): CONFIG=caravel -$(dv-caravel-targets-gl): verify-caravel-%-gl: $(dv_base_dependencies) verify_log_header - $(docker_run_verify) - -$(dv-caravel-targets-gl-sdf): SIM=GL_SDF -$(dv-caravel-targets-gl-sdf): CONFIG=caravel -$(dv-caravel-targets-gl-sdf): verify-caravel-%-gl-sdf: $(dv_base_dependencies) verify_log_header - $(docker_run_verify) - -$(dv-standalone-targets-rtl): SIM=RTL -$(dv-standalone-targets-rtl): CONFIG=standalone -$(dv-standalone-targets-rtl): verify-standalone-%-rtl: $(dv_base_dependencies) verify_log_header - $(docker_run_verify) - -$(dv-standalone-targets-gl): SIM=GL -$(dv-standalone-targets-gl): CONFIG=standalone -$(dv-standalone-targets-gl): verify-standalone-%-gl: $(dv_base_dependencies) verify_log_header - $(docker_run_verify) - -$(dv-standalone-targets-gl-sdf): SIM=GL_SDF -$(dv-standalone-targets-gl-sdf): CONFIG=standalone -$(dv-standalone-targets-gl-sdf): verify-standalone-%-gl-sdf: $(dv_base_dependencies) verify_log_header - $(docker_run_verify) - -clean-targets=$(blocks:%=clean-%) -.PHONY: $(clean-targets) -$(clean-targets): clean-% : - rm -f ./verilog/gl/$*.v - rm -f ./spef/$*.spef - rm -f ./sdc/$*.sdc - rm -f ./sdf/$*.sdf - rm -f ./gds/$*.gds - rm -f ./mag/$*.mag - rm -f ./lef/$*.lef - rm -f ./maglef/*.maglef - -############### ##### $(LARGE_FILES_GZ): %.$(ARCHIVE_EXT): % From 6831b85e3c5031766976c9031334dc2c868dafa1 Mon Sep 17 00:00:00 2001 From: RTimothyEdwards Date: Thu, 6 Oct 2022 01:34:14 +0000 Subject: [PATCH 19/22] Apply automatic changes to Manifest and README.rst --- manifest | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/manifest b/manifest index 08025efb..c23e296d 100644 --- a/manifest +++ b/manifest @@ -2,8 +2,8 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v -a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v +ebd68a20da36a7f2cde0f4aa02ab2fce44000dbe verilog/rtl/caravan.v +a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v a017c38ef9b280e55b1ced730e643300b66f2ab3 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v @@ -14,7 +14,7 @@ fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v 941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v -60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v +2b8a0d04b8f7214a5205aade7ec074fe32dbb44e verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v 8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v From e2556cc11b1caed14b3d308d5fdde1ccd88061f0 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Wed, 5 Oct 2022 21:37:55 -0400 Subject: [PATCH 20/22] Removed the SPARE_LOGIC_BLOCK ifdef...endif from around the spare logic in caravel.v and caravan.v. These had been added to the caravel_stanford branch because the spare logic blocks are not usefully synthesizable. --- verilog/rtl/caravan.v | 3 --- verilog/rtl/caravel.v | 2 -- 2 files changed, 5 deletions(-) diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 5b357042..3751c4ee 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -1375,7 +1375,6 @@ module caravan ( .X(rstb_l) ); - `ifdef USE_SPARE_LOGIC // Spare logic for metal mask fixes wire [107:0] spare_xz_nc; wire [15:0] spare_xi_nc; @@ -1400,8 +1399,6 @@ module caravan ( .spare_xfq(spare_xfq_nc), .spare_xfqn(spare_xfqn_nc) ); - `endif - endmodule // `default_nettype wire diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 3a8e082e..315fbc30 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -1427,7 +1427,6 @@ module caravel ( .X(rstb_l) ); - `ifdef USE_SPARE_LOGIC // Spare logic for metal mask fixes wire [107:0] spare_xz_nc; wire [15:0] spare_xi_nc; @@ -1452,7 +1451,6 @@ module caravel ( .spare_xfq(spare_xfq_nc), .spare_xfqn(spare_xfqn_nc) ); - `endif endmodule // `default_nettype wire From 77b47e3b5c69075d70f717b3009e027f01cc352f Mon Sep 17 00:00:00 2001 From: RTimothyEdwards Date: Thu, 6 Oct 2022 01:39:57 +0000 Subject: [PATCH 21/22] Apply automatic changes to Manifest and README.rst --- manifest | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/manifest b/manifest index c23e296d..3abfdd60 100644 --- a/manifest +++ b/manifest @@ -2,10 +2,10 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -ebd68a20da36a7f2cde0f4aa02ab2fce44000dbe verilog/rtl/caravan.v +462e675b1c3d5949856b5d8b7b893ffa5a012f79 verilog/rtl/caravan.v a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -a017c38ef9b280e55b1ced730e643300b66f2ab3 verilog/rtl/caravel.v +bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v From 42805f767e0e9fb91e8e4937e1be780fad62edb2 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Wed, 5 Oct 2022 21:43:29 -0400 Subject: [PATCH 22/22] Removed some references to mgmt_soc_litex files that had been added to caravel_netlists.v when attempting to determine if the verification testbenches could be run from caravel referencing caravel_mgmt_soc_litex instead of the other way around. This file has been reverted back to its original form. --- verilog/rtl/caravel_netlists.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index 2a6d2d0a..dfdcecbc 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -66,10 +66,6 @@ `include "gl/spare_logic_block.v" `include "gl/mgmt_defines.v" `include "gl/mgmt_core_wrapper.v" - `include "gl/mgmt_core.v" - `include "gl/DFFRAM.v" - `include "gl/DFFRAMBB.v" - `include "gl/VexRiscv_LiteDebug.v" `include "gl/caravel.v" `else `include "digital_pll.v" @@ -93,10 +89,6 @@ `include "xres_buf.v" `include "spare_logic_block.v" `include "mgmt_core_wrapper.v" - `include "mgmt_core.v" - `include "DFFRAM.v" - `include "DFFRAMBB.v" - `include "VexRiscv_LiteDebug.v" `include "caravel.v" `endif