diff --git a/manifest b/manifest index 00337339..3abfdd60 100644 --- a/manifest +++ b/manifest @@ -2,18 +2,19 @@ 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v -0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v -a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v +462e675b1c3d5949856b5d8b7b893ffa5a012f79 verilog/rtl/caravan.v +a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v -cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v +bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v -d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v -54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v +fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v +8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v +941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v -60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v +2b8a0d04b8f7214a5205aade7ec074fe32dbb44e verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v 8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v @@ -21,9 +22,9 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v 9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v -9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v +d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v -6f490c83d6064c380a3f475823ef97f325d7f6c1 verilog/rtl/pads.v +4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v 1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index f3315cd7..3751c4ee 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -165,6 +165,7 @@ module caravan ( wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in; wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3; wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out; + wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_one; // User Project Control (user-facing) // 27 GPIO bidirectional with in/out/oeb and a 3.3V copy of the input @@ -291,7 +292,6 @@ module caravan ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - .gpio(gpio), .mprj_io(mprj_io), .clock(clock), @@ -325,6 +325,7 @@ module caravan ( .flash_io1_do_core(flash_io1_do), .flash_io0_di_core(flash_io0_di), .flash_io1_di_core(flash_io1_di), + .mprj_io_one(mprj_io_one), .mprj_io_in(mprj_io_in), .mprj_io_in_3v3(mprj_io_in_3v3), .mprj_io_out(mprj_io_out), @@ -1099,7 +1100,7 @@ module caravan ( .mgmt_gpio_out(mgmt_io_out[1:0]), .mgmt_gpio_oeb(mgmt_io_oeb[1:0]), - .one(), + .one(mprj_io_one[1:0]), .zero(), // Serial data chain for pad configuration @@ -1127,7 +1128,6 @@ module caravan ( ); /* Section 1 GPIOs (GPIO 0 to 18) */ - wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:0] one_loop1; /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */ @@ -1153,9 +1153,9 @@ module caravan ( .mgmt_gpio_in(mgmt_io_in[7:2]), .mgmt_gpio_out(mgmt_io_in[7:2]), - .mgmt_gpio_oeb(one_loop1[5:0]), + .mgmt_gpio_oeb(mprj_io_one[7:2]), - .one(one_loop1[5:0]), + .one(mprj_io_one[7:2]), .zero(), // Serial data chain for pad configuration @@ -1205,9 +1205,9 @@ module caravan ( .mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]), .mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]), - .mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]), - .one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]), + .one(mprj_io_one[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]), .zero(), // Serial data chain for pad configuration @@ -1260,7 +1260,7 @@ module caravan ( .mgmt_gpio_out(mgmt_io_out[4:2]), .mgmt_gpio_oeb(mgmt_io_oeb[4:2]), - .one(), + .one(mprj_io_one[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]), .zero(), // Serial data chain for pad configuration @@ -1288,7 +1288,6 @@ module caravan ( ); /* Section 2 GPIOs (GPIO 19 to 37) */ - wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] one_loop2; gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] ( `ifdef USE_POWER_PINS @@ -1312,9 +1311,9 @@ module caravan ( .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]), .mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]), - .mgmt_gpio_oeb(one_loop2), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]), - .one(one_loop2), + .one(mprj_io_one[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]), .zero(), // Serial data chain for pad configuration diff --git a/verilog/rtl/caravan_netlists.v b/verilog/rtl/caravan_netlists.v index 8dc8a7eb..488fda46 100644 --- a/verilog/rtl/caravan_netlists.v +++ b/verilog/rtl/caravan_netlists.v @@ -58,6 +58,7 @@ `include "gl/mprj2_logic_high.v" `include "gl/mgmt_protect.v" `include "gl/mgmt_protect_hv.v" + `include "gl/constant_block.v" `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" @@ -83,6 +84,7 @@ `include "mprj2_logic_high.v" `include "mgmt_protect.v" `include "mgmt_protect_hv.v" + `include "constant_block.v" `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 706cb21a..315fbc30 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -142,6 +142,7 @@ module caravel ( wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm; wire [`MPRJ_IO_PADS-1:0] mprj_io_in; wire [`MPRJ_IO_PADS-1:0] mprj_io_out; + wire [`MPRJ_IO_PADS-1:0] mprj_io_one; // User Project Control (user-facing) wire [`MPRJ_IO_PADS-1:0] user_io_oeb; @@ -252,7 +253,6 @@ module caravel ( .vccd2 (vccd2_core), .vssd1 (vssd1_core), .vssd2 (vssd2_core), - .gpio(gpio), .mprj_io(mprj_io), .clock(clock), @@ -286,6 +286,7 @@ module caravel ( .flash_io1_do_core(flash_io1_do), .flash_io0_di_core(flash_io0_di), .flash_io1_di_core(flash_io1_di), + .mprj_io_one(mprj_io_one), .mprj_io_in(mprj_io_in), .mprj_io_out(mprj_io_out), .mprj_io_oeb(mprj_io_oeb), @@ -1152,7 +1153,7 @@ module caravel ( .mgmt_gpio_out(mgmt_io_out[1:0]), .mgmt_gpio_oeb(mgmt_io_oeb[1:0]), - .one(), + .one(mprj_io_one[1:0]), .zero(), // Serial data chain for pad configuration @@ -1179,9 +1180,6 @@ module caravel ( .pad_gpio_in(mprj_io_in[1:0]) ); - /* Section 1 GPIOs (GPIO 0 to 18) */ - wire [`MPRJ_IO_PADS_1-1:2] one_loop1; - /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */ gpio_control_block gpio_control_in_1a [5:0] ( @@ -1206,9 +1204,9 @@ module caravel ( .mgmt_gpio_in(mgmt_io_in[7:2]), .mgmt_gpio_out(mgmt_io_in[7:2]), - .mgmt_gpio_oeb(one_loop1[7:2]), + .mgmt_gpio_oeb(mprj_io_one[7:2]), - .one(one_loop1[7:2]), + .one(mprj_io_one[7:2]), .zero(), // Serial data chain for pad configuration @@ -1259,9 +1257,9 @@ module caravel ( .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]), .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]), - .mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]), - .one(one_loop1[(`MPRJ_IO_PADS_1-1):8]), + .one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]), .zero(), // Serial data chain for pad configuration @@ -1314,7 +1312,7 @@ module caravel ( .mgmt_gpio_out(mgmt_io_out[4:2]), .mgmt_gpio_oeb(mgmt_io_oeb[4:2]), - .one(), + .one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]), .zero(), // Serial data chain for pad configuration @@ -1342,7 +1340,6 @@ module caravel ( ); /* Section 2 GPIOs (GPIO 19 to 34) */ - wire [`MPRJ_IO_PADS_2-4:0] one_loop2; gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] ( `ifdef USE_POWER_PINS @@ -1366,9 +1363,9 @@ module caravel ( .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), - .mgmt_gpio_oeb(one_loop2), + .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), - .one(one_loop2), + .one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]), .zero(), // Serial data chain for pad configuration diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index c967700e..dfdcecbc 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -56,6 +56,7 @@ `include "gl/mprj2_logic_high.v" `include "gl/mgmt_protect.v" `include "gl/mgmt_protect_hv.v" + `include "gl/constant_block.v" `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_defaults_block_0403.v" @@ -81,6 +82,7 @@ `include "mprj2_logic_high.v" `include "mgmt_protect.v" `include "mgmt_protect_hv.v" + `include "constant_block.v" `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 8ae69d11..7aafd2db 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -97,6 +97,8 @@ module chip_io( input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol, input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm, output [`MPRJ_IO_PADS-1:0] mprj_io_in, + // Loopbacks to constant value 1 in the 1.8V domain + input [`MPRJ_IO_PADS-1:0] mprj_io_one, // User project direct access to gpio pad connections for analog // (all but the lowest-numbered 7 pads) inout [`MPRJ_IO_PADS-10:0] mprj_analog_io @@ -273,19 +275,29 @@ module chip_io( wire[2:0] flash_io1_mode = {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; + wire [6:0] vccd_const_one; // Constant value for management pins + wire [6:0] vssd_const_zero; // Constant value for management pins + + constant_block constant_value_inst [6:0] ( + .vccd(vccd), + .vssd(vssd), + .one(vccd_const_one), + .zero(vssd_const_zero) + ); + // Management clock input pad - `INPUT_PAD(clock, clock_core); + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -293,6 +305,7 @@ module chip_io( // free reset. wire xresloop; + wire xres_vss_loop; sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING @@ -300,16 +313,16 @@ module chip_io( `endif .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h .TIE_HI_ESD(), - .TIE_LO_ESD(), + .TIE_LO_ESD(xres_vss_loop), .PAD_A_ESD_H(xresloop), .XRES_H_N(resetb_core_h), - .DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad - .ENABLE_H(porb_h), // Power-on-reset - .EN_VDDIO_SIG_H(vssio), // No idea. - .INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input - .FILT_IN_H(vssio), // Alternate input for glitch filter - .PULLUP_H(vssio), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd) + .DISABLE_PULLUP_H(xres_vss_loop), // 0 = enable pull-up on reset pad + .ENABLE_H(porb_h), // Power-on-reset + .EN_VDDIO_SIG_H(xres_vss_loop), // No idea. + .INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input + .FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter + .PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input + .ENABLE_VDDIO(vccd_const_one[6]) ); // Corner cells (These are overlay cells; it is not clear what is normally @@ -378,6 +391,7 @@ module chip_io( .analog_a(analog_a), .analog_b(analog_b), .porb_h(porb_h), + .vccd_conb(mprj_io_one), .io(mprj_io), .io_out(mprj_io_out), .oeb(mprj_io_oeb), diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v index 0ea1fafa..3b74b35d 100644 --- a/verilog/rtl/chip_io_alt.v +++ b/verilog/rtl/chip_io_alt.v @@ -116,6 +116,7 @@ module chip_io_alt #( input [(`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2)*3-1:0] mprj_io_dm, output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in, output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in_3v3, + input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_one, // User project direct access to gpio pad connections for analog // "analog" connects to the "esd_0" pin of the GPIO pad, and @@ -343,18 +344,28 @@ module chip_io_alt #( wire[2:0] flash_io1_mode = {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; + wire [6:0] vccd_const_one; // Constant value for management pins + wire [6:0] vssd_const_zero; // Constant value for management pins + + constant_block constant_value_inst [6:0] ( + .vccd(vccd), + .vssd(vssd), + .one(vccd_const_one), + .zero(vssd_const_zero) + ); + // Management clock input pad - `INPUT_PAD(clock, clock_core); + `INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]); // Management GPIO pad - `INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); + `INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all); // Management Flash SPI pads - `INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); - `INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); - `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core); - `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core); + `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core); // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board @@ -362,6 +373,7 @@ module chip_io_alt #( // free reset. wire xresloop; + wire xres_zero_loop sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING @@ -369,16 +381,16 @@ module chip_io_alt #( `endif .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h .TIE_HI_ESD(), - .TIE_LO_ESD(), + .TIE_LO_ESD(xres_zero_loop), .PAD_A_ESD_H(xresloop), .XRES_H_N(resetb_core_h), - .DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad - .ENABLE_H(porb_h), // Power-on-reset - .EN_VDDIO_SIG_H(vssio), // No idea. - .INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input - .FILT_IN_H(vssio), // Alternate input for glitch filter - .PULLUP_H(vssio), // Pullup connection for alternate filter input - .ENABLE_VDDIO(vccd) + .DISABLE_PULLUP_H(xres_zero_loop), // 0 = enable pull-up on reset pad + .ENABLE_H(porb_h), // Power-on-reset + .EN_VDDIO_SIG_H(xres_zero_loop), // No idea. + .INP_SEL_H(xres_zero_loop), // 1 = use filt_in_h else filter the pad input + .FILT_IN_H(xres_zero_loop), // Alternate input for glitch filter + .PULLUP_H(xres_zero_loop), // Pullup connection for alternate filter input + .ENABLE_VDDIO(vccd_const_one[6]) ); // Corner cells (These are overlay cells; it is not clear what is normally @@ -451,6 +463,7 @@ module chip_io_alt #( .analog_a(analog_a), .analog_b(analog_b), .porb_h(porb_h), + .vccd_conb(mprj_io_one), .io({mprj_io[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS_1+ANALOG_PADS_2], mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}), diff --git a/verilog/rtl/constant_block.v b/verilog/rtl/constant_block.v new file mode 100644 index 00000000..d6a03b3e --- /dev/null +++ b/verilog/rtl/constant_block.v @@ -0,0 +1,77 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *--------------------------------------------------------------------- + * A simple module that generates buffered high and low outputs + * in the 1.8V domain. + *--------------------------------------------------------------------- + */ + +module constant_block ( + `ifdef USE_POWER_PINS + inout vccd, + inout vssd, + `endif + + output one, + output zero +); + + wire one_unbuf; + wire zero_unbuf; + + sky130_fd_sc_hd__conb_1 const_source ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .HI(one_unbuf), + .LO(zero_unbuf) + ); + + /* Buffer the constant outputs (could be synthesized) */ + /* NOTE: Constant cell HI, LO outputs are connected to power */ + /* rails through an approximately 120 ohm resistor, which is not */ + /* enough to drive inputs in the I/O cells while ensuring ESD */ + /* requirements, without buffering. */ + + sky130_fd_sc_hd__buf_16 const_one_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(one_unbuf), + .X(one) + ); + + sky130_fd_sc_hd__buf_16 const_zero_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(zero_unbuf), + .X(zero) + ); + +endmodule +`default_nettype wire diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index 639d734a..7163e7bf 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -140,8 +140,8 @@ module gpio_control_block #( wire pad_gpio_outenb; wire pad_gpio_out; wire pad_gpio_in; - wire one; - wire zero; + wire one_unbuf; + wire zero_unbuf; wire user_gpio_in; wire gpio_in_unbuf; @@ -261,8 +261,36 @@ module gpio_control_block #( .VPB(vccd), .VNB(vssd), `endif - .HI(one), - .LO(zero) + .HI(one_unbuf), + .LO(zero_unbuf) + ); + + /* Buffer the constant outputs (could be synthesized) */ + /* NOTE: Constant cell HI, LO outputs are connected to power */ + /* rails through an approximately 120 ohm resistor, which is not */ + /* enough to drive inputs in the I/O cells while ensuring ESD */ + /* requirements, without buffering. */ + + sky130_fd_sc_hd__buf_8 const_one_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(one_unbuf), + .X(one) + ); + + sky130_fd_sc_hd__buf_8 const_zero_buf ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .A(zero_unbuf), + .X(zero) ); endmodule diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v index ec4fdf99..f76cfc7a 100644 --- a/verilog/rtl/mprj_io.v +++ b/verilog/rtl/mprj_io.v @@ -44,6 +44,7 @@ module mprj_io #( input analog_a, input analog_b, input porb_h, + input [TOTAL_PADS-1:0] vccd_conb, inout [TOTAL_PADS-1:0] io, input [TOTAL_PADS-1:0] io_out, input [TOTAL_PADS-1:0] oeb, @@ -79,8 +80,8 @@ module mprj_io #( .ENABLE_H(enh[AREA1PADS - 1:0]), .ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]), .ENABLE_VDDA_H(porb_h), - .ENABLE_VSWITCH_H(vssio), - .ENABLE_VDDIO(vccd), + .ENABLE_VSWITCH_H(loop1_io[AREA1PADS - 1:0]), + .ENABLE_VDDIO(vccd_conb[AREA1PADS - 1:0]), .INP_DIS(inp_dis[AREA1PADS - 1:0]), .IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]), .VTRIP_SEL(vtrip_sel[AREA1PADS - 1:0]), @@ -110,8 +111,8 @@ module mprj_io #( .ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_VDDA_H(porb_h), - .ENABLE_VSWITCH_H(vssio), - .ENABLE_VDDIO(vccd), + .ENABLE_VSWITCH_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]), + .ENABLE_VDDIO(vccd_conb[TOTAL_PADS - 1:AREA1PADS]), .INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]), .IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]), .VTRIP_SEL(vtrip_sel[TOTAL_PADS - 1:AREA1PADS]), diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index 86e0be5d..623fc818 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -73,40 +73,42 @@ .SRC_BDY_LVC1(L1), \ .SRC_BDY_LVC2(L2) -`define INPUT_PAD(X,Y) \ - wire loop_``X; \ +`define INPUT_PAD(X,Y,CONB_ONE,CONB_ZERO) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ .PAD(X), \ `endif \ - .OUT(vssd), \ - .OE_N(vccd), \ - .HLD_H_N(vddio), \ + .OUT(CONB_ZERO), \ + .OE_N(CONB_ONE), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(por), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ - .DM({vssd, vssd, vccd}), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ZERO, CONB_ZERO, CONB_ONE}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(Y), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X) ) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X) ) -`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \ - wire loop_``X; \ +`define OUTPUT_PAD(X,Y,CONB_ONE,CONB_ZERO,INPUT_DIS,OUT_EN_N) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ @@ -114,31 +116,32 @@ `endif \ .OUT(Y), \ .OE_N(OUT_EN_N), \ - .HLD_H_N(vddio), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ - .DM({vccd, vccd, vssd}), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X)) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X)) -`define OUTPUT_NO_INP_DIS_PAD(X,Y,OUT_EN_N) \ - wire loop_``X; \ +`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,CONB_ZERO,OUT_EN_N) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ @@ -146,31 +149,32 @@ `endif \ .OUT(Y), \ .OE_N(OUT_EN_N), \ - .HLD_H_N(vddio), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ - .INP_DIS(loop_``X), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ - .DM({vccd, vccd, vssd}), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ + .INP_DIS(CONB_ZERO), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ + .DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X)) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X)) -`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ - wire loop_``X; \ +`define INOUT_PAD(X,Y,CONB_ONE,CONB_ZERO,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \ + wire loop_zero_``X; \ + wire loop_one_``X; \ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ @@ -178,27 +182,27 @@ `endif \ .OUT(Y_OUT), \ .OE_N(OUT_EN_N), \ - .HLD_H_N(vddio), \ + .HLD_H_N(loop_one_``X), \ .ENABLE_H(porb_h), \ - .ENABLE_INP_H(loop_``X), \ + .ENABLE_INP_H(loop_zero_``X), \ .ENABLE_VDDA_H(porb_h), \ - .ENABLE_VSWITCH_H(vssa), \ - .ENABLE_VDDIO(vccd), \ + .ENABLE_VSWITCH_H(loop_zero_``X), \ + .ENABLE_VDDIO(CONB_ONE), \ .INP_DIS(INPUT_DIS), \ - .IB_MODE_SEL(vssd), \ - .VTRIP_SEL(vssd), \ - .SLOW(vssd), \ - .HLD_OVR(vssd), \ - .ANALOG_EN(vssd), \ - .ANALOG_SEL(vssd), \ - .ANALOG_POL(vssd), \ + .IB_MODE_SEL(CONB_ZERO), \ + .VTRIP_SEL(CONB_ZERO), \ + .SLOW(CONB_ZERO), \ + .HLD_OVR(CONB_ZERO), \ + .ANALOG_EN(CONB_ZERO), \ + .ANALOG_SEL(CONB_ZERO), \ + .ANALOG_POL(CONB_ZERO), \ .DM(MODE), \ .PAD_A_NOESD_H(), \ .PAD_A_ESD_0_H(), \ .PAD_A_ESD_1_H(), \ .IN(Y), \ .IN_H(), \ - .TIE_HI_ESD(), \ - .TIE_LO_ESD(loop_``X) ) + .TIE_HI_ESD(loop_one_``X), \ + .TIE_LO_ESD(loop_zero_``X) ) // `default_nettype wire