Correction to the mprj_bitbang testbench to run the test without running

into issues of contention between the SPI and wishbone interfaces.  The
testbench now passes, although the contention isn't handled particularly
well.

verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang.c

@@ -33,7 +33,6 @@ void main()
     /* config for the management SoC to apply output.		*/
 
     reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
-
     reg_mprj_datal = 0xffffffff;
     reg_mprj_datah = 0x0000003f;
 

verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang_tb.v

@@ -230,6 +230,16 @@ module mprj_bitbang_tb;
 	    RSTB <= 1'b1;
 	    #2000;
 
+	    // Give 100us for the startup code to complete and the GPIO output
+	    // value set.
+	    #100000;
+
+	    // NOTE:  The SPI takes precedence over the wishbone back-door
+	    // access and the GPIO lines will not get set from the program
+	    // while CSB is held low.  The C program keeps attempting a
+	    // write and should succeed after the following code finishes
+	    // and CSB is raised.
+
 	    start_csb();
 	    write_byte(8'h80);	// Write stream command
 	    write_byte(8'h13);	// Address (register 19 = GPIO bit-bang control)

verilog/rtl/defines.v

@@ -56,9 +56,11 @@
 `define CLK_DIV 3'b010
 
 // GPIO control default mode and enable for most I/Os
-// Most I/Os set to be user bidirectional pins on power-up.
+// Most I/Os set to be user input pins on startup.
+// NOTE:  To be modified, with GPIOs 5 to 35 being set from a build-time-
+// programmable block.
 `define MGMT_INIT 1'b0
 `define OENB_INIT 1'b0
-`define DM_INIT 3'b110
+`define DM_INIT 3'b001
 
 `endif // __GLOBAL_DEFINE_H