From 56c0fdcd81c2ab1f3112dd16d25da3af99df5fc0 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Fri, 21 Apr 2023 09:15:24 -0700 Subject: [PATCH 1/2] change -quiet to -silent in compositor.py --- scripts/compositor.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/compositor.py b/scripts/compositor.py index c5c01398..999038f7 100755 --- a/scripts/compositor.py +++ b/scripts/compositor.py @@ -179,7 +179,7 @@ if __name__ == '__main__': # it's gigabytes anyway, so we don't want to deal with any # actual data. So it's just a placeholder. - print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile) + print('load ' + project_with_id + '_fill_pattern -silent', file=ofile) print('snap internal', file=ofile) print('box values {*}$bbox', file=ofile) print('paint comment', file=ofile) @@ -188,7 +188,7 @@ if __name__ == '__main__': print('property FIXED_BBOX "$bbox"', file=ofile) # Create a new project top level and place the fill cell. - print('load ' + project_with_id + ' -quiet', file=ofile) + print('load ' + project_with_id + ' -silent', file=ofile) print('box values 0 0 0 0', file=ofile) print('box position 6um 6um', file=ofile) print('getcell ' + project + ' child 0 0', file=ofile) @@ -230,7 +230,7 @@ if __name__ == '__main__': for line in mproc.stdout.splitlines(): print(line) if mproc.stderr: - # NOTE: Until there is a "load -quiet" option in magic, loading + # NOTE: Until there is a "load -silent" option in magic, loading # a new cell generates an error. This code ignores the error. newlines = [] for line in mproc.stderr.splitlines(): From b8a11f868a70d0e33800ae7e4739f76d402e1942 Mon Sep 17 00:00:00 2001 From: jeffdi Date: Fri, 21 Apr 2023 16:28:30 +0000 Subject: [PATCH 2/2] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index 6813f391..2d8f7aab 100644 --- a/manifest +++ b/manifest @@ -47,4 +47,4 @@ b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v 8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v c94f7ed5aa311f005513ace344991c8e6d3d19f5 scripts/set_user_id.py 98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py -3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py +9e31b1bbbb03024d02d54f9da8d42b3837abc5e5 scripts/compositor.py