mirror of https://github.com/efabless/caravel.git
Optimize and update mem tests - script is generating new linker script for the test to be all to test the whole dff or dff2 memory
This commit is contained in:
M0stafaRady
parent
4dd3644438
commit
422bb26ca0
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@ -30,7 +30,4 @@ void main()
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if (!is_fail)
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reg_debug_1 = 0x1B;
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// test finish
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reg_debug_1 = 0xFF;
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}
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@ -30,7 +30,4 @@ void main()
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if (!is_fail)
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reg_debug_1 = 0x1B;
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// test finish
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reg_debug_1 = 0xFF;
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}
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@ -13,15 +13,13 @@ reg = Regs()
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@cocotb.test()
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@repot_test
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async def mem_dff2(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
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caravelEnv,clock = await test_configure(dut,timeout_cycles=1426536)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start mem stress test")
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pass_list = (0x1B)
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fail_list = (0x1E)
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phases_fails = 1
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phases_passes = 0
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pass_list = [0x1B]
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fail_list = [0x1E]
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reg1 =0 # buffer
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while True:
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if cpu.read_debug_reg1() == 0xFF: # test finish
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@ -29,45 +27,34 @@ async def mem_dff2(dut):
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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if reg1 in pass_list: # pass phase
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phases_passes +=1
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phases_fails -=1
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cocotb.log.info(f"[TEST] pass writing and reading all dff2 memory ")
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break
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elif reg1 in fail_list: # pass phase
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cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
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break
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await ClockCycles(caravelEnv.clk,100)
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if phases_fails > 0:
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cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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else:
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cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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@cocotb.test()
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@repot_test
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async def mem_dff(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
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caravelEnv,clock = await test_configure(dut,timeout_cycles=2378120)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start mem stress test")
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pass_list = (0x1B)
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fail_list = (0x1E)
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phases_fails = 1
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phases_passes = 0
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pass_list = [0x1B]
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fail_list = [0x1E]
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reg1 =0 # buffer
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while True:
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if cpu.read_debug_reg1() == 0xFF: # test finish
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break
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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if reg1 in pass_list: # pass phase
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phases_passes +=1
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phases_fails -=1
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cocotb.log.info(f"[TEST] pass writing and reading all dff memory ")
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break
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elif reg1 in fail_list: # pass phase
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cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
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break
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await ClockCycles(caravelEnv.clk,100)
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if phases_fails > 0:
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cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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else:
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cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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@ -36,10 +36,6 @@ def change_dff(str,new_str,file_path):
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with open(file_path, 'r') as file :
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filedata = file.read()
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if new_str == "> dff2":
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if new_str in filedata: # to avoid type dff22 types
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return
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# Replace the target string
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filedata = filedata.replace(str, new_str)
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# Write the file out again
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@ -160,6 +156,7 @@ class RunTest:
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def hex_generate(self):
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tests_use_dff2 = ["mem_dff"]
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tests_use_dff = ["mem_dff2"]
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#open docker
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test_path =self.test_path()
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self.cd_make()
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@ -175,15 +172,18 @@ class RunTest:
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CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ "
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verilog_path = f"{os.getenv('VERILOG_PATH')}"
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test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo
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print(test_dir)
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#change linker script to for mem tests
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if self.test_name in tests_use_dff2:
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LINKER_SCRIPT = self.linkerScript_for_mem("dff2",LINKER_SCRIPT)
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elif self.test_name in tests_use_dff:
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LINKER_SCRIPT = self.linkerScript_for_mem("dff",LINKER_SCRIPT)
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elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated -I{verilog_path}/dv/ "
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f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT},"
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f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
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hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
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sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
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#change linker script to dff2
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if self.test_name in tests_use_dff2:
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change_dff(str="> dff",new_str="> dff2",file_path=LINKER_SCRIPT)
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hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
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self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
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self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
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@ -193,8 +193,24 @@ class RunTest:
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if hex_gen_state != 0 :
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print(f"fatal: Error when generating hex")
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sys.exit()
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if self.test_name in tests_use_dff2:
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change_dff(str="> dff2",new_str="> dff",file_path=LINKER_SCRIPT)
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#change linker script to for mem tests
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def linkerScript_for_mem(self,ram,LINKER_SCRIPT):
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new_LINKER_SCRIPT = f"{self.cocotb_path}/{self.sim_path}/sections.lds"
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shutil.copyfile(LINKER_SCRIPT, new_LINKER_SCRIPT)
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if ram == "dff2":
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change_dff(str="> dff ",new_str="> dff2 ",file_path=new_LINKER_SCRIPT)
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change_dff(str="> dff\n",new_str="> dff2\n",file_path=new_LINKER_SCRIPT)
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change_dff(str="ORIGIN(dff)",new_str="ORIGIN(dff2)",file_path=LINKER_SCRIPT)
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change_dff(str="LENGTH(dff)",new_str="LENGTH(dff2)",file_path=LINKER_SCRIPT)
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elif ram == "dff":
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change_dff(str="> dff2 ",new_str="> dff ",file_path=new_LINKER_SCRIPT)
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change_dff(str="ORIGIN(dff2)",new_str="ORIGIN(dff)",file_path=LINKER_SCRIPT)
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change_dff(str="LENGTH(dff2)",new_str="LENGTH(dff)",file_path=LINKER_SCRIPT)
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else:
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print(f"ERROR: wrong trype of ram {ram} need to be used for now the oldy rams that can be used for flashing and data are dff and dff2")
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sys.exit()
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return new_LINKER_SCRIPT
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def cd_make(self):
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os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")
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