Optimize and update mem tests - script is generating new linker script for the test to be all to test the whole dff or dff2 memory

verilog/dv/cocotb/tests/mem/mem_dff.c

@@ -30,7 +30,4 @@ void main()
     if (!is_fail)
         reg_debug_1 = 0x1B;
 
-
-    // test finish 
-    reg_debug_1 = 0xFF;
 }

verilog/dv/cocotb/tests/mem/mem_dff2.c

@@ -30,7 +30,4 @@ void main()
     if (!is_fail)
         reg_debug_1 = 0x1B;
 
-
-    // test finish 
-    reg_debug_1 = 0xFF;
 }

verilog/dv/cocotb/tests/mem/mem_stress.py

@@ -13,15 +13,13 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def mem_dff2(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1426536)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     cocotb.log.info(f"[TEST] Start mem stress test")   
-    pass_list = (0x1B)
+    pass_list = [0x1B]
-    fail_list = (0x1E)
+    fail_list = [0x1E]
-    phases_fails = 1
-    phases_passes = 0
     reg1 =0 # buffer
     while True: 
         if cpu.read_debug_reg1() == 0xFF:  # test finish 
@@ -29,45 +27,34 @@ async def mem_dff2(dut):
         if reg1 != cpu.read_debug_reg1():
             reg1 = cpu.read_debug_reg1()
             if reg1 in pass_list:  # pass phase
-                phases_passes +=1
-                phases_fails  -=1
                 cocotb.log.info(f"[TEST] pass writing and reading all dff2 memory ")   
+                break
             elif reg1 in fail_list:  # pass phase
                 cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")     
+                break
         await ClockCycles(caravelEnv.clk,100) 
 
-    if phases_fails > 0:
-        cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") 
-    else:
-        cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")        
 
 @cocotb.test()
 @repot_test
 async def mem_dff(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=2378120)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     cocotb.log.info(f"[TEST] Start mem stress test")   
-    pass_list = (0x1B)
+    pass_list = [0x1B]
-    fail_list = (0x1E)
+    fail_list = [0x1E]
-    phases_fails = 1
-    phases_passes = 0
     reg1 =0 # buffer
     while True: 
-        if cpu.read_debug_reg1() == 0xFF:  # test finish 
-            break
         if reg1 != cpu.read_debug_reg1():
             reg1 = cpu.read_debug_reg1()
             if reg1 in pass_list:  # pass phase
-                phases_passes +=1
-                phases_fails  -=1
                 cocotb.log.info(f"[TEST] pass writing and reading all dff memory ")  
+                break 
             elif reg1 in fail_list:  # pass phase
                 cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")     
+                break 
         await ClockCycles(caravelEnv.clk,100) 
     
-    if phases_fails > 0:
+   
-        cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") 
-    else:
-        cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")        

verilog/dv/cocotb/verify_cocotb.py

@@ -36,10 +36,6 @@ def change_dff(str,new_str,file_path):
     with open(file_path, 'r') as file :
         filedata = file.read()
 
-    if new_str == "> dff2":
-        if new_str in filedata: # to avoid type dff22 types 
-            return
-    # Replace the target string
     filedata = filedata.replace(str, new_str)
 
     # Write the file out again
@@ -160,6 +156,7 @@ class RunTest:
 
     def hex_generate(self):
         tests_use_dff2 = ["mem_dff"]
+        tests_use_dff = ["mem_dff2"]
         #open docker 
         test_path =self.test_path()
         self.cd_make()
@@ -175,15 +172,18 @@ class RunTest:
         CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ "
         verilog_path = f"{os.getenv('VERILOG_PATH')}"
         test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo
-        print(test_dir)
+        #change linker script to for mem tests 
+        if self.test_name in tests_use_dff2:
+           LINKER_SCRIPT = self.linkerScript_for_mem("dff2",LINKER_SCRIPT)
+        elif self.test_name in tests_use_dff:
+           LINKER_SCRIPT = self.linkerScript_for_mem("dff",LINKER_SCRIPT)
+
         elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated  -I{verilog_path}/dv/ "
                  f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT},"
                  f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
         hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
         sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
-        #change linker script to dff2 
+       
-        if self.test_name in tests_use_dff2:
-            change_dff(str="> dff",new_str="> dff2",file_path=LINKER_SCRIPT)
         hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)}  efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
         self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
         self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
@@ -193,8 +193,24 @@ class RunTest:
         if hex_gen_state != 0 :
             print(f"fatal: Error when generating hex")
             sys.exit()
-        if self.test_name in tests_use_dff2:
+        
-            change_dff(str="> dff2",new_str="> dff",file_path=LINKER_SCRIPT)
+    #change linker script to for mem tests 
+    def linkerScript_for_mem(self,ram,LINKER_SCRIPT):
+        new_LINKER_SCRIPT = f"{self.cocotb_path}/{self.sim_path}/sections.lds"
+        shutil.copyfile(LINKER_SCRIPT, new_LINKER_SCRIPT)
+        if ram == "dff2":  
+            change_dff(str="> dff ",new_str="> dff2 ",file_path=new_LINKER_SCRIPT)
+            change_dff(str="> dff\n",new_str="> dff2\n",file_path=new_LINKER_SCRIPT)
+            change_dff(str="ORIGIN(dff)",new_str="ORIGIN(dff2)",file_path=LINKER_SCRIPT)
+            change_dff(str="LENGTH(dff)",new_str="LENGTH(dff2)",file_path=LINKER_SCRIPT)
+        elif ram == "dff":
+            change_dff(str="> dff2 ",new_str="> dff ",file_path=new_LINKER_SCRIPT)
+            change_dff(str="ORIGIN(dff2)",new_str="ORIGIN(dff)",file_path=LINKER_SCRIPT)
+            change_dff(str="LENGTH(dff2)",new_str="LENGTH(dff)",file_path=LINKER_SCRIPT)
+        else: 
+            print(f"ERROR: wrong trype of ram {ram} need to be used for now the oldy rams that can be used for flashing and data are dff and dff2")
+            sys.exit()
+        return new_LINKER_SCRIPT
 
     def cd_make(self):
         os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")