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Merge branch 'efabless:caravel_redesign' into caravel_redesign

This commit is contained in:
Mohamed Hosni 2022-10-10 05:08:33 -07:00 committed by GitHub
parent fa441babea ace9274138
commit 40098f693e
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26 changed files with 403377 additions and 110441 deletions
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@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
timestamp 1665259416
timestamp 1665336875
<< metal1 >>
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@ -1026,17 +1026,13 @@ rect 200206 42057 200258 42063
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<< via2 >>
rect 143407 40073 143519 40090
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<< metal3 >>
rect 40854 926876 46818 926940
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rect 313543 39718 313700 40044
rect 203740 30843 204105 31600
rect 314034 39976 314214 40321
rect 314045 39717 314202 40043
rect 313963 37372 314291 38153
rect 368334 40054 368514 40316
rect 368343 39718 368500 40044
rect 313340 30843 313705 31600
rect 368834 39976 369014 40321
rect 368845 39717 369002 40043
rect 368763 37372 369091 38153
rect 423134 40054 423314 40316
rect 423143 39718 423300 40044
rect 368140 30843 368505 31600
rect 423634 39976 423814 40321
rect 423645 39717 423802 40043
rect 423563 37372 423891 38153
rect 477934 40054 478114 40316
rect 477943 39718 478100 40044
rect 422940 30843 423305 31600
rect 478434 39976 478614 40321
rect 478445 39717 478602 40043
rect 478363 37372 478691 38153
rect 532734 40054 532914 40316
rect 532743 39718 532900 40044
rect 477740 30843 478105 31600
rect 533234 39976 533414 40321
rect 533245 39717 533402 40043
rect 533163 37372 533491 38153
rect 532540 30843 532905 31600
<< metal4 >>
@ -1647,62 +1652,62 @@ rect 40994 445596 43604 445704
rect 40994 440984 41122 445596
rect 43488 440984 43604 445596
rect 40994 440896 43604 440984
rect 149632 40321 149816 40323
rect 149132 40316 149316 40318
rect 149132 40054 149134 40316
rect 149314 40054 149316 40316
rect 149132 40052 149316 40054
rect 149632 39976 149634 40321
rect 149814 39976 149816 40321
rect 204432 40321 204616 40323
rect 203932 40316 204116 40318
rect 203932 40054 203934 40316
rect 204114 40054 204116 40316
rect 203932 40052 204116 40054
rect 149632 39974 149816 39976
rect 204432 39976 204434 40321
rect 204614 39976 204616 40321
rect 314032 40321 314216 40323
rect 313532 40316 313716 40318
rect 313532 40054 313534 40316
rect 313714 40054 313716 40316
rect 313532 40052 313716 40054
rect 204432 39974 204616 39976
rect 314032 39976 314034 40321
rect 314214 39976 314216 40321
rect 368832 40321 369016 40323
rect 368332 40316 368516 40318
rect 368332 40054 368334 40316
rect 368514 40054 368516 40316
rect 368332 40052 368516 40054
rect 314032 39974 314216 39976
rect 368832 39976 368834 40321
rect 369014 39976 369016 40321
rect 423632 40321 423816 40323
rect 423132 40316 423316 40318
rect 423132 40054 423134 40316
rect 423314 40054 423316 40316
rect 423132 40052 423316 40054
rect 368832 39974 369016 39976
rect 423632 39976 423634 40321
rect 423814 39976 423816 40321
rect 478432 40321 478616 40323
rect 477932 40316 478116 40318
rect 477932 40054 477934 40316
rect 478114 40054 478116 40316
rect 477932 40052 478116 40054
rect 423632 39974 423816 39976
rect 478432 39976 478434 40321
rect 478614 39976 478616 40321
rect 533232 40321 533416 40323
rect 532732 40316 532916 40318
rect 532732 40054 532734 40316
rect 532914 40054 532916 40316
rect 532732 40052 532916 40054
rect 478432 39974 478616 39976
rect 533232 39976 533234 40321
rect 533414 39976 533416 40321
rect 533232 39974 533416 39976
rect 149134 40044 149314 40149
rect 149134 39718 149143 40044
rect 149300 39718 149314 40044
rect 149134 39704 149314 39718
rect 149634 40043 149814 40149
rect 149634 39717 149645 40043
rect 149802 39717 149814 40043
rect 149634 39704 149814 39717
rect 203934 40044 204114 40148
rect 203934 39718 203943 40044
rect 204100 39718 204114 40044
rect 203934 39704 204114 39718
rect 204434 40043 204614 40148
rect 204434 39717 204445 40043
rect 204602 39717 204614 40043
rect 204434 39704 204614 39717
rect 313534 40044 313714 40148
rect 313534 39718 313543 40044
rect 313700 39718 313714 40044
rect 313534 39704 313714 39718
rect 314034 40043 314214 40148
rect 314034 39717 314045 40043
rect 314202 39717 314214 40043
rect 314034 39704 314214 39717
rect 368334 40044 368514 40148
rect 368334 39718 368343 40044
rect 368500 39718 368514 40044
rect 368334 39704 368514 39718
rect 368834 40043 369014 40148
rect 368834 39717 368845 40043
rect 369002 39717 369014 40043
rect 368834 39704 369014 39717
rect 423134 40044 423314 40148
rect 423134 39718 423143 40044
rect 423300 39718 423314 40044
rect 423134 39704 423314 39718
rect 423634 40043 423814 40148
rect 423634 39717 423645 40043
rect 423802 39717 423814 40043
rect 423634 39704 423814 39717
rect 477934 40044 478114 40148
rect 477934 39718 477943 40044
rect 478100 39718 478114 40044
rect 477934 39704 478114 39718
rect 478434 40043 478614 40148
rect 478434 39717 478445 40043
rect 478602 39717 478614 40043
rect 478434 39704 478614 39717
rect 532734 40044 532914 40148
rect 532734 39718 532743 40044
rect 532900 39718 532914 40044
rect 532734 39704 532914 39718
rect 533234 40043 533414 40148
rect 533234 39717 533245 40043
rect 533402 39717 533414 40043
rect 533234 39704 533414 39717
rect 132600 36323 132792 37013
<< via4 >>
rect 44294 922268 46702 926876
@ -4789,188 +4794,188 @@ timestamp 1663859327
transform -1 0 669200 0 -1 39593
box 0 0 4000 39593
use chip_io_gpio_connects chip_io_gpio_connects_0
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 0
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_1
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 45200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_2
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 90200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_3
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 135400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_4
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 180400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_5
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 225400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_6
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 270600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_7
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 447800
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_8
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 493000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_9
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 538000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_10
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 583200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_11
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 628200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_12
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 673200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_13
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 762400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_14
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 851600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_15
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 297600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_16
timestamp 1665248140
timestamp 1665336875
transform 0 -1 742000 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_17
timestamp 1665248140
timestamp 1665336875
transform 0 -1 640200 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_18
timestamp 1665248140
timestamp 1665336875
transform 0 -1 588800 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_19
timestamp 1665248140
timestamp 1665336875
transform 0 -1 499800 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_21
timestamp 1665248140
timestamp 1665336875
transform 0 -1 398000 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_22
timestamp 1665248140
timestamp 1665336875
transform 0 -1 346400 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_23
timestamp 1665248140
timestamp 1665336875
transform 0 -1 295000 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_24
timestamp 1665248140
timestamp 1665336875
transform 0 -1 243600 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_25
timestamp 1665248140
timestamp 1665336875
transform 0 -1 192200 1 0 320000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_26
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 1070200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_27
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 900400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_28
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 857200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_29
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 814000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_30
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 770800
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_31
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 727600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_32
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 684400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_33
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 641200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_34
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 513600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_35
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 470400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_36
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 427200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_37
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 384000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_38
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 340800
box 675407 99896 675887 115709
use sky130_ef_io__gpiov2_pad_wrapped clock_pad $PDKPATH/libs.ref/sky130_fd_io/maglef
timestamp 1663859327
transform -1 0 202400 0 -1 42193
box -32 0 16032 42193
use constant_block constant_block_0
timestamp 1665259416
transform -1 0 151016 0 1 39452
use constant_block constant_block_0 ../maglef
timestamp 1665254081
transform -1 0 151016 0 1 39652
box 0 496 2800 2224
use constant_block constant_block_1
timestamp 1665259416
transform -1 0 205816 0 1 39452
timestamp 1665254081
transform -1 0 205816 0 1 39652
box 0 496 2800 2224
use constant_block constant_block_2
timestamp 1665259416
transform -1 0 315416 0 1 39452
timestamp 1665254081
transform -1 0 315416 0 1 39652
box 0 496 2800 2224
use constant_block constant_block_3
timestamp 1665259416
transform -1 0 370216 0 1 39452
timestamp 1665254081
transform -1 0 370216 0 1 39652
box 0 496 2800 2224
use constant_block constant_block_4
timestamp 1665259416
transform -1 0 425016 0 1 39452
timestamp 1665254081
transform -1 0 425016 0 1 39652
box 0 496 2800 2224
use constant_block constant_block_5
timestamp 1665259416
transform -1 0 479816 0 1 39452
timestamp 1665254081
transform -1 0 479816 0 1 39652
box 0 496 2800 2224
use constant_block constant_block_6
timestamp 1665259416
transform -1 0 534616 0 1 39452
timestamp 1665254081
transform -1 0 534616 0 1 39652
box 0 496 2800 2224
use sky130_ef_io__disconnect_vdda_slice_5um disconnect_vdda_0 $PDKPATH/libs.ref/sky130_fd_io/maglef
timestamp 1663859327

631
mag/chip_io_alt.mag
View File

@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
timestamp 1665259295
timestamp 1665337263
<< metal1 >>
rect 41866 42181 41918 784786
rect 411070 42422 411076 42474
@ -88,6 +88,7 @@ rect 475769 42045 475775 42097
rect 514362 42045 516320 42097
rect 516372 42045 530517 42097
rect 530569 42045 530575 42097
rect 534760 42013 534812 42019
rect 186548 41961 189163 42013
rect 189215 41961 191003 42013
rect 191055 41961 192202 42013
@ -98,8 +99,8 @@ rect 197222 41961 197813 42013
rect 197865 41961 198368 42013
rect 198420 41961 200206 42013
rect 200258 41961 200857 42013
rect 200909 41961 202563 42013
rect 202615 41961 202621 42013
rect 200909 41961 205926 42013
rect 205978 41961 205984 42013
rect 295162 41961 297768 42013
rect 297820 41961 300804 42013
rect 300856 41961 301451 42013
@ -109,8 +110,8 @@ rect 302695 41961 305133 42013
rect 305185 41961 306418 42013
rect 306470 41961 308809 42013
rect 308861 41961 309452 42013
rect 309504 41961 311163 42013
rect 311215 41961 311221 42013
rect 309504 41961 315536 42013
rect 315588 41961 315594 42013
rect 349962 41961 352568 42013
rect 352620 41961 355600 42013
rect 355652 41961 356246 42013
@ -120,8 +121,8 @@ rect 357496 41961 359928 42013
rect 359980 41961 361217 42013
rect 361269 41961 363607 42013
rect 363659 41961 364252 42013
rect 364304 41961 365963 42013
rect 366015 41961 366021 42013
rect 364304 41961 370328 42013
rect 370380 41961 370386 42013
rect 404762 41961 407367 42013
rect 407419 41961 410398 42013
rect 410450 41961 411691 42013
@ -129,8 +130,8 @@ rect 411743 41961 414725 42013
rect 414777 41961 416013 42013
rect 416065 41961 418404 42013
rect 418456 41961 419045 42013
rect 419097 41961 420763 42013
rect 420815 41961 420821 42013
rect 419097 41961 425174 42013
rect 425226 41961 425232 42013
rect 459562 41961 462162 42013
rect 462214 41961 465201 42013
rect 465253 41961 466488 42013
@ -138,8 +139,8 @@ rect 466540 41961 469522 42013
rect 469574 41961 470810 42013
rect 470862 41961 473201 42013
rect 473253 41961 473849 42013
rect 473901 41961 475563 42013
rect 475615 41961 475621 42013
rect 473901 41961 479956 42013
rect 480008 41961 480014 42013
rect 514362 41961 516969 42013
rect 517021 41961 520004 42013
rect 520056 41961 521293 42013
@ -147,8 +148,8 @@ rect 521345 41961 524328 42013
rect 524380 41961 525615 42013
rect 525667 41961 528009 42013
rect 528061 41961 528652 42013
rect 528704 41961 530363 42013
rect 530415 41961 530421 42013
rect 528704 41961 534760 42013
rect 534760 41955 534812 41961
rect 186548 41877 187968 41929
rect 188020 41877 195973 41929
rect 196025 41877 202162 41929
@ -267,7 +268,7 @@ rect 197813 41961 197865 42013
rect 198368 41961 198420 42013
rect 200206 41961 200258 42013
rect 200857 41961 200909 42013
rect 202563 41961 202615 42013
rect 205926 41961 205978 42013
rect 297768 41961 297820 42013
rect 300804 41961 300856 42013
rect 301451 41961 301503 42013
@ -277,7 +278,7 @@ rect 305133 41961 305185 42013
rect 306418 41961 306470 42013
rect 308809 41961 308861 42013
rect 309452 41961 309504 42013
rect 311163 41961 311215 42013
rect 315536 41961 315588 42013
rect 352568 41961 352620 42013
rect 355600 41961 355652 42013
rect 356246 41961 356298 42013
@ -287,7 +288,7 @@ rect 359928 41961 359980 42013
rect 361217 41961 361269 42013
rect 363607 41961 363659 42013
rect 364252 41961 364304 42013
rect 365963 41961 366015 42013
rect 370328 41961 370380 42013
rect 407367 41961 407419 42013
rect 410398 41961 410450 42013
rect 411691 41961 411743 42013
@ -295,7 +296,7 @@ rect 414725 41961 414777 42013
rect 416013 41961 416065 42013
rect 418404 41961 418456 42013
rect 419045 41961 419097 42013
rect 420763 41961 420815 42013
rect 425174 41961 425226 42013
rect 462162 41961 462214 42013
rect 465201 41961 465253 42013
rect 466488 41961 466540 42013
@ -303,7 +304,7 @@ rect 469522 41961 469574 42013
rect 470810 41961 470862 42013
rect 473201 41961 473253 42013
rect 473849 41961 473901 42013
rect 475563 41961 475615 42013
rect 479956 41961 480008 42013
rect 516969 41961 517021 42013
rect 520004 41961 520056 42013
rect 521293 41961 521345 42013
@ -311,7 +312,7 @@ rect 524328 41961 524380 42013
rect 525615 41961 525667 42013
rect 528009 41961 528061 42013
rect 528652 41961 528704 42013
rect 530363 41961 530415 42013
rect 534760 41961 534812 42013
rect 187968 41877 188020 41929
rect 195973 41877 196025 41929
rect 296576 41877 296628 41929
@ -896,21 +897,25 @@ rect 200206 42013 200258 42019
rect 200206 41955 200258 41961
rect 200857 42013 200909 42019
rect 200857 41955 200909 41961
rect 202563 42013 202615 42019
rect 195973 41929 196025 41935
rect 195973 41871 196025 41877
rect 194688 41845 194740 41851
rect 194688 41787 194740 41793
rect 199012 41845 199064 41851
rect 199012 41787 199064 41793
rect 202563 40911 202615 41961
rect 202559 40902 202619 40911
rect 202559 40833 202619 40842
rect 202717 40738 202769 42045
rect 202717 40938 202769 42045
rect 297125 42097 297177 42103
rect 297125 42039 297177 42045
rect 299607 42097 299659 42103
rect 299607 42039 299659 42045
rect 205926 42013 205978 42019
rect 145830 40930 145888 40937
rect 145828 40928 145888 40930
rect 145828 40872 145830 40928
rect 145886 40872 145888 40928
rect 145828 40859 145888 40872
rect 202713 40929 202773 40938
rect 205926 40927 205978 41961
rect 297768 42013 297820 42019
rect 297768 41955 297820 41961
rect 300804 42013 300856 42019
@ -956,11 +961,7 @@ rect 358731 42181 358787 42196
rect 358731 42129 358732 42181
rect 358784 42129 358787 42181
rect 311317 42097 311369 42103
rect 311163 42013 311215 42019
rect 311163 40911 311215 41961
rect 311159 40902 311219 40911
rect 311159 40833 311219 40842
rect 311317 40738 311369 42045
rect 311317 40938 311369 42045
rect 351925 42097 351977 42103
rect 351925 42039 351977 42045
rect 354406 42097 354458 42103
@ -968,6 +969,9 @@ rect 358731 42093 358787 42129
rect 360570 42097 360622 42103
rect 354406 42039 354458 42045
rect 360570 42039 360622 42045
rect 315536 42013 315588 42019
rect 311313 40929 311373 40938
rect 315536 40937 315588 41961
rect 352568 42013 352620 42019
rect 352568 41955 352620 41961
rect 355600 42013 355652 42019
@ -1004,11 +1008,16 @@ rect 362412 41845 362464 41851
rect 362412 41787 362464 41793
rect 364895 41713 364951 42193
rect 366117 42097 366169 42103
rect 365963 42013 366015 42019
rect 365963 40911 366015 41961
rect 365959 40902 366019 40911
rect 365959 40833 366019 40842
rect 366117 40738 366169 42045
rect 366117 40938 366169 42045
rect 370328 42013 370380 42019
rect 202713 40860 202773 40869
rect 205922 40918 205982 40927
rect 145852 40090 145888 40859
rect 311313 40860 311373 40869
rect 315532 40928 315592 40937
rect 315532 40859 315592 40868
rect 366113 40929 366173 40938
rect 370328 40931 370380 41961
rect 404877 41845 404929 41851
rect 404877 41787 404929 41793
rect 405527 41713 405583 42193
@ -1060,12 +1069,10 @@ rect 417210 41845 417262 41851
rect 417210 41787 417262 41793
rect 419695 41776 419764 42193
rect 420917 42097 420969 42103
rect 420763 42013 420815 42019
rect 419695 41713 419751 41776
rect 420763 40911 420815 41961
rect 420759 40902 420819 40911
rect 420759 40833 420819 40842
rect 420917 40738 420969 42045
rect 420917 40938 420969 42045
rect 425174 42013 425226 42019
rect 425174 40939 425226 41961
rect 459678 41845 459730 41851
rect 459678 41787 459730 41793
rect 460327 41713 460383 42193
@ -1117,13 +1124,18 @@ rect 473849 41955 473901 41961
rect 472010 41845 472062 41851
rect 472010 41787 472062 41793
rect 474476 41762 474551 42193
rect 475717 42097 475769 42103
rect 474495 41713 474551 41762
rect 475563 42013 475615 42019
rect 475563 40911 475615 41961
rect 475559 40902 475619 40911
rect 475559 40833 475619 40842
rect 475717 40738 475769 42045
rect 475717 42097 475769 42103
rect 366113 40860 366173 40869
rect 370324 40922 370384 40931
rect 205922 40849 205982 40858
rect 370324 40853 370384 40862
rect 420913 40929 420973 40938
rect 420913 40860 420973 40869
rect 425170 40930 425230 40939
rect 475717 40938 475769 42045
rect 479956 42013 480008 42019
rect 479956 40941 480008 41961
rect 514487 41845 514539 41851
rect 514487 41787 514539 41793
rect 515127 41713 515183 42193
@ -1168,47 +1180,37 @@ rect 526810 41845 526862 41851
rect 526810 41787 526862 41793
rect 529295 41713 529351 42193
rect 530517 42097 530569 42103
rect 530363 42013 530415 42019
rect 530363 40911 530415 41961
rect 530359 40902 530419 40911
rect 530359 40833 530419 40842
rect 530517 40738 530569 42045
rect 145830 40730 145888 40737
rect 145828 40728 145888 40730
rect 145828 40672 145830 40728
rect 145886 40672 145888 40728
rect 145828 40659 145888 40672
rect 202713 40729 202773 40738
rect 202713 40660 202773 40669
rect 311313 40729 311373 40738
rect 311313 40660 311373 40669
rect 366113 40729 366173 40738
rect 366113 40660 366173 40669
rect 420913 40729 420973 40738
rect 420913 40660 420973 40669
rect 475713 40729 475773 40738
rect 475713 40660 475773 40669
rect 530513 40729 530573 40738
rect 530513 40660 530573 40669
rect 145852 40090 145888 40659
rect 425170 40861 425230 40870
rect 475713 40929 475773 40938
rect 475713 40860 475773 40869
rect 479952 40932 480012 40941
rect 530517 40938 530569 42045
rect 534754 41961 534760 42013
rect 534812 41961 534818 42013
rect 479952 40863 480012 40872
rect 530513 40929 530573 40938
rect 534760 40937 534812 41961
rect 530513 40860 530573 40869
rect 534756 40928 534816 40937
rect 534756 40859 534816 40868
rect 145828 40030 145837 40090
rect 145897 40030 145906 40090
<< via2 >>
rect 143407 40029 143519 40046
rect 143407 39990 143519 40029
rect 202559 40842 202619 40902
rect 311159 40842 311219 40902
rect 365959 40842 366019 40902
rect 420759 40842 420819 40902
rect 475559 40842 475619 40902
rect 530359 40842 530419 40902
rect 145830 40672 145886 40728
rect 202713 40669 202773 40729
rect 311313 40669 311373 40729
rect 366113 40669 366173 40729
rect 420913 40669 420973 40729
rect 475713 40669 475773 40729
rect 530513 40669 530573 40729
rect 145830 40872 145886 40928
rect 202713 40869 202773 40929
rect 205922 40858 205982 40918
rect 311313 40869 311373 40929
rect 315532 40868 315592 40928
rect 366113 40869 366173 40929
rect 370324 40862 370384 40922
rect 420913 40869 420973 40929
rect 425170 40870 425230 40930
rect 475713 40869 475773 40929
rect 479952 40872 480012 40932
rect 530513 40869 530573 40929
rect 534756 40868 534816 40928
rect 145837 40030 145897 40090
<< metal3 >>
rect 82144 997600 87144 1014070
@ -1272,67 +1274,77 @@ rect 40940 445574 46824 445700
rect 40940 441014 41100 445574
rect 43486 441014 46824 445574
rect 40940 440900 46824 441014
rect 202554 40902 202624 40907
rect 311154 40902 311224 40907
rect 365954 40902 366024 40907
rect 420754 40902 420824 40907
rect 475554 40902 475624 40907
rect 530354 40902 530424 40907
rect 202554 40842 202559 40902
rect 202619 40842 204878 40902
rect 202554 40837 202624 40842
rect 145825 40730 145891 40733
rect 145825 40728 148252 40730
rect 145825 40672 145830 40728
rect 145886 40672 148252 40728
rect 145825 40670 148252 40672
rect 202708 40729 202778 40734
rect 145825 40667 145891 40670
rect 202708 40669 202713 40729
rect 202773 40669 203064 40729
rect 204818 40669 204878 40842
rect 311154 40842 311159 40902
rect 311219 40842 314473 40902
rect 311154 40837 311224 40842
rect 311308 40729 311378 40734
rect 311308 40669 311313 40729
rect 311373 40669 312684 40729
rect 202708 40664 202778 40669
rect 311308 40664 311378 40669
rect 314413 40660 314473 40842
rect 365954 40842 365959 40902
rect 366019 40842 369270 40902
rect 365954 40837 366024 40842
rect 366108 40729 366178 40734
rect 366108 40669 366113 40729
rect 366173 40669 367484 40729
rect 369210 40672 369270 40842
rect 420754 40842 420759 40902
rect 420819 40842 424060 40902
rect 420754 40837 420824 40842
rect 420908 40729 420978 40734
rect 420908 40669 420913 40729
rect 420973 40669 422262 40729
rect 366108 40664 366178 40669
rect 420908 40664 420978 40669
rect 424000 40668 424060 40842
rect 475554 40842 475559 40902
rect 475619 40842 478875 40902
rect 475554 40837 475624 40842
rect 475708 40729 475778 40734
rect 475708 40669 475713 40729
rect 475773 40669 477055 40729
rect 475708 40664 475778 40669
rect 478815 40668 478875 40842
rect 530354 40842 530359 40902
rect 530419 40842 533657 40902
rect 530354 40837 530424 40842
rect 530508 40729 530578 40734
rect 530508 40669 530513 40729
rect 530573 40669 531856 40729
rect 530508 40664 530578 40669
rect 533597 40668 533657 40842
rect 148901 40272 149351 40294
rect 479947 40936 480017 40937
rect 145825 40930 145891 40933
rect 145825 40928 148252 40930
rect 145825 40872 145830 40928
rect 145886 40872 148252 40928
rect 145825 40870 148252 40872
rect 202708 40929 202778 40934
rect 311308 40929 311378 40934
rect 145825 40867 145891 40870
rect 202708 40869 202713 40929
rect 202773 40869 203064 40929
rect 205917 40922 205987 40923
rect 205764 40918 205988 40922
rect 202708 40864 202778 40869
rect 205764 40862 205922 40918
rect 205917 40858 205922 40862
rect 205982 40862 205988 40918
rect 311308 40869 311313 40929
rect 311373 40869 312684 40929
rect 315527 40928 315597 40933
rect 315527 40926 315532 40928
rect 311308 40864 311378 40869
rect 315382 40868 315532 40926
rect 315592 40926 315597 40928
rect 366108 40929 366178 40934
rect 420908 40929 420978 40934
rect 425165 40930 425235 40935
rect 315592 40868 315600 40926
rect 315382 40866 315600 40868
rect 366108 40869 366113 40929
rect 366173 40869 367484 40929
rect 370319 40924 370389 40927
rect 370156 40922 370389 40924
rect 315527 40863 315597 40866
rect 366108 40864 366178 40869
rect 370156 40864 370324 40922
rect 370319 40862 370324 40864
rect 370384 40862 370389 40922
rect 420908 40869 420913 40929
rect 420973 40869 422262 40929
rect 425165 40928 425170 40930
rect 424966 40870 425170 40928
rect 425230 40928 425235 40930
rect 475708 40929 475778 40934
rect 479766 40932 480018 40936
rect 425230 40870 425236 40928
rect 420908 40864 420978 40869
rect 424966 40868 425236 40870
rect 475708 40869 475713 40929
rect 475773 40869 477055 40929
rect 479766 40876 479952 40932
rect 479947 40872 479952 40876
rect 480012 40876 480018 40932
rect 530508 40929 530578 40934
rect 480012 40872 480017 40876
rect 425165 40865 425235 40868
rect 475708 40864 475778 40869
rect 479947 40867 480017 40872
rect 530508 40869 530513 40929
rect 530573 40869 531856 40929
rect 534751 40928 534821 40933
rect 534751 40924 534756 40928
rect 530508 40864 530578 40869
rect 534576 40868 534756 40924
rect 534816 40924 534821 40928
rect 534816 40868 534822 40924
rect 534576 40864 534822 40868
rect 534751 40863 534821 40864
rect 205982 40858 205987 40862
rect 205917 40853 205987 40858
rect 370319 40857 370389 40862
rect 133094 40114 144010 40174
rect 133094 39940 133154 40114
rect 143407 40051 143519 40053
@ -1345,97 +1357,98 @@ rect 145832 40090 145902 40104
rect 145832 40030 145837 40090
rect 145897 40030 145902 40090
rect 145832 39938 145902 40030
rect 148901 40010 149134 40272
rect 149314 40010 149351 40272
rect 148901 31556 149351 40010
rect 149537 40277 149918 40298
rect 149537 39932 149634 40277
rect 149814 39932 149918 40277
rect 149537 38109 149918 39932
rect 148901 40012 149351 40022
rect 148901 39694 149144 40012
rect 149304 39694 149351 40012
rect 148901 31556 149351 39694
rect 149537 40010 149918 40022
rect 149537 39692 149644 40010
rect 149804 39692 149918 40010
rect 149537 38109 149918 39692
rect 149537 37328 149563 38109
rect 149891 37328 149918 38109
rect 149537 37296 149918 37328
rect 203701 40272 204151 40294
rect 203701 40010 203934 40272
rect 204114 40010 204151 40272
rect 203701 40012 204151 40022
rect 203701 39694 203944 40012
rect 204104 39694 204151 40012
rect 148901 30799 148940 31556
rect 149305 30799 149351 31556
rect 148901 30762 149351 30799
rect 203701 31556 204151 40010
rect 204337 40277 204718 40298
rect 204337 39932 204434 40277
rect 204614 39932 204718 40277
rect 204337 38109 204718 39932
rect 203701 31556 204151 39694
rect 204337 40010 204718 40022
rect 204337 39692 204444 40010
rect 204604 39692 204718 40010
rect 204337 38109 204718 39692
rect 204337 37328 204363 38109
rect 204691 37328 204718 38109
rect 204337 37296 204718 37328
rect 313301 40272 313751 40294
rect 313301 40010 313534 40272
rect 313714 40010 313751 40272
rect 313301 40012 313751 40022
rect 313301 39694 313544 40012
rect 313704 39694 313751 40012
rect 203701 30799 203740 31556
rect 204105 30799 204151 31556
rect 203701 30762 204151 30799
rect 313301 31556 313751 40010
rect 313937 40277 314318 40298
rect 313937 39932 314034 40277
rect 314214 39932 314318 40277
rect 313937 38109 314318 39932
rect 313301 31556 313751 39694
rect 313937 40010 314318 40022
rect 313937 39692 314044 40010
rect 314204 39692 314318 40010
rect 313937 38109 314318 39692
rect 313937 37328 313963 38109
rect 314291 37328 314318 38109
rect 313937 37296 314318 37328
rect 368101 40272 368551 40294
rect 368101 40010 368334 40272
rect 368514 40010 368551 40272
rect 368101 40012 368551 40022
rect 368101 39694 368344 40012
rect 368504 39694 368551 40012
rect 313301 30799 313340 31556
rect 313705 30799 313751 31556
rect 313301 30762 313751 30799
rect 368101 31556 368551 40010
rect 368737 40277 369118 40298
rect 368737 39932 368834 40277
rect 369014 39932 369118 40277
rect 368737 38109 369118 39932
rect 368101 31556 368551 39694
rect 368737 40010 369118 40022
rect 368737 39692 368844 40010
rect 369004 39692 369118 40010
rect 368737 38109 369118 39692
rect 368737 37328 368763 38109
rect 369091 37328 369118 38109
rect 368737 37296 369118 37328
rect 422901 40272 423351 40294
rect 422901 40010 423134 40272
rect 423314 40010 423351 40272
rect 422901 40012 423351 40022
rect 422901 39694 423144 40012
rect 423304 39694 423351 40012
rect 368101 30799 368140 31556
rect 368505 30799 368551 31556
rect 368101 30762 368551 30799
rect 422901 31556 423351 40010
rect 423537 40277 423918 40298
rect 423537 39932 423634 40277
rect 423814 39932 423918 40277
rect 423537 38109 423918 39932
rect 422901 31556 423351 39694
rect 423537 40010 423918 40022
rect 423537 39692 423644 40010
rect 423804 39692 423918 40010
rect 423537 38109 423918 39692
rect 423537 37328 423563 38109
rect 423891 37328 423918 38109
rect 423537 37296 423918 37328
rect 477701 40272 478151 40294
rect 477701 40010 477934 40272
rect 478114 40010 478151 40272
rect 477701 40012 478151 40022
rect 477701 39694 477944 40012
rect 478104 39694 478151 40012
rect 422901 30799 422940 31556
rect 423305 30799 423351 31556
rect 422901 30762 423351 30799
rect 477701 31556 478151 40010
rect 478337 40277 478718 40298
rect 478337 39932 478434 40277
rect 478614 39932 478718 40277
rect 478337 38109 478718 39932
rect 477701 31556 478151 39694
rect 478337 40010 478718 40022
rect 478337 39692 478444 40010
rect 478604 39692 478718 40010
rect 478337 38109 478718 39692
rect 478337 37328 478363 38109
rect 478691 37328 478718 38109
rect 478337 37296 478718 37328
rect 532501 40272 532951 40294
rect 532501 40010 532734 40272
rect 532914 40010 532951 40272
rect 532501 40012 532951 40022
rect 532501 39694 532744 40012
rect 532904 39694 532951 40012
rect 477701 30799 477740 31556
rect 478105 30799 478151 31556
rect 477701 30762 478151 30799
rect 532501 31556 532951 40010
rect 533137 40277 533518 40298
rect 533137 39932 533234 40277
rect 533414 39932 533518 40277
rect 533137 38109 533518 39932
rect 532501 31556 532951 39694
rect 533137 40010 533518 40022
rect 533137 39692 533244 40010
rect 533404 39692 533518 40010
rect 533137 38109 533518 39692
rect 533137 37328 533163 38109
rect 533491 37328 533518 38109
rect 533137 37296 533518 37328
@ -1455,32 +1468,32 @@ rect 670960 460006 673300 464530
rect 41108 451068 43494 455628
rect 44290 446104 46656 450534
rect 41100 441014 43486 445574
rect 149134 40010 149314 40272
rect 149634 39932 149814 40277
rect 149144 39694 149304 40012
rect 149644 39692 149804 40010
rect 149563 37328 149891 38109
rect 203934 40010 204114 40272
rect 203944 39694 204104 40012
rect 148940 30799 149305 31556
rect 204434 39932 204614 40277
rect 204444 39692 204604 40010
rect 204363 37328 204691 38109
rect 313534 40010 313714 40272
rect 313544 39694 313704 40012
rect 203740 30799 204105 31556
rect 314034 39932 314214 40277
rect 314044 39692 314204 40010
rect 313963 37328 314291 38109
rect 368334 40010 368514 40272
rect 368344 39694 368504 40012
rect 313340 30799 313705 31556
rect 368834 39932 369014 40277
rect 368844 39692 369004 40010
rect 368763 37328 369091 38109
rect 423134 40010 423314 40272
rect 423144 39694 423304 40012
rect 368140 30799 368505 31556
rect 423634 39932 423814 40277
rect 423644 39692 423804 40010
rect 423563 37328 423891 38109
rect 477934 40010 478114 40272
rect 477944 39694 478104 40012
rect 422940 30799 423305 31556
rect 478434 39932 478614 40277
rect 478444 39692 478604 40010
rect 478363 37328 478691 38109
rect 532734 40010 532914 40272
rect 532744 39694 532904 40012
rect 477740 30799 478105 31556
rect 533234 39932 533414 40277
rect 533244 39692 533404 40010
rect 533163 37328 533491 38109
rect 532540 30799 532905 31556
<< metal4 >>
@ -1536,62 +1549,62 @@ rect 40992 445574 43578 445690
rect 40992 441014 41100 445574
rect 43486 441014 43578 445574
rect 40992 440914 43578 441014
rect 149632 40277 149816 40279
rect 149132 40272 149316 40274
rect 149132 40010 149134 40272
rect 149314 40010 149316 40272
rect 149132 40008 149316 40010
rect 149632 39932 149634 40277
rect 149814 39932 149816 40277
rect 204432 40277 204616 40279
rect 203932 40272 204116 40274
rect 203932 40010 203934 40272
rect 204114 40010 204116 40272
rect 203932 40008 204116 40010
rect 149632 39930 149816 39932
rect 204432 39932 204434 40277
rect 204614 39932 204616 40277
rect 314032 40277 314216 40279
rect 313532 40272 313716 40274
rect 313532 40010 313534 40272
rect 313714 40010 313716 40272
rect 313532 40008 313716 40010
rect 204432 39930 204616 39932
rect 314032 39932 314034 40277
rect 314214 39932 314216 40277
rect 368832 40277 369016 40279
rect 368332 40272 368516 40274
rect 368332 40010 368334 40272
rect 368514 40010 368516 40272
rect 368332 40008 368516 40010
rect 314032 39930 314216 39932
rect 368832 39932 368834 40277
rect 369014 39932 369016 40277
rect 423632 40277 423816 40279
rect 423132 40272 423316 40274
rect 423132 40010 423134 40272
rect 423314 40010 423316 40272
rect 423132 40008 423316 40010
rect 368832 39930 369016 39932
rect 423632 39932 423634 40277
rect 423814 39932 423816 40277
rect 478432 40277 478616 40279
rect 477932 40272 478116 40274
rect 477932 40010 477934 40272
rect 478114 40010 478116 40272
rect 477932 40008 478116 40010
rect 423632 39930 423816 39932
rect 478432 39932 478434 40277
rect 478614 39932 478616 40277
rect 533232 40277 533416 40279
rect 532732 40272 532916 40274
rect 532732 40010 532734 40272
rect 532914 40010 532916 40272
rect 532732 40008 532916 40010
rect 478432 39930 478616 39932
rect 533232 39932 533234 40277
rect 533414 39932 533416 40277
rect 533232 39930 533416 39932
rect 149134 40012 149314 40108
rect 149134 39694 149144 40012
rect 149304 39694 149314 40012
rect 149134 39682 149314 39694
rect 149634 40010 149814 40108
rect 149634 39692 149644 40010
rect 149804 39692 149814 40010
rect 149634 39682 149814 39692
rect 203934 40012 204114 40104
rect 203934 39694 203944 40012
rect 204104 39694 204114 40012
rect 203934 39682 204114 39694
rect 204434 40010 204614 40104
rect 204434 39692 204444 40010
rect 204604 39692 204614 40010
rect 204434 39682 204614 39692
rect 313534 40012 313714 40104
rect 313534 39694 313544 40012
rect 313704 39694 313714 40012
rect 313534 39682 313714 39694
rect 314034 40010 314214 40104
rect 314034 39692 314044 40010
rect 314204 39692 314214 40010
rect 314034 39682 314214 39692
rect 368334 40012 368514 40104
rect 368334 39694 368344 40012
rect 368504 39694 368514 40012
rect 368334 39682 368514 39694
rect 368834 40010 369014 40104
rect 368834 39692 368844 40010
rect 369004 39692 369014 40010
rect 368834 39682 369014 39692
rect 423134 40012 423314 40104
rect 423134 39694 423144 40012
rect 423304 39694 423314 40012
rect 423134 39682 423314 39694
rect 423634 40010 423814 40104
rect 423634 39692 423644 40010
rect 423804 39692 423814 40010
rect 423634 39682 423814 39692
rect 477934 40012 478114 40104
rect 477934 39694 477944 40012
rect 478104 39694 478114 40012
rect 477934 39682 478114 39694
rect 478434 40010 478614 40104
rect 478434 39692 478444 40010
rect 478604 39692 478614 40010
rect 478434 39682 478614 39692
rect 532734 40012 532914 40104
rect 532734 39694 532744 40012
rect 532904 39694 532914 40012
rect 532734 39682 532914 39694
rect 533234 40010 533414 40104
rect 533234 39692 533244 40010
rect 533404 39692 533414 40010
rect 533234 39682 533414 39692
rect 132600 36323 132792 37013
<< via4 >>
rect 44296 922264 46674 926816
@ -4570,144 +4583,144 @@ timestamp 1663859327
transform -1 0 669200 0 -1 39593
box 0 0 4000 39593
use chip_io_gpio_connects chip_io_gpio_connects_0
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 0
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_1
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 45200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_2
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 90200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_3
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 135400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_4
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 180400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_5
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 225400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_6
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 270600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_7
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 447800
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_8
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 493000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_9
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 538000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_10
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 583200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_11
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 628200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_12
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 673200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_13
timestamp 1665248140
timestamp 1665336875
transform 1 0 0 0 1 762400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_15
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 297600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_27
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 900400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_28
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 857200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_29
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 814000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_30
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 770800
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_31
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 727600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_32
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 684400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_33
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 641200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_34
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 513600
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_35
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 470400
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_36
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 427200
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_37
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 384000
box 675407 99896 675887 115709
use chip_io_gpio_connects chip_io_gpio_connects_38
timestamp 1665248140
timestamp 1665336875
transform -1 0 717600 0 -1 340800
box 675407 99896 675887 115709
use sky130_ef_io__gpiov2_pad_wrapped clock_pad $PDKPATH/libs.ref/sky130_fd_io/maglef
timestamp 1663859327
transform -1 0 202400 0 -1 42193
box -32 0 16032 42193
use constant_block constant_block_0
timestamp 1665259295
transform -1 0 151016 0 1 39408
use constant_block constant_block_0 ../maglef
timestamp 1665254081
transform -1 0 151016 0 1 39608
box 0 496 2800 2224
use constant_block constant_block_1
timestamp 1665259295
transform -1 0 205816 0 1 39408
timestamp 1665254081
transform -1 0 205816 0 1 39608
box 0 496 2800 2224
use constant_block constant_block_2
timestamp 1665259295
transform -1 0 315416 0 1 39408
timestamp 1665254081
transform -1 0 315416 0 1 39608
box 0 496 2800 2224
use constant_block constant_block_3
timestamp 1665259295
transform -1 0 370216 0 1 39408
timestamp 1665254081
transform -1 0 370216 0 1 39608
box 0 496 2800 2224
use constant_block constant_block_4
timestamp 1665259295
transform -1 0 425016 0 1 39408
timestamp 1665254081
transform -1 0 425016 0 1 39608
box 0 496 2800 2224
use constant_block constant_block_5
timestamp 1665259295
transform -1 0 479816 0 1 39408
timestamp 1665254081
transform -1 0 479816 0 1 39608
box 0 496 2800 2224
use constant_block constant_block_6
timestamp 1665259295
transform -1 0 534616 0 1 39408
timestamp 1665254081
transform -1 0 534616 0 1 39608
box 0 496 2800 2224
use sky130_ef_io__disconnect_vdda_slice_5um disconnect_vdda_0 $PDKPATH/libs.ref/sky130_fd_io/maglef
timestamp 1663859327

4
mag/chip_io_gpio_connects.mag
View File

@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
timestamp 1665248140
timestamp 1665336875
<< checkpaint >>
rect 675407 99896 675887 115709
<< metal1 >>
@ -60,4 +60,6 @@ rect 675407 100284 675586 100339
rect 675638 100339 675644 100456
rect 675638 100284 675887 100339
rect 675407 100283 675887 100284
<< properties >>
string flatten true
<< end >>

1
manifest
View File

@ -8,6 +8,7 @@ a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
b4b8fecbdc56c5d8acca9b904415f30e3159d1d5 verilog/rtl/caravel.v
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
82d3766e5ed2a29ff06150aab1c7b0f4c5651551 verilog/rtl/chip_io.v
97c958944dd74a87f75d9fe2309837e567468722 verilog/rtl/chip_io_alt.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v

25
openlane/Makefile
View File

@ -15,9 +15,10 @@
MAKEFLAGS+=--warn-undefined-variables
export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
export OPENLANE_RUN_TAG ?= $(shell date '+%y_%m_%d_%H_%M')
OPENLANE_TAG ?= 2021.11.23_01.42.34
OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
IT_SCRIPT ?= ./interactive.tcl
designs = $(shell find * -maxdepth 0 -type d)
current_design = null
@ -26,9 +27,14 @@ openlane_cmd = \
-design $$(realpath ./$*) \
-save_path $$(realpath ..) \
-save \
-tag $(OPENLANE_RUN_TAG) \
-OPENLANE_RUN_TAG $(OPENLAN_RUN_TAG) \
-verbose 1 \
-overwrite"
openlane_cmd_interactive = "flow.tcl -it -file $$(realpath ./$*/interactive.tcl)"
openlane_cmd_interactive = "flow.tcl -ignore_mismatches -it -file $$(realpath ./$*/$(IT_SCRIPT))"
openlane_cmd_regression = "cd /openlane && ./run_designs.py \
--regression $$(realpath ./$*/regression.config) \
--threads 6 \
$$(realpath ./$*)"
docker_mounts = \
-v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
@ -45,6 +51,12 @@ docker_env = \
-e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG) \
-w $(PWD)
ifneq ($(OPENLANE_ROOT),)
$(info openlane $(OPENLANE_ROOT))
docker_mounts += -v $(OPENLANE_ROOT):/openlane
docker_mounts += -v $(OPENLANE_ROOT):/openLANE_flow
endif
ifneq ($(MCW_ROOT),)
docker_env += -e MCW_ROOT=$(MCW_ROOT)
docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
@ -60,6 +72,13 @@ docker_run = \
list:
@echo $(designs)
regression-designs=$(designs:%=%-regression)
.PHONY: $(regression-designs)
$(regression-designs): %-regression: ./%/regression.config
$(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_regression)
.PHONY: $(designs)
$(designs) : % : ./%/config.tcl
ifneq (,$(wildcard ./$(MAKECMDGOALS)/interactive.tcl)))

BIN
openlane/caravel/caravel_power_routing-shifted.gds Normal file
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Binary file not shown.

5347
openlane/caravel/caravel_power_routing-shifted.lef Normal file
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File diff suppressed because it is too large Load Diff

50
openlane/caravel/config.tcl
View File

@ -14,15 +14,15 @@
# SPDX-License-Identifier: Apache-2.0
# User config
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) caravel
set ::env(ROUTING_CORES) 50
set ::env(STD_CELL_LIBRARY_OPT) "sky130_fd_sc_hd"
set verilog_root $script_dir/../../verilog/
set lef_root $script_dir/../../lef/
set gds_root $script_dir/../../gds/
set verilog_root $::env(CARAVEL_ROOT)/verilog/
set lef_root $::env(CARAVEL_ROOT)/lef/
set gds_root $::env(CARAVEL_ROOT)/gds/
set mgmt_area_verilog_root $::env(MCW_ROOT)/verilog/
set mgmt_area_lef_root $::env(MCW_ROOT)/lef/
@ -50,10 +50,12 @@ set ::env(VERILOG_FILES_BLACKBOX) "\
$verilog_root/rtl/simple_por.v\
$verilog_root/rtl/spare_logic_block.v\
$verilog_root/rtl/xres_buf.v \
$verilog_root/rtl/caravel_power_routing.v \
$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
"
set ::env(EXTRA_LEFS) "\
$::env(DESIGN_DIR)/caravel_power_routing-shifted.lef \
$lef_root/chip_io.lef \
$lef_root/user_project_wrapper.lef \
$lef_root/mgmt_protect.lef \
@ -70,12 +72,11 @@ set ::env(EXTRA_LEFS) "\
"
set ::env(EXTRA_GDS_FILES) "\
$::env(DESIGN_DIR)/caravel_power_routing-shifted.gds \
$gds_root/chip_io.gds \
$gds_root/user_project_wrapper.gds \
$gds_root/mgmt_protect.gds \
$gds_root/gpio_control_block.gds \
$gds_root/gpio_defaults_block.gds \
$gds_root/user_id_programming.gds \
$gds_root/housekeeping.gds \
$gds_root/digital_pll.gds \
$gds_root/caravel_clocking.gds \
@ -97,7 +98,7 @@ set ::env(LEC_ENABLE) 0
set ::env(FP_SIZING) absolute
set fd [open "$script_dir/../chip_dimensions.txt" "r"]
set fd [open "$::env(DESIGN_DIR)/../chip_dimensions.txt" "r"]
set ::env(DIE_AREA) [read $fd]
close $fd
@ -109,21 +110,16 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(GLB_RT_OVERFLOW_ITERS) 50
set ::env(GLB_RT_TILES) 30
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6
#set ::env(RT_MIN_LAYER) met1
#set ::env(RT_MAX_LAYER) met5
set ::env(GLB_RT_ADJUSTMENT) "0"
set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
set ::env(GLB_RT_L6_ADJUSTMENT) "0"
#set ::env(GLB_RT_ADJUSTMENT) "0"
#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
#set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
#set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
#set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
#set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
#set ::env(GLB_RT_L2_ADJUSTMENT) "0"
#set ::env(GLB_RT_L3_ADJUSTMENT) "0"
@ -138,7 +134,7 @@ set ::env(GLB_RT_L6_ADJUSTMENT) "0"
#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
# set ::env(ROUTING_OPT_ITERS) 7
# set ::env(GLB_RT_UNIDIRECTIONAL) 0
set ::env(GLB_RT_UNIDIRECTIONAL) 0
set ::env(FILL_INSERTION) 0
@ -151,5 +147,17 @@ set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
set ::env(QUIT_ON_TR_DRC) 0
set ::env(QUIT_ON_LVS_ERROR) 0
#set ::env(TRACKS_INFO_FILE) $script_dir/tracks.info
#set ::env(TRACKS_INFO_FILE) $::env(DESIGN_DIR)/tracks.info
#
set ::env(ROUTING_OPT_ITERS) 100
set ::env(TECH_LEF) $::env(DESIGN_DIR)/sky130_fd_sc_hd.tlef
set ::env(GLB_RT_ADJUSTMENT) "0"
set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
set ::env(GLB_RT_L2_ADJUSTMENT) "0.2"
set ::env(GLB_RT_L3_ADJUSTMENT) "0.45"
set ::env(GLB_RT_L4_ADJUSTMENT) "0.45"
set ::env(GLB_RT_L5_ADJUSTMENT) "0.45"
set ::env(GLB_RT_L6_ADJUSTMENT) "0"

265
openlane/caravel/interactive-old.tcl Normal file
View File

@ -0,0 +1,265 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
set script_dir [file dirname [file normalize [info script]]]
set save_path $::env(CARAVEL_ROOT)
# FOR LVS AND CREATING PORT LABELS
# ACTUAL CHIP INTEGRATION
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
prep -design $SCRIPT_DIR -tag caravel_lvs -overwrite --verbose 2
set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
verilog_elaborate
file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
prep -ignore_mismatches -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 2
set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(GLB_RT_OVERFLOW_ITERS) 50
set ::env(GLB_RT_TILES) 30
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6
exec rm -rf $SCRIPT_DIR/runs/caravel
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/caravel
file copy -force $::env(CARAVEL_ROOT)/openlane/caravel/runs/caravel_lvs/tmp/lvs.v $::env(RUN_DIR)/caravel.v
set ::env(SYNTH_DEFINES) "TOP_ROUTING"
verilog_elaborate
#logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v
init_floorplan
#set ::env(GLB_RT_ADJUSTMENT) "0"
#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
#set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
#set ::env(GLB_RT_L3_ADJUSTMENT) "0.3"
#set ::env(GLB_RT_L4_ADJUSTMENT) "0.3"
#set ::env(GLB_RT_L5_ADJUSTMENT) "0.3"
#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
set mprj_x 326.540
set mprj_y 1393.590
set soc_x 260.170
set soc_y 265.010
add_macro_placement caravel_power_routing 30.11 169.5 N
add_macro_placement padframe 0 0 N
add_macro_placement soc $soc_x $soc_y N
add_macro_placement housekeeping 2962.17 500.010 N
add_macro_placement mprj $mprj_x $mprj_y N
add_macro_placement mgmt_buffers 640.900 1160.180 N
# add_macro_placement mgmt_buffers 1060.850 1234.090 N
add_macro_placement rstb_level 708.550 235.440 S
add_macro_placement user_id_value 3283.120 440.630 N
add_macro_placement por 3250.730 234.721 MX
add_macro_placement pll 3140.730 404.721 N
add_macro_placement spare_logic\\\[0\\\] 443.16 1162.64 N
add_macro_placement spare_logic\\\[1\\\] 446.75500 1243.36700 N
add_macro_placement spare_logic\\\[2\\\] 2875.72600 1234.93300 N
add_macro_placement spare_logic\\\[3\\\] 3067.79200 1229.28000 N
add_macro_placement clock_ctrl 3133.820 316.420 N
#add_macro_placement clocking 1028.730 27.440 N
# west
set west_x 38.155
add_macro_placement "gpio_control_bidir_2\\\[2\\\]" $west_x 1013.000 R0
add_macro_placement "gpio_defaults_block_37" [expr $west_x + 3.6815559] [expr 1013.000 + 65] R0
add_macro_placement "gpio_control_bidir_2\\\[1\\\]" $west_x 1229.000 R0
add_macro_placement "gpio_defaults_block_36" [expr $west_x + 3.6815559] [expr 1229.000 + 65] R0
add_macro_placement "gpio_control_bidir_2\\\[0\\\]" $west_x 1445.000 R0
add_macro_placement "gpio_defaults_block_35" [expr $west_x + 3.6815559] [expr 1445.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[15\\\]" $west_x 1661.000 R0
add_macro_placement "gpio_defaults_block_34" [expr $west_x + 3.6815559] [expr 1661.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[14\\\]" $west_x 1877.000 R0
add_macro_placement "gpio_defaults_block_33" [expr $west_x + 3.6815559] [expr 1877.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[13\\\]" $west_x 2093.000 R0
add_macro_placement "gpio_defaults_block_32" [expr $west_x + 3.6815559] [expr 2093.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[12\\\]" $west_x 2731.000 R0
add_macro_placement "gpio_defaults_block_31" [expr $west_x + 3.6815559] [expr 2731.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[11\\\]" $west_x 2947.000 R0
add_macro_placement "gpio_defaults_block_30" [expr $west_x + 3.6815559] [expr 2947.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[10\\\]" $west_x 3163.000 R0
add_macro_placement "gpio_defaults_block_29" [expr $west_x + 3.6815559] [expr 3163.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[9\\\]" $west_x 3379.000 R0
add_macro_placement "gpio_defaults_block_28" [expr $west_x + 3.6815559] [expr 3379.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[8\\\]" $west_x 3595.000 R0
add_macro_placement "gpio_defaults_block_27" [expr $west_x + 3.6815559] [expr 3595.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[7\\\]" $west_x 3811.000 R0
add_macro_placement "gpio_defaults_block_26" [expr $west_x + 3.6815559] [expr 3811.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[6\\\]" $west_x 4027.000 R0
add_macro_placement "gpio_defaults_block_25" [expr $west_x + 3.6815559] [expr 4027.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[5\\\]" $west_x 4656.000 R0
add_macro_placement "gpio_defaults_block_24" [expr $west_x + 3.6815559] [expr 4656.000 + 65] R0
# north
set north_y 4980.385
add_macro_placement "gpio_control_in_2\\\[4\\\]" 486.000 $north_y R270
add_macro_placement "gpio_defaults_block_23" [expr 486.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[3\\\]" 743.000 $north_y R270
add_macro_placement "gpio_defaults_block_22" [expr 743.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[2\\\]" 1000.000 $north_y R270
add_macro_placement "gpio_defaults_block_21" [expr 1000.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[1\\\]" 1257.000 $north_y R270
add_macro_placement "gpio_defaults_block_20" [expr 1257.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[0\\\]" 1515.000 $north_y R270
add_macro_placement "gpio_defaults_block_19" [expr 1515.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[10\\\]" 1767.000 $north_y R270
add_macro_placement "gpio_defaults_block_18" [expr 1767.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[9\\\]" 2104.000 $north_y R270
add_macro_placement "gpio_defaults_block_17" [expr 2104.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[8\\\]" 2489.000 $north_y R270
add_macro_placement "gpio_defaults_block_16" [expr 2489.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[7\\\]" 2746.000 $north_y R270
add_macro_placement "gpio_defaults_block_15" [expr 2746.00 + 64.968717] [expr $north_y + 136.3215974] R270
# east
set east_x 3381.015
add_macro_placement "gpio_defaults_block_0" [expr $east_x+136.320042674] 670.000 FN
add_macro_placement "gpio_control_bidir_1\\\[0\\\]" $east_x 605.000 MY
add_macro_placement "gpio_defaults_block_1" [expr $east_x+136.320042674] 896.000 FN
add_macro_placement "gpio_control_bidir_1\\\[1\\\]" $east_x 831.000 MY
add_macro_placement "gpio_defaults_block_2" [expr $east_x+136.320042674] 1121.000 FN
add_macro_placement "gpio_control_in_1a\\\[0\\\]" $east_x 1056.000 MY
add_macro_placement "gpio_defaults_block_3" [expr $east_x+136.320042674] 1347.000 FN
add_macro_placement "gpio_control_in_1a\\\[1\\\]" $east_x 1282.000 MY
add_macro_placement "gpio_defaults_block_4" [expr $east_x+136.320042674] 1572.000 FN
add_macro_placement "gpio_control_in_1a\\\[2\\\]" $east_x 1507.000 MY
add_macro_placement "gpio_defaults_block_5" [expr $east_x+136.320042674] 1797.000 FN
add_macro_placement "gpio_control_in_1a\\\[3\\\]" $east_x 1732.000 MY
add_macro_placement "gpio_defaults_block_6" [expr $east_x+136.320042674] 2023.000 FN
add_macro_placement "gpio_control_in_1a\\\[4\\\]" $east_x 1958.000 MY
add_macro_placement "gpio_defaults_block_7" [expr $east_x+136.320042674] 2464.000 FN
add_macro_placement "gpio_control_in_1a\\\[5\\\]" $east_x 2399.000 MY
add_macro_placement "gpio_defaults_block_8" [expr $east_x+136.320042674] 2684.000 FN
add_macro_placement "gpio_control_in_1\\\[0\\\]" $east_x 2619.000 MY
add_macro_placement "gpio_defaults_block_9" [expr $east_x+136.320042674] 2909.000 FN
add_macro_placement "gpio_control_in_1\\\[1\\\]" $east_x 2844.000 MY
add_macro_placement "gpio_defaults_block_10" [expr $east_x+136.320042674] 3135.000 FN
add_macro_placement "gpio_control_in_1\\\[2\\\]" $east_x 3070.000 MY
add_macro_placement "gpio_defaults_block_11" [expr $east_x+136.320042674] [expr 3295.000+65] FN
add_macro_placement "gpio_control_in_1\\\[3\\\]" $east_x 3295.000 MY
add_macro_placement "gpio_defaults_block_12" [expr $east_x+136.320042674] [expr 3521.000+65] FN
add_macro_placement "gpio_control_in_1\\\[4\\\]" $east_x 3521.000 MY
add_macro_placement "gpio_defaults_block_13" [expr $east_x+136.320042674] [expr 3746.000+65] FN
add_macro_placement "gpio_control_in_1\\\[5\\\]" $east_x 3746.000 MY
add_macro_placement "gpio_defaults_block_14" [expr $east_x+136.320042674] [expr 4638.000+65] FN
add_macro_placement "gpio_control_in_1\\\[6\\\]" $east_x 4638.000 MY
manual_macro_placement f
# modify to a different file
remove_pins -input $::env(CURRENT_DEF)
remove_empty_nets -input $::env(CURRENT_DEF)
# add routing obstruction around the user_project_wrapper to prevent
# having shorts with the core ring or signal routing inside the wrapper
set gap 0.4
set user_project_wrapper_obs [list [expr $mprj_x-$gap] [expr $mprj_y-$gap] [expr $mprj_x+$gap+2920] [expr $mprj_y+$gap+3520]]
set user_project_wrapper_core_ring_obs [list [expr $mprj_x-43.63] [expr $mprj_y-38.34] [expr $mprj_x+2963.25] [expr $mprj_y+$gap+3557.96]]
# add routing obstructions on the management area
set mgmt_area_obs [list $soc_x $soc_y [expr $soc_x+2620] [expr $soc_y+820]]
set routing_vio_obs [list 106.26803 2098.54857 108.85254 2096.63000]
set ::env(GLB_RT_OBS) "
met1 $user_project_wrapper_obs,\
met2 $user_project_wrapper_obs,\
met3 $user_project_wrapper_obs,\
met4 $user_project_wrapper_core_ring_obs,\
met4 $mgmt_area_obs,\
met5 $user_project_wrapper_core_ring_obs,\
met5 $mgmt_area_obs"
try_catch openroad -python $::env(SCRIPTS_DIR)/add_def_obstructions.py \
--input-def $::env(CURRENT_DEF) \
--lef $::env(MERGED_LEF) \
--obstructions $::env(GLB_RT_OBS) \
--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
set_def [file rootname $::env(CURRENT_DEF)].obs.def
# add_macro_obs \
# -defFile $::env(CURRENT_DEF) \
# -lefFile $::env(MERGED_LEF_UNPADDED) \
# -obstruction vddio_obs \
# -placementX 103.400 \
# -placementY 607.150 \
# -sizeWidth 94.500 \
# -sizeHeight 30 \
# -fixed 1 \
# -layerNames "met2 met4"
# add_macro_obs \
# -defFile $::env(CURRENT_DEF) \
# -lefFile $::env(MERGED_LEF_UNPADDED) \
# -obstruction vddio_pad_obs \
# -placementX 33.375 \
# -placementY 557.100 \
# -sizeWidth 62.615 \
# -sizeHeight 62.700 \
# -fixed 1 \
# -layerNames "li1 met1 met2 met3 met4 met5"
li1_hack_start
global_routing
detailed_routing
li1_hack_end
remove_component -input $::env(CURRENT_DEF) -instance_name obs_li1
run_magic
save_views -def_path $::env(CURRENT_DEF) \
-gds_path $::env(magic_result_file_tag).gds \
-mag_path $::env(magic_result_file_tag).mag \
-verilog_path $::env(RUN_DIR)/caravel.v \
-save_path $save_path \
-tag caravel
exit
label_macro_pins\
-lef $::env(TMP_DIR)/lvs.lef\
-netlist_def $::env(TMP_DIR)/lvs.def
# -extra_args {-v\
# --map padframe vddio vddio INOUT\
# --map padframe vssio vssio INOUT\
# --map padframe vssa vssa INOUT\
# --map padframe vccd vccd INOUT\
# --map padframe vssd vssd INOUT}
run_magic
run_magic_spice_export
save_views -lef_path $::env(magic_result_file_tag).lef \
-def_path $::env(tritonRoute_result_file_tag).def \
-gds_path $::env(magic_result_file_tag).gds \
-mag_path $::env(magic_result_file_tag).mag \
-verilog_path $::env(TMP_DIR)/lvs.v \
-spice_path $::env(magic_result_file_tag).spice \
-save_path $save_path \
-tag $::env(RUN_TAG)
run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v

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openlane/caravel/sky130_fd_sc_hd.tlef Normal file
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@ -0,0 +1,788 @@
# Copyright 2020 The SkyWater PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
VERSION 5.7 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
UNITS
TIME NANOSECONDS 1 ;
CAPACITANCE PICOFARADS 1 ;
RESISTANCE OHMS 1 ;
DATABASE MICRONS 1000 ;
END UNITS
MANUFACTURINGGRID 0.005 ;
USEMINSPACING OBS OFF ;
PROPERTYDEFINITIONS
LAYER LEF58_TYPE STRING ;
END PROPERTYDEFINITIONS
# High density, single height
SITE unithd
SYMMETRY Y ;
CLASS CORE ;
SIZE 0.46 BY 2.72 ;
END unithd
# High density, double height
SITE unithddbl
SYMMETRY Y ;
CLASS CORE ;
SIZE 0.46 BY 5.44 ;
END unithddbl
LAYER nwell
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
END nwell
LAYER pwell
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE PWELL ;" ;
END pwell
LAYER li1
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.46 0.34 ;
OFFSET 0.23 0.17 ;
WIDTH 0.17 ; # LI 1
# SPACING 0.17 ; # LI 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.17 ;
AREA 0.0561 ; # LI 6
THICKNESS 0.1 ;
EDGECAPACITANCE 40.697E-6 ;
CAPACITANCE CPERSQDIST 36.9866E-6 ;
RESISTANCE RPERSQ 12.2 ;
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ;
END li1
LAYER mcon
TYPE CUT ;
WIDTH 0.17 ; # Mcon 1
SPACING 0.19 ; # Mcon 2
ENCLOSURE BELOW 0 0 ; # Mcon 4
ENCLOSURE ABOVE 0.03 0.06 ; # Met1 4 / Met1 5
ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ;
DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC
END mcon
LAYER met1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.34 ;
OFFSET 0.17 ;
WIDTH 0.14 ; # Met1 1
# SPACING 0.14 ; # Met1 2
# SPACING 0.28 RANGE 3.001 100 ; # Met1 3b
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.28 ;
AREA 0.083 ; # Met1 6
THICKNESS 0.35 ;
MINENCLOSEDAREA 0.14 ;
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
EDGECAPACITANCE 40.567E-6 ;
CAPACITANCE CPERSQDIST 25.7784E-6 ;
DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
RESISTANCE RPERSQ 0.125 ;
END met1
LAYER via
TYPE CUT ;
WIDTH 0.15 ; # Via 1a
SPACING 0.17 ; # Via 2
ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a
ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
END via
LAYER met2
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.46 ;
OFFSET 0.23 ;
WIDTH 0.14 ; # Met2 1
# SPACING 0.14 ; # Met2 2
# SPACING 0.28 RANGE 3.001 100 ; # Met2 3b
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.28 ;
AREA 0.0676 ; # Met2 6
THICKNESS 0.35 ;
MINENCLOSEDAREA 0.14 ;
EDGECAPACITANCE 37.759E-6 ;
CAPACITANCE CPERSQDIST 16.9423E-6 ;
RESISTANCE RPERSQ 0.125 ;
DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
END met2
# ******** Layer via2, type routing, number 44 **************
LAYER via2
TYPE CUT ;
WIDTH 0.2 ; # Via2 1
SPACING 0.2 ; # Via2 2
ENCLOSURE BELOW 0.04 0.085 ; # Via2 4
ENCLOSURE ABOVE 0.065 0.065 ; # Met3 4
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
END via2
LAYER met3
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.68 ;
OFFSET 0.34 ;
WIDTH 0.3 ; # Met3 1
# SPACING 0.3 ; # Met3 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.4 ;
AREA 0.24 ; # Met3 6
THICKNESS 0.8 ;
EDGECAPACITANCE 40.989E-6 ;
CAPACITANCE CPERSQDIST 12.3729E-6 ;
RESISTANCE RPERSQ 0.047 ;
DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
END met3
LAYER via3
TYPE CUT ;
WIDTH 0.2 ; # Via3 1
SPACING 0.2 ; # Via3 2
ENCLOSURE BELOW 0.06 0.09 ; # Via3 4 / Via3 5
ENCLOSURE ABOVE 0.065 0.065 ; # Met4 3
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
END via3
LAYER met4
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.92 ;
OFFSET 0.46 ;
WIDTH 0.3 ; # Met4 1
# SPACING 0.3 ; # Met4 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.4 ;
AREA 0.24 ; # Met4 4a
THICKNESS 0.8 ;
EDGECAPACITANCE 36.676E-6 ;
CAPACITANCE CPERSQDIST 8.41537E-6 ;
RESISTANCE RPERSQ 0.047 ;
DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
END met4
LAYER via4
TYPE CUT ;
WIDTH 0.8 ; # Via4 1
SPACING 0.8 ; # Via4 2
ENCLOSURE BELOW 0.19 0.19 ; # Via4 4
ENCLOSURE ABOVE 0.31 0.31 ; # Met5 3
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
END via4
LAYER met5
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 3.4 ;
OFFSET 1.7 ;
WIDTH 1.6 ; # Met5 1
#SPACING 1.6 ; # Met5 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 1.6 ;
AREA 4 ; # Met5 4
THICKNESS 1.2 ;
EDGECAPACITANCE 38.851E-6 ;
CAPACITANCE CPERSQDIST 6.32063E-6 ;
RESISTANCE RPERSQ 0.0285 ;
DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
END met5
### Routing via cells section ###
# Plus via rule, metals are along the prefered direction
VIA L1M1_PR DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.115 0.145 0.115 ;
END L1M1_PR
VIARULE L1M1_PR GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.06 0.03 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR
# Plus via rule, metals are along the non prefered direction
VIA L1M1_PR_R DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.115 -0.145 0.115 0.145 ;
END L1M1_PR_R
VIARULE L1M1_PR_R GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.03 0.06 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA L1M1_PR_M DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.115 -0.145 0.115 0.145 ;
END L1M1_PR_M
VIARULE L1M1_PR_M GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.03 0.06 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA L1M1_PR_MR DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.115 0.145 0.115 ;
END L1M1_PR_MR
VIARULE L1M1_PR_MR GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.06 0.03 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_MR
# Centered via rule, we really do not want to use it
VIA L1M1_PR_C DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.145 0.145 0.145 ;
END L1M1_PR_C
VIARULE L1M1_PR_C GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.06 0.06 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_C
# Plus via rule, metals are along the prefered direction
VIA M1M2_PR DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR
VIARULE M1M2_PR GENERATE
LAYER met1 ;
ENCLOSURE 0.085 0.055 ;
LAYER met2 ;
ENCLOSURE 0.055 0.085 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR
# Plus via rule, metals are along the non prefered direction
VIA M1M2_PR_R DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_R
VIARULE M1M2_PR_R GENERATE
LAYER met1 ;
ENCLOSURE 0.055 0.085 ;
LAYER met2 ;
ENCLOSURE 0.085 0.055 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M1M2_PR_M DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_M
VIARULE M1M2_PR_M GENERATE
LAYER met1 ;
ENCLOSURE 0.085 0.055 ;
LAYER met2 ;
ENCLOSURE 0.085 0.055 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M1M2_PR_MR DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR_MR
VIARULE M1M2_PR_MR GENERATE
LAYER met1 ;
ENCLOSURE 0.055 0.085 ;
LAYER met2 ;
ENCLOSURE 0.055 0.085 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_MR
# Centered via rule, we really do not want to use it
VIA M1M2_PR_C DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.16 -0.16 0.16 0.16 ;
LAYER met2 ;
RECT -0.16 -0.16 0.16 0.16 ;
END M1M2_PR_C
VIARULE M1M2_PR_C GENERATE
LAYER met1 ;
ENCLOSURE 0.085 0.085 ;
LAYER met2 ;
ENCLOSURE 0.085 0.085 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_C
# Plus via rule, metals are along the prefered direction
VIA M2M3_PR DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.14 -0.185 0.14 0.185 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR
VIARULE M2M3_PR GENERATE
LAYER met2 ;
ENCLOSURE 0.04 0.085 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR
# Plus via rule, metals are along the non prefered direction
VIA M2M3_PR_R DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.185 -0.14 0.185 0.14 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_R
VIARULE M2M3_PR_R GENERATE
LAYER met2 ;
ENCLOSURE 0.085 0.04 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M2M3_PR_M DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.14 -0.185 0.14 0.185 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_M
VIARULE M2M3_PR_M GENERATE
LAYER met2 ;
ENCLOSURE 0.04 0.085 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M2M3_PR_MR DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.185 -0.14 0.185 0.14 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_MR
VIARULE M2M3_PR_MR GENERATE
LAYER met2 ;
ENCLOSURE 0.085 0.04 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_MR
# Centered via rule, we really do not want to use it
VIA M2M3_PR_C DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.185 -0.185 0.185 0.185 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_C
VIARULE M2M3_PR_C GENERATE
LAYER met2 ;
ENCLOSURE 0.085 0.085 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_C
# Plus via rule, metals are along the prefered direction
VIA M3M4_PR DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.19 -0.16 0.19 0.16 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR
VIARULE M3M4_PR GENERATE
LAYER met3 ;
ENCLOSURE 0.09 0.06 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR
# Plus via rule, metals are along the non prefered direction
VIA M3M4_PR_R DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.16 -0.19 0.16 0.19 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_R
VIARULE M3M4_PR_R GENERATE
LAYER met3 ;
ENCLOSURE 0.06 0.09 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M3M4_PR_M DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.19 -0.16 0.19 0.16 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_M
VIARULE M3M4_PR_M GENERATE
LAYER met3 ;
ENCLOSURE 0.09 0.06 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M3M4_PR_MR DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.16 -0.19 0.16 0.19 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_MR
VIARULE M3M4_PR_MR GENERATE
LAYER met3 ;
ENCLOSURE 0.06 0.09 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_MR
# Centered via rule, we really do not want to use it
VIA M3M4_PR_C DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.19 -0.19 0.19 0.19 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_C
VIARULE M3M4_PR_C GENERATE
LAYER met3 ;
ENCLOSURE 0.09 0.09 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_C
# Plus via rule, metals are along the prefered direction
VIA M4M5_PR DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR
VIARULE M4M5_PR GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR
# Plus via rule, metals are along the non prefered direction
VIA M4M5_PR_R DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_R
VIARULE M4M5_PR_R GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M4M5_PR_M DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_M
VIARULE M4M5_PR_M GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M4M5_PR_MR DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_MR
VIARULE M4M5_PR_MR GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_MR
# Centered via rule, we really do not want to use it
VIA M4M5_PR_C DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_C
VIARULE M4M5_PR_C GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_C
### end of single via cells ###
END LIBRARY

90
scripts/signoff_automation.py
View File

@ -5,6 +5,7 @@ from cmath import log
import logging
import os
import subprocess
from sys import stdout
import count_lvs
import glob
import run_pt_sta
@ -36,6 +37,7 @@ def build_caravel(caravel_root, mcw_root, pdk_root, log_dir, pdk_env):
)
subprocess.run(build_cmd, stderr=build_log, stdout=build_log)
def run_drc(caravel_root, log_dir, signoff_dir, pdk_root):
klayout_drc_cmd = [
"python3",
@ -54,13 +56,14 @@ def run_drc(caravel_root, log_dir, signoff_dir, pdk_root):
def run_lvs(caravel_root, mcw_root, log_dir, signoff_dir, pdk_root, lvs_root, pdk_env):
os.environ["PDK_ROOT"] = pdk_root
os.environ["PDK"] = pdk_env
os.environ["LVS_ROOT"] = lvs_root
os.environ["LOG_ROOT"] = log_dir
os.environ["CARAVEL_ROOT"] = caravel_root
os.environ["MCW_ROOT"] = mcw_root
os.environ["SIGNOFF_ROOT"] = os.path.join(signoff_dir, "caravel")
myenv = os.environ.copy()
myenv["PDK_ROOT"] = pdk_root
myenv["PDK"] = pdk_env
myenv["LVS_ROOT"] = lvs_root
myenv["LOG_ROOT"] = log_dir
myenv["CARAVEL_ROOT"] = caravel_root
myenv["MCW_ROOT"] = mcw_root
myenv["SIGNOFF_ROOT"] = os.path.join(signoff_dir, "caravel")
if not os.path.exists(f"{lvs_root}"):
subprocess.run(
@ -83,13 +86,20 @@ def run_lvs(caravel_root, mcw_root, log_dir, signoff_dir, pdk_root, lvs_root, pd
"caravel",
f"{caravel_root}/gds/caravel.gds",
]
p1 = subprocess.Popen(lvs_cmd)
p1 = subprocess.Popen(
lvs_cmd,
env=myenv,
universal_newlines=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
)
return p1
def run_verification(caravel_root, pdk_root, pdk_env, sim, simulator="vcs"):
os.environ["PDK_ROOT"] = pdk_root
os.environ["PDK"] = pdk_env
myenv = os.environ.copy()
myenv["PDK_ROOT"] = pdk_root
myenv["PDK"] = pdk_env
if simulator == "vcs":
lvs_cmd = [
"python3",
@ -112,6 +122,8 @@ def run_verification(caravel_root, pdk_root, pdk_env, sim, simulator="vcs"):
p1 = subprocess.Popen(
lvs_cmd,
cwd=f"{caravel_root}/verilog/dv/cocotb",
env=myenv,
universal_newlines=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
)
@ -119,9 +131,10 @@ def run_verification(caravel_root, pdk_root, pdk_env, sim, simulator="vcs"):
def run_sta(caravel_root, mcw_root, pt_lib_root, log_dir, signoff_dir):
os.environ["CARAVEL_ROOT"] = caravel_root
os.environ["MCW_ROOT"] = mcw_root
os.environ["PT_LIB_ROOT"] = pt_lib_root
myenv = os.environ.copy()
myenv["CARAVEL_ROOT"] = caravel_root
myenv["MCW_ROOT"] = mcw_root
myenv["PT_LIB_ROOT"] = pt_lib_root
if not os.path.exists(f"{pt_lib_root}"):
subprocess.run(
[
@ -141,23 +154,24 @@ def run_sta(caravel_root, mcw_root, pt_lib_root, log_dir, signoff_dir):
"-o",
f"{signoff_dir}/caravel",
"-l",
f"{log_dir}"
f"{log_dir}",
]
p1 = subprocess.Popen(
sta_cmd,
cwd=f"{caravel_root}/scripts",
env=myenv,
universal_newlines=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
)
return p1
def check_errors(caravel_root, log_dir, signoff_dir, drc, lvs, verification):
drc_count_klayout = os.path.join(log_dir, "caravel_klayout_drc.total")
lvs_report = os.path.join(signoff_dir, "caravel/caravel.lvs.rpt")
lvs_summary_report = open(os.path.join(signoff_dir, "caravel/lvs_summary.rpt"))
f = open(os.path.join(signoff_dir, "caravel/signoff.rpt"))
count = 0
if drc:
drc_count_klayout = os.path.join(log_dir, "caravel_klayout_drc.total")
with open(drc_count_klayout) as rep:
if rep.readline() != 0:
logging.error(f"klayout DRC failed")
@ -167,6 +181,8 @@ def check_errors(caravel_root, log_dir, signoff_dir, drc, lvs, verification):
logging.info("Klayout MR DRC: Passed")
f.write("Klayout MR DRC: Passed")
if lvs:
lvs_summary_report = open(os.path.join(signoff_dir, "caravel/lvs_summary.rpt"))
lvs_report = os.path.join(signoff_dir, "caravel/caravel.lvs.rpt")
failures = count_lvs.count_LVS_failures(args.file)
if failures[0] > 0:
lvs_summary_report.write("LVS reports:")
@ -307,6 +323,7 @@ if __name__ == "__main__":
drc = True
lvs = True
verification = True
sta = True
if drc:
drc_p1 = run_drc(caravel_root, log_dir, signoff_dir, pdk_root)
@ -323,6 +340,17 @@ if __name__ == "__main__":
pdk_env,
)
logging.info("Running LVS on caravel")
if sta:
logging.info(f"Running PrimeTime STA all corners on caravel")
sta_p = run_sta(
caravel_root,
mcw_root,
f"{caravel_root}/scripts/mpw-2-sta-debug/files/custom/lib",
log_dir,
signoff_dir,
)
if verification or iverilog:
verify_p = []
sim = []
@ -338,29 +366,39 @@ if __name__ == "__main__":
simulator = "vcs"
elif iverilog:
simulator = "iverilog"
for sim in sim:
logging.info(f"Running all {sim} verification on caravel")
for sim_type in sim:
logging.info(f"Running all {sim_type} verification on caravel")
verify_p.append(
run_verification(caravel_root, pdk_root, pdk_env, sim, simulator)
run_verification(caravel_root, pdk_root, pdk_env, sim_type, simulator)
)
for i in range(len(verify_p)):
out, err = verify_p[i].communicate()
ver_log = open(f"{log_dir}/{sim[i]}_caravel.log", "w")
if err:
logging.error(err.decode())
if sta:
logging.info(f"Running PrimeTime STA all corners on caravel")
sta_p = run_sta(caravel_root, mcw_root, "mpw-2-sta-debug", log_dir, signoff_dir)
ver_log.write(err)
if out:
ver_log.write(out)
if lvs and drc and sta:
sta_p.wait()
out, err = sta_p.communicate()
sta_log = open(f"{log_dir}/PT_STA_caravel.log", "w")
if err:
logging.error(err.decode())
sta_log.write(err)
drc_p1.wait()
lvs_p1.wait()
if lvs:
lvs_p1.wait()
if drc:
drc_p1.wait()
if sta:
out, err = sta_p.communicate()
sta_log = open(f"{log_dir}/PT_STA_caravel.log", "w")
if err:
logging.error(err.decode())
sta_log.write(err)
if not check_errors(caravel_root, log_dir, signoff_dir, drc, lvs, verification):
exit(1)

1
signoff/caravel/OPENLANE_VERSION Normal file
View File

@ -0,0 +1 @@
openlane v0.22

6
signoff/caravel/PDK_SOURCES Normal file
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@ -0,0 +1,6 @@
-ne openlane
02c16938aea3770c1d2e03fc8beed763fa83f30f
-ne skywater-pdk
ea95157faad3a3f5c560aaec3f1841ee5a2aa2db
-ne open_pdks
1d93a6bd9d6e481acfdf88f26aa3bb0600303d98

94964
spef/multicorner/caravel.max.spef Normal file
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83450
spef/multicorner/caravel.min.spef Normal file
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87818
spef/multicorner/caravel.nom.spef Normal file
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File diff suppressed because it is too large Load Diff

772
verilog/gl/caravel.v
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File diff suppressed because it is too large Load Diff

2
verilog/rtl/caravel_power_routing.v Normal file
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@ -0,0 +1,2 @@
module caravel_power_routing ();
endmodule