From 3fe7f3f38b926ac96c65d5b228a11bbaf0ec3679 Mon Sep 17 00:00:00 2001
From: M0stafaRady <mostafa.rady@efabless.com>
Date: Tue, 11 Oct 2022 06:04:16 -0700
Subject: [PATCH] fix tests timeout

---
 verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py | 2 +-
 verilog/dv/cocotb/tests/gpio/gpio.py                 | 2 +-
 verilog/dv/cocotb/tests/gpio/gpio_all_o.c            | 2 +-
 verilog/dv/cocotb/tests/gpio/gpio_user.py            | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
index 5c6ec045..fc675710 100644
--- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
+++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
@@ -134,7 +134,7 @@ async def bitbang_cpu_all_0011(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_1100(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py
index 92bb82c0..778a1bf3 100644
--- a/verilog/dv/cocotb/tests/gpio/gpio.py
+++ b/verilog/dv/cocotb/tests/gpio/gpio.py
@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def gpio_all_o(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=586652)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o.c b/verilog/dv/cocotb/tests/gpio/gpio_all_o.c
index be8748bf..f1db9d93 100644
--- a/verilog/dv/cocotb/tests/gpio/gpio_all_o.c
+++ b/verilog/dv/cocotb/tests/gpio/gpio_all_o.c
@@ -77,7 +77,7 @@ void main(){
         
         // try to give input 
         reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
-        int timeout = 1000;
+        int timeout = 100;
         while (reg_mprj_datal != 0x8F66FD7B){
                 timeout--;
                 if (timeout==0){
diff --git a/verilog/dv/cocotb/tests/gpio/gpio_user.py b/verilog/dv/cocotb/tests/gpio/gpio_user.py
index bf4d5f7f..d8394e62 100644
--- a/verilog/dv/cocotb/tests/gpio/gpio_user.py
+++ b/verilog/dv/cocotb/tests/gpio/gpio_user.py
@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def gpio_all_o_user(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=585321)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=542674)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()