From 3b89cf0efa17b39f64e05114375085f3d150952c Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Wed, 3 Nov 2021 11:30:39 -0400 Subject: [PATCH] Corrected the clock signal into the housekeeping module, which was incorrectly assigned to the clock on the user side of the managment protect block, causing it to be undefined when the user area power supply is down. The "hkspi_power" testbench which tests using the housekeeping SPI while the user area power is grounded now works correctly. --- verilog/rtl/caravan.v | 4 ++-- verilog/rtl/caravel.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index ead1d1bf..5a183d46 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -696,8 +696,8 @@ module caravan ( .vss(VGND), `endif - .wb_clk_i(mprj_clock), - .wb_rst_i(mprj_reset), + .wb_clk_i(caravel_clk), + .wb_rst_i(caravel_rstn), .wb_adr_i(mprj_adr_o_core), .wb_dat_i(mprj_dat_o_core), diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index cffb17e1..9f5c37bf 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -637,8 +637,8 @@ module caravel ( .vss(VGND), `endif - .wb_clk_i(mprj_clock), - .wb_rst_i(mprj_reset), + .wb_clk_i(caravel_clk), + .wb_rst_i(caravel_rstn), .wb_adr_i(mprj_adr_o_core), .wb_dat_i(mprj_dat_o_core),