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Apply automatic changes to Manifest and README.rst

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RTimothyEdwards 2022-09-20 20:04:12 +00:00 committed by My GitHub Actions Bot
parent 37720ea216
commit 3962b061f6
1 changed files with 6 additions and 6 deletions
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@ -2,14 +2,14 @@
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
6576abded424d948d2a7e71c2b4a4df1eda77238 verilog/rtl/caravan.v
670031aa4d92dbf15054b698f859b01d35143aa9 verilog/rtl/caravan.v
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v
22c9fc7c6e9dccd4c8511d9d6ec63765dfaedf3a verilog/rtl/caravel.v
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v
54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v
a0b12a4769db4cfa0cd340194af3429d3daedb51 verilog/rtl/chip_io.v
2b0bbaa63039534db811c82d808e885a1b9c20e3 verilog/rtl/chip_io_alt.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
@ -21,9 +21,9 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
6f490c83d6064c380a3f475823ef97f325d7f6c1 verilog/rtl/pads.v
770d418646d4f4f37a08b5de8308d33eafd7bde9 verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v