connected rest of buffers to power

2022-10-17 01:15:46 +02:00 · 2022-10-17 01:15:46 +02:00 · 37d2a9d463
parent 84d1627151
commit 37d2a9d463
2 changed files with 12 additions and 8 deletions
--- a/gds/caravel_power_routing.gds.gz
+++ b/gds/caravel_power_routing.gds.gz
--- a/verilog/rtl/buff_flash_clkrst.v
+++ b/verilog/rtl/buff_flash_clkrst.v
@ -1,17 +1,21 @@
 module buff_flash_clkrst (
+	`ifdef USE_POWER_PINS
+		inout VPWR,
+		inout VGND,
+	`endif
 	input[11:0] in_n, 
 	input[2:0] in_s, 
 	output[11:0] out_s, 
-	output[2:0] out_n,
-	input VPWR,
- 	input VGND);
+	output[2:0] out_n);

 	sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (
-		.A({in_n, in_s}), 
-		.X({out_s, out_n}),
+		`ifdef USE_POWER_PINS
 			.VGND(VGND),
 			.VNB(VGND),
 			.VPB(VPWR),
-		.VPWR(VPWR)); 
+			.VPWR(VPWR),
+		`endif
+		.A({in_n, in_s}), 
+		.X({out_s, out_n})); 

 endmodule