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connected rest of buffers to power

This commit is contained in:
Marwan Abbas 2022-10-17 01:15:46 +02:00
parent 84d1627151
commit 37d2a9d463
2 changed files with 12 additions and 8 deletions
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gds/caravel_power_routing.gds.gz
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16
verilog/rtl/buff_flash_clkrst.v
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@ -1,17 +1,21 @@
module buff_flash_clkrst ( module buff_flash_clkrst (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
input[11:0] in_n, input[11:0] in_n,
input[2:0] in_s, input[2:0] in_s,
output[11:0] out_s, output[11:0] out_s,
output[2:0] out_n, output[2:0] out_n);
input VPWR,
input VGND);
sky130_fd_sc_hd__clkbuf_8 BUF[14:0] ( sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (
.A({in_n, in_s}), `ifdef USE_POWER_PINS
.X({out_s, out_n}),
.VGND(VGND), .VGND(VGND),
.VNB(VGND), .VNB(VGND),
.VPB(VPWR), .VPB(VPWR),
.VPWR(VPWR)); .VPWR(VPWR),
`endif
.A({in_n, in_s}),
.X({out_s, out_n}));
endmodule endmodule