mirror of https://github.com/efabless/caravel.git
[DATA] Update HK module (li1 routing: 249um)
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218560
def/housekeeping.def
218560
def/housekeeping.def
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@ -3213,19 +3213,9 @@ MACRO housekeeping
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END wb_we_i
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END wb_we_i
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OBS
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OBS
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@ -3452,342 +3442,341 @@ MACRO housekeeping
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RECT 12.540 194.700 291.060 254.660 ;
|
|
||||||
END
|
END
|
||||||
END housekeeping
|
END housekeeping
|
||||||
END LIBRARY
|
END LIBRARY
|
||||||
|
|
742196
mag/housekeeping.mag
742196
mag/housekeeping.mag
File diff suppressed because it is too large
Load Diff
|
@ -1,21 +1,11 @@
|
||||||
magic
|
magic
|
||||||
tech sky130A
|
tech sky130A
|
||||||
magscale 1 2
|
magscale 1 2
|
||||||
timestamp 1637253363
|
timestamp 1637412622
|
||||||
<< obsli1 >>
|
<< obsli1 >>
|
||||||
rect 949 100759 60046 107831
|
rect 1104 2159 58880 107729
|
||||||
rect 949 80257 60047 100759
|
|
||||||
rect 949 78183 60046 80257
|
|
||||||
rect 949 55913 60047 78183
|
|
||||||
rect 949 51731 60046 55913
|
|
||||||
rect 949 42245 60047 51731
|
|
||||||
rect 949 42007 60046 42245
|
|
||||||
rect 949 36873 60047 42007
|
|
||||||
rect 949 36567 60046 36873
|
|
||||||
rect 949 23069 60047 36567
|
|
||||||
rect 949 901 60046 23069
|
|
||||||
<< obsm1 >>
|
<< obsm1 >>
|
||||||
rect 14 892 60044 108044
|
rect 14 2128 60044 107976
|
||||||
<< metal2 >>
|
<< metal2 >>
|
||||||
rect 202 109390 258 110190
|
rect 202 109390 258 110190
|
||||||
rect 662 109390 718 110190
|
rect 662 109390 718 110190
|
||||||
|
@ -638,344 +628,344 @@ rect 0 1368 800 1488
|
||||||
rect 59246 824 60046 944
|
rect 59246 824 60046 944
|
||||||
rect 0 416 800 536
|
rect 0 416 800 536
|
||||||
<< obsm3 >>
|
<< obsm3 >>
|
||||||
rect 880 109416 59971 109578
|
rect 880 109416 60016 109578
|
||||||
rect 880 109408 59166 109416
|
rect 880 109408 59166 109416
|
||||||
rect 105 109136 59166 109408
|
rect 381 109136 59166 109408
|
||||||
rect 105 108736 59971 109136
|
rect 381 108736 60016 109136
|
||||||
rect 880 108456 59971 108736
|
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rect 105 26320 59971 26856
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rect 381 26320 60016 26856
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rect 105 26048 59166 26320
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rect 381 26048 59166 26320
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rect 880 26040 59166 26048
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rect 880 26040 59166 26048
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rect 880 25768 59971 26040
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rect 880 25768 60016 26040
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rect 105 25096 59971 25768
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rect 381 25096 60016 25768
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rect 880 24816 59971 25096
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rect 880 24816 60016 25096
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rect 105 24688 59971 24816
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rect 381 24688 60016 24816
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rect 105 24408 59166 24688
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rect 381 24408 59166 24688
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rect 105 24008 59971 24408
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rect 381 24008 60016 24408
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rect 880 23728 59971 24008
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rect 880 23728 60016 24008
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rect 105 23056 59971 23728
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rect 381 23056 60016 23728
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rect 880 22776 59166 23056
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rect 880 22776 59166 23056
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rect 105 21968 59971 22776
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rect 381 21968 60016 22776
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rect 880 21688 59971 21968
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rect 880 21688 60016 21968
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rect 105 21288 59971 21688
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rect 381 21288 60016 21688
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rect 105 21016 59166 21288
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rect 381 21016 59166 21288
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rect 880 21008 59166 21016
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rect 880 21008 59166 21016
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rect 880 20736 59971 21008
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rect 880 20736 60016 21008
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rect 105 19928 59971 20736
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rect 381 19928 60016 20736
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rect 880 19656 59971 19928
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rect 880 19656 60016 19928
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rect 880 19648 59166 19656
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rect 880 19648 59166 19656
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rect 105 19376 59166 19648
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rect 381 19376 59166 19648
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rect 105 18976 59971 19376
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rect 381 18976 60016 19376
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rect 880 18696 59971 18976
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rect 880 18696 60016 18976
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rect 105 17888 59971 18696
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rect 381 17888 60016 18696
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rect 880 17608 59166 17888
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rect 880 17608 59166 17888
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rect 105 16936 59971 17608
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rect 381 16936 60016 17608
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rect 880 16656 59971 16936
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rect 880 16656 60016 16936
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rect 105 16256 59971 16656
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rect 381 16256 60016 16656
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rect 105 15976 59166 16256
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rect 381 15976 59166 16256
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rect 105 15848 59971 15976
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rect 381 15848 60016 15976
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rect 880 15568 59971 15848
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rect 880 15568 60016 15848
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rect 105 14896 59971 15568
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rect 381 14896 60016 15568
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rect 880 14616 59971 14896
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rect 880 14616 60016 14896
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rect 105 14488 59971 14616
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rect 381 14488 60016 14616
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rect 105 14208 59166 14488
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rect 381 14208 59166 14488
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rect 105 13808 59971 14208
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rect 381 13808 60016 14208
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rect 880 13528 59971 13808
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rect 880 13528 60016 13808
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rect 105 12856 59971 13528
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rect 381 12856 60016 13528
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rect 880 12576 59166 12856
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rect 880 12576 59166 12856
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rect 105 11768 59971 12576
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rect 381 11768 60016 12576
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rect 880 11488 59971 11768
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rect 880 11488 60016 11768
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rect 105 11088 59971 11488
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rect 381 11088 60016 11488
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rect 105 10816 59166 11088
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rect 381 10816 59166 11088
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rect 880 10808 59166 10816
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rect 880 10808 59166 10816
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rect 880 10536 59971 10808
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rect 880 10536 60016 10808
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rect 105 9728 59971 10536
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rect 381 9728 60016 10536
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rect 880 9456 59971 9728
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rect 880 9456 60016 9728
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rect 880 9448 59166 9456
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rect 880 9448 59166 9456
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rect 105 9176 59166 9448
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rect 381 9176 59166 9448
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rect 105 8776 59971 9176
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rect 381 8776 60016 9176
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rect 880 8496 59971 8776
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rect 880 8496 60016 8776
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rect 105 7688 59971 8496
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rect 381 7688 60016 8496
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rect 880 7408 59166 7688
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rect 880 7408 59166 7688
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rect 105 6736 59971 7408
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rect 381 6736 60016 7408
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rect 880 6456 59971 6736
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rect 880 6456 60016 6736
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rect 105 6056 59971 6456
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rect 381 6056 60016 6456
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rect 105 5776 59166 6056
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rect 381 5776 59166 6056
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rect 105 5648 59971 5776
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rect 381 5648 60016 5776
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rect 880 5368 59971 5648
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rect 880 5368 60016 5648
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rect 105 4696 59971 5368
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rect 381 4696 60016 5368
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rect 880 4416 59971 4696
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rect 880 4416 60016 4696
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rect 105 4288 59971 4416
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rect 381 4288 60016 4416
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rect 105 4008 59166 4288
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rect 381 4008 59166 4288
|
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rect 105 3608 59971 4008
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rect 381 3608 60016 4008
|
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rect 880 3328 59971 3608
|
rect 880 3328 60016 3608
|
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rect 105 2656 59971 3328
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rect 381 2656 60016 3328
|
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rect 880 2376 59166 2656
|
rect 880 2376 59166 2656
|
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rect 105 1568 59971 2376
|
rect 381 1568 60016 2376
|
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rect 880 1288 59971 1568
|
rect 880 1288 60016 1568
|
||||||
rect 105 1024 59971 1288
|
rect 381 1024 60016 1288
|
||||||
rect 105 744 59166 1024
|
rect 381 744 59166 1024
|
||||||
rect 105 616 59971 744
|
rect 381 616 60016 744
|
||||||
rect 880 446 59971 616
|
rect 880 446 60016 616
|
||||||
<< metal4 >>
|
<< metal4 >>
|
||||||
rect 4208 2128 4528 107760
|
rect 4208 2128 4528 107760
|
||||||
rect 19568 2128 19888 107760
|
rect 19568 2128 19888 107760
|
||||||
rect 34928 2128 35248 107760
|
rect 34928 2128 35248 107760
|
||||||
rect 50288 2128 50608 107760
|
rect 50288 2128 50608 107760
|
||||||
<< obsm4 >>
|
<< obsm4 >>
|
||||||
rect 979 3979 4128 104141
|
rect 1163 3299 4128 106589
|
||||||
rect 4608 3979 19488 104141
|
rect 4608 3299 19488 106589
|
||||||
rect 19968 3979 34848 104141
|
rect 19968 3299 34848 106589
|
||||||
rect 35328 3979 50208 104141
|
rect 35328 3299 50208 106589
|
||||||
rect 50688 3979 59925 104141
|
rect 50688 3299 59925 106589
|
||||||
<< metal5 >>
|
<< metal5 >>
|
||||||
rect 1104 97206 58880 97526
|
rect 1104 97206 58880 97526
|
||||||
rect 1104 81888 58880 82208
|
rect 1104 81888 58880 82208
|
||||||
|
@ -985,8 +975,7 @@ rect 1104 35934 58880 36254
|
||||||
rect 1104 20616 58880 20936
|
rect 1104 20616 58880 20936
|
||||||
rect 1104 5298 58880 5618
|
rect 1104 5298 58880 5618
|
||||||
<< obsm5 >>
|
<< obsm5 >>
|
||||||
rect 2508 51892 58212 58980
|
rect 3244 38940 28036 39260
|
||||||
rect 2508 38940 58212 50932
|
|
||||||
<< labels >>
|
<< labels >>
|
||||||
rlabel metal5 s 1104 20616 58880 20936 6 VGND
|
rlabel metal5 s 1104 20616 58880 20936 6 VGND
|
||||||
port 1 nsew ground input
|
port 1 nsew ground input
|
||||||
|
@ -1803,7 +1792,7 @@ string LEFclass BLOCK
|
||||||
string FIXED_BBOX 0 0 60046 110190
|
string FIXED_BBOX 0 0 60046 110190
|
||||||
string LEFview TRUE
|
string LEFview TRUE
|
||||||
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/housekeeping/runs/housekeeping/results/magic/housekeeping.gds
|
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/housekeeping/runs/housekeeping/results/magic/housekeeping.gds
|
||||||
string GDS_END 22484834
|
string GDS_END 22580570
|
||||||
string GDS_START 1111786
|
string GDS_START 1111786
|
||||||
<< end >>
|
<< end >>
|
||||||
|
|
||||||
|
|
|
@ -50,6 +50,13 @@ set ::env(GLB_RT_OVERFLOW_ITERS) 100
|
||||||
|
|
||||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
|
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
|
||||||
|
|
||||||
|
# prevent signal routing on li1
|
||||||
|
set ::env(GLB_RT_OBS) "\
|
||||||
|
li1 0 0 5.94500 550.950,\
|
||||||
|
li1 0 0 300.23000 10.97000,\
|
||||||
|
li1 294.23500 0 300.22000 550.95000,\
|
||||||
|
li1 0 538.84500 300.2300 550.95000"
|
||||||
|
|
||||||
## Placement
|
## Placement
|
||||||
set ::env(PL_TARGET_DENSITY) 0.384
|
set ::env(PL_TARGET_DENSITY) 0.384
|
||||||
|
|
||||||
|
|
|
@ -1 +1 @@
|
||||||
openlane 2021.09.09_03.00.48-66-gbdb1b56
|
openlane 2021.09.09_03.00.48-71-ge0e6fbc
|
||||||
|
|
|
@ -1,2 +1,2 @@
|
||||||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||||
0,/home/ma/ef/caravel_openframe/openlane/housekeeping,housekeeping,housekeeping,flow_completed,0h28m56s,-1,64928.89438180887,0.16541171850000005,32464.447190904433,37.52,961.92,5370,0,0,0,0,0,0,0,57,0,66,-1,454178,61924,-1.5,-11.43,-1,0.0,-1,-753.9,-6155.54,-1,0.0,-1,313455162.0,27.26,39.37,64.05,15.67,30.22,1.82,8469,9603,194,1275,0,0,0,9230,0,0,0,0,0,0,0,4,1066,991,49,388,2156,0,2544,90.9090909090909,11.0,10.0,AREA 0,10,50,1,153.6,153.18,0.384,0.05,sky130_fd_sc_hd,0,3
|
0,/home/ma/ef/caravel_openframe/openlane/housekeeping,housekeeping,housekeeping,flow_completed,0h25m7s,-1,64928.89438180887,0.16541171850000005,32464.447190904433,37.52,976.58,5370,0,0,0,0,0,0,0,52,0,66,-1,454708,62134,-1.5,-11.43,-1,0.0,-1,-753.9,-6155.54,-1,0.0,-1,313455162.0,25.69,39.14,63.89,15.31,31.29,2.02,8469,9603,194,1275,0,0,0,9230,0,0,0,0,0,0,0,4,1066,991,49,388,2156,0,2544,90.9090909090909,11.0,10.0,AREA 0,10,50,1,153.6,153.18,0.384,0.05,sky130_fd_sc_hd,0,3
|
||||||
|
|
|
File diff suppressed because it is too large
Load Diff
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Reference in New Issue