Correction to the gen_gpio_defaults.py file, which was accidentally

overwriting the top-level gate-level verilog netlist with the
modified layout file contents.
This commit is contained in:
Tim Edwards 2021-12-04 12:41:06 -05:00
parent 9da6bab4a8
commit 3246e64407
1 changed files with 1 additions and 1 deletions

View File

@ -391,7 +391,7 @@ if __name__ == '__main__':
outlines.append(magline)
if not testmode:
with open(glpath + '/caravan.v', 'w') as ofile:
with open(magpath + '/caravan.mag', 'w') as ofile:
for outline in outlines:
print(outline, file=ofile)