From 2f6fe69b36ccf0422cfdc40ae1943d0ab5978296 Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Wed, 29 Dec 2021 15:42:41 -0500
Subject: [PATCH] Corrected the gen_gpio_defaults.py script so that it behaves
 correctly no matter how the "gpio_defaults_block.mag" and
 "gl/gpio_defaults_block.v" are defined.  Previously it assumed that they both
 defined all bits as zero, which was not the case for the layout.  Now both
 define bit value 0x0402 and the script can flip bits either direction as
 needed in both verilog and layout

---
 scripts/gen_gpio_defaults.py     | 17 +++++++++++++++++
 verilog/gl/gpio_defaults_block.v |  4 ++--
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/scripts/gen_gpio_defaults.py b/scripts/gen_gpio_defaults.py
index 15347e79..b88183e1 100755
--- a/scripts/gen_gpio_defaults.py
+++ b/scripts/gen_gpio_defaults.py
@@ -233,9 +233,12 @@ if __name__ == '__main__':
 
         # Record which bits need to be set for this binval
         bitflips = []
+        notflipped = []
         for j in range(0, 13):
             if binval[12 - j] == '1':
                 bitflips.append(j)
+            else:
+                notflipped.append(j)
 
         if not os.path.isfile(mag_file):
             # A cell with this set of defaults doesn't exist, so make it
@@ -247,12 +250,21 @@ if __name__ == '__main__':
                 outlines = []
                 for magline in maglines:
                     is_flipped = False
+                    reverse_flipped = False
                     for bitflip in bitflips:
                         if magline == zero_string[bitflip]:
                             is_flipped = True
                             break
+                    if not is_flipped:
+                        for bitflip in notflipped:
+                            if magline == one_string[bitflip]:
+                                reverse_flipped = True
+                                break
+
                     if is_flipped:
                         outlines.append(one_string[bitflip])
+                    elif reverse_flipped:
+                        outlines.append(zero_string[bitflip])
                     else:
                         outlines.append(magline)
 
@@ -280,13 +292,18 @@ if __name__ == '__main__':
                 outlines = []
                 for vline in vlines:
                     is_flipped = False
+                    is_reversed = False
                     dmatch = defrex.match(vline)
                     if dmatch:
                         bitidx = int(dmatch.group(1))
                         if bitidx in bitflips:
                             is_flipped = True
+                        else:
+                            is_reversed = True
                     if is_flipped:
                         outlines.append(re.sub('_low', '_high', vline))
+                    elif is_reversed:
+                        outlines.append(re.sub('_high', '_low', vline))
                     elif 'gpio_defaults_block' in vline:
                         outlines.append(re.sub('gpio_defaults_block', cell_name, vline))
                     else:
diff --git a/verilog/gl/gpio_defaults_block.v b/verilog/gl/gpio_defaults_block.v
index 34eb813e..4e6c7a4a 100644
--- a/verilog/gl/gpio_defaults_block.v
+++ b/verilog/gl/gpio_defaults_block.v
@@ -245,7 +245,7 @@ module gpio_defaults_block (VGND,
     .VPB(VPWR),
     .VPWR(VPWR));
  assign gpio_defaults[0] = \gpio_defaults_low[0] ;
- assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
  assign gpio_defaults[2] = \gpio_defaults_low[2] ;
  assign gpio_defaults[3] = \gpio_defaults_low[3] ;
  assign gpio_defaults[4] = \gpio_defaults_low[4] ;
@@ -254,7 +254,7 @@ module gpio_defaults_block (VGND,
  assign gpio_defaults[7] = \gpio_defaults_low[7] ;
  assign gpio_defaults[8] = \gpio_defaults_low[8] ;
  assign gpio_defaults[9] = \gpio_defaults_low[9] ;
- assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[10] = \gpio_defaults_high[10] ;
  assign gpio_defaults[11] = \gpio_defaults_low[11] ;
  assign gpio_defaults[12] = \gpio_defaults_low[12] ;
 endmodule