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Merge pull request #206 from efabless/cocotb 

Cocotb tests update
This commit is contained in:
Marwan Abbas 2022-10-13 22:16:06 +02:00 committed by GitHub
parent a3c1a3b3bc 143bccccbe
commit 2bf4aebcca
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GPG Key ID: 4AEE18F83AFDEB23
50 changed files with 1692 additions and 397 deletions
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4
manifest
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@ -1,9 +1,9 @@
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
1315c3df4decc1a015ec78dfb7df174eb3a74e9a verilog/rtl/__user_project_gpio_example.v
79cdb50a7dd60f69b63c0b6440b0dea35386387d verilog/rtl/__user_project_gpio_example.v
5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
ef356bbc8938fef0c1866a709a3bf846d8c7e1e4 verilog/rtl/__user_project_wrapper.v
cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v
65594673d24b42cce78491c8a695a147d8ead2ce verilog/rtl/buff_flash_clkrst.v
f93c57988b0044d2bff4470a84b5eddc158f2094 verilog/rtl/caravan.v
1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v

1
verilog/dv/README.md
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@ -15,6 +15,7 @@
#
# SPDX-License-Identifier: Apache-2.0
-->
# DV Tests
Organized into two subdirectories:

21
verilog/dv/cocotb/caravel_top.sv
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@ -1,12 +1,21 @@
`timescale 1 ns / 1 ps
`ifdef VCS
`ifndef ENABLE_SDF
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`endif
`timescale 1 ns / 1 ps
`else
`include "cvc-pdk/sky130_ef_io.v"
`include "cvc-pdk/sky130_fd_io.v"
`include "cvc-pdk/primitives_hd.v"
`include "cvc-pdk/sky130_fd_sc_hd.v"
`include "cvc-pdk/primitives_hvl.v"
`include "cvc-pdk/sky130_fd_sc_hvl.v"
`endif // ENABLE_SDF
`endif // VCS
module caravel_top ;
@ -15,7 +24,7 @@ parameter FILENAME={"hex_files/",`TESTNAME,".hex"};
initial begin
`ifdef VCS
`ifdef ENABLE_SDF
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `SDF_POSTFIX, ".vpd"});
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `CORNER,"-",`SDF_POSTFIX, ".vpd"});
`else
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,".vpd"});
`endif
@ -25,7 +34,11 @@ initial begin
$dumpvars (0, caravel_top);
`endif
end
`ifdef VCS
`ifdef ENABLE_SDF
`include "sdf_includes.v"
`endif
`endif // VCS
wire vddio_tb; // Common 3.3V padframe/ESD power
wire vddio_2_tb; // Common 3.3V padframe/ESD power
wire vssio_tb; // Common padframe/ESD ground

13
verilog/dv/cocotb/interfaces/caravel.py
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@ -1,7 +1,7 @@
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
import cocotb.log
import cocotb.simulator
from cocotb.handle import SimHandleBase
@ -51,13 +51,15 @@ class Caravel_env:
"""start carvel by insert power then reset"""
async def start_up(self):
await self.power_up()
# await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
await self.reset()
await self.disable_bins()
common.fill_macros(self.dut.macros) # get macros value
async def disable_bins(self):
for i in range(38):
if i in [3,4]: #CSB and SCK
continue
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
"""setup the vdd and vcc power bins"""
@ -108,7 +110,7 @@ class Caravel_env:
"""drive csb signal bin E8 mprj[3]"""
async def drive_csb(self,bit):
self.drive_gpio_in((3,3),bit)
self.drive_gpio_in((2,2),0)
self.drive_gpio_in((4,4),0)
await ClockCycles(self.clk, 1)
@ -121,7 +123,7 @@ class Caravel_env:
async def release_csb(self ):
cocotb.log.info(f' [caravel] release housekeeping spi transmission')
self.release_gpio(3)
self.release_gpio(2)
self.release_gpio(4)
await ClockCycles(self.clk, 1)
"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""
@ -369,6 +371,9 @@ class Caravel_env:
self.path = self.dut.mprj_io_tb
data_bit = BinaryValue(value = data , n_bits = 8,bigEndian=False)
for i in range(7,-1,-1):
# for j in range(4):
# await FallingEdge(self.clk)
# await Timer(7, units='ns')
await FallingEdge(self.clk)
#common.drive_hdl(self.path,[(4,4),(2,2)],[0,int(data_bit[i])]) # 2 = SDI 4 = SCK
self.drive_gpio_in((2,2),int(data_bit[i]))

5
verilog/dv/cocotb/interfaces/cpu.py
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@ -33,10 +33,11 @@ class RiskV:
if not Macros['GL']:
self.cpu_hdl = dut.uut.soc.core.VexRiscv
else:
self.cpu_hdl = dut.uut.soc.core
self.cpu_hdl = dut.uut.soc
self.debug_hdl = dut.uut.mprj.debug
self.force_reset = 0
cocotb.scheduler.add(self.force_reset_fun())
if not Macros['GL']:
cocotb.scheduler.add(self.force_reset_fun())
""" """

3
verilog/dv/cocotb/sdf_includes.v Normal file
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@ -0,0 +1,3 @@
initial begin
$sdf_annotate({`MAIN_PATH,"/../../../signoff/caravel/primetime-signoff/sdf/",`CORNER,"/caravel.", `SDF_POSTFIX,".sdf"}, uut,,{`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},"MINIMUM");
end

36
verilog/dv/cocotb/tests.json
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@ -33,24 +33,42 @@
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input using automatic approach firmware and check them"}
,"gpio_all_i_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user input using automatic approach firmware and check them"}
,"gpio_all_i_pu" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"}
,"gpio_all_i_pu_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user input pull up using automatic approach firmware and check them"}
,"gpio_all_i_pd" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"}
,"gpio_all_bidir" :{"level":0,
,"gpio_all_i_pd_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt bidir using automatic approach firmware and check them"}
"description":"configure all gpios as user input pull down using automatic approach firmware and check them"}
,"gpio_all_bidir_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user bidir using automatic approach firmware and check them"}
,"bitbang_cpu_all_10" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
@ -110,8 +128,8 @@
,"hk_regs_wr_wb" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL":[],
"GL_SDF":[],
"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
,"hk_regs_wr_spi" :{"level":0,
"SW":false,
@ -138,12 +156,18 @@
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"stress the cpu with heavy processing"}
,"mem_stress" :{"level":2,
,"mem_dff2" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"Memory stress tests write and read from 800 bytes 200 words and 400 half words"}
"description":"Memory stress for all space of dff2"}
,"mem_dff" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"Memory stress for all space of dff"}
,"IRQ_external" :{"level":2,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],

2
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_0011.c
View File

@ -49,7 +49,7 @@ void main(){
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
for(int i =0;i<62;i++){
clock00();
clock00();
clock11();

2
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_01.c
View File

@ -49,7 +49,7 @@ void main(){
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
for(int i =0;i<124;i++){
clock00();
clock11();
}

2
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_10.c
View File

@ -49,7 +49,7 @@ void main(){
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
for(int i =0;i<124;i++){
clock11();
clock00();
}

2
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_1100.c
View File

@ -49,7 +49,7 @@ void main(){
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
for(int i =0;i<62;i++){
clock11();
clock11();
clock00();

176
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c
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@ -3,96 +3,96 @@
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
// Configure all as output except reg_mprj_io_3
clock_in_right_o_left_o_standard(0); // 18 and 19
clock_in_right_o_left_o_standard(0); // 17 and 20
clock_in_right_o_left_o_standard(0); // 16 and 21
clock_in_right_o_left_o_standard(0); // 15 and 22
clock_in_right_o_left_o_standard(0); // 14 and 23
clock_in_right_o_left_o_standard(0); // 13 and 24
clock_in_right_o_left_o_standard(0); // 12 and 25
clock_in_right_o_left_o_standard(0); // 11 and 26
clock_in_right_o_left_o_standard(0); // 10 and 27
clock_in_right_o_left_o_standard(0); // 9 and 28
clock_in_right_o_left_o_standard(0); // 8 and 29
clock_in_right_o_left_o_standard(0); // 7 and 30
clock_in_right_o_left_o_standard(0); // 6 and 31
clock_in_right_o_left_o_standard(0); // 5 and 32
clock_in_right_o_left_o_standard(0); // 4 and 33
clock_in_right_o_left_i_standard(0); // 3 and 34
clock_in_right_o_left_o_standard(0); // 2 and 35
clock_in_right_o_left_o_standard(0); // 1 and 36
clock_in_right_o_left_o_standard(0); // 0 and 37
load();
reg_debug_1 = 0xFF; // finish configuration
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
// bitbang
// Configure all as output except reg_mprj_io_3
clock_in_right_o_left_o_standard(0); // 18 and 19
clock_in_right_o_left_o_standard(0); // 17 and 20
clock_in_right_o_left_o_standard(0); // 16 and 21
clock_in_right_o_left_o_standard(0); // 15 and 22
clock_in_right_o_left_o_standard(0); // 14 and 23
clock_in_right_o_left_o_standard(0); // 13 and 24
clock_in_right_o_left_o_standard(0); // 12 and 25
clock_in_right_o_left_o_standard(0); // 11 and 26
clock_in_right_o_left_o_standard(0); // 10 and 27
clock_in_right_o_left_o_standard(0); // 9 and 28
clock_in_right_o_left_o_standard(0); // 8 and 29
clock_in_right_o_left_o_standard(0); // 7 and 30
clock_in_right_o_left_o_standard(0); // 6 and 31
clock_in_right_o_left_o_standard(0); // 5 and 32
clock_in_right_o_left_o_standard(0); // 4 and 33
clock_in_right_o_left_o_standard(0); // 3 and 34
clock_in_right_o_left_o_standard(0); // 2 and 35
clock_in_right_o_left_o_standard(0); // 1 and 36
clock_in_right_o_left_o_standard(0); // 0 and 37
load();
reg_debug_1 = 0xFF; // finish configuration
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
}

4
verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c
View File

@ -9,7 +9,7 @@ void main()
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
@ -50,7 +50,7 @@ void main()
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_debug_1 = 0xFF; // finish configuration
while (reg_debug_2 != 0xDD);
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal

13
verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c
View File

@ -9,7 +9,7 @@ void main()
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
@ -43,14 +43,15 @@ void main()
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = 0x1803;
reg_mprj_io_3 = 0x1803;
reg_mprj_io_2 = 0x1803;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// reg_mprj_io_4 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
// reg_mprj_io_3 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
// reg_mprj_io_2 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
// reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
// reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_debug_1 = 0xFF; // finish configuration
while (reg_debug_2 != 0xFF); // finish bit bang
reg_hkspi_disable = 1;
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;

2
verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
View File

@ -234,7 +234,7 @@ async def bitbang_no_cpu_all_i(dut):
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI."""
@cocotb.test()
@repot_test
async def io_ports(dut):

31
verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
View File

@ -21,30 +21,31 @@ async def bitbang_cpu_all_o(dut):
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xFF)
await caravelEnv.release_csb()
cocotb.log.info("[TEST] finish configuring using bitbang")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,0)).integer != i<<32:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
if caravelEnv.monitor_gpio((31,0)).integer != i :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
@ -113,7 +114,7 @@ async def bitbang_cpu_all_01(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_0011(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
caravelEnv,clock = await test_configure(dut,timeout_cycles=5963970)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -134,7 +135,7 @@ async def bitbang_cpu_all_0011(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_1100(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
caravelEnv,clock = await test_configure(dut,timeout_cycles=5962067)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -224,7 +225,7 @@ async def bitbang_cpu_all_i(dut):
@cocotb.test()
@repot_test
async def bitbang_spi_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=639757)
caravelEnv,clock = await test_configure(dut,timeout_cycles=2639757)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -289,7 +290,7 @@ async def bitbang_spi_o(dut):
@cocotb.test()
@repot_test
async def bitbang_spi_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=56703)
caravelEnv,clock = await test_configure(dut,timeout_cycles=11156703)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -316,7 +317,7 @@ async def bitbang_spi_i(dut):
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37
await load_spi(caravelEnv) # load
cpu.write_debug_reg2_backdoor(0xDD)
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B

2
verilog/dv/cocotb/tests/common_functions/test_functions.py
View File

@ -57,7 +57,7 @@ def repot_test(func):
cocotb.log.error = CallCounted(cocotb.log.error)
cocotb.log.critical = CallCounted(cocotb.log.critical)
cocotb.log.warning = CallCounted(cocotb.log.warning)
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('SIM')}-{TestName}/{TestName}.log",mode='w')
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('TESTFULLNAME')}/{TestName}.log",mode='w')
handler.addFilter(SimTimeContextFilter())
handler.setFormatter(SimLogFormatter())
cocotb.log.addHandler(handler)

109
verilog/dv/cocotb/tests/gpio/gpio.py
View File

@ -15,12 +15,13 @@ reg = Regs()
@cocotb.test()
@repot_test
async def gpio_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
caravelEnv,clock = await test_configure(dut,timeout_cycles=586652)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xAA)
await caravelEnv.release_csb()
cocotb.log.info("[TEST] finish configuring ")
i= 0x20
for j in range(5):
@ -51,7 +52,7 @@ async def gpio_all_o(dut):
await wait_reg1(cpu,caravelEnv,0XBB)
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]")
cocotb.log.info(f"[TEST] try drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
reg2 =0
await wait_reg1(cpu,caravelEnv,0XFF)
@ -73,47 +74,82 @@ async def gpio_all_o(dut):
@cocotb.test()
@repot_test
async def gpio_all_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=44980)
caravelEnv,clock = await test_configure(dut,timeout_cycles=56837)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
data_in = 0xFFFFFFFF
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xFFA88C5A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xAAAAAAAA
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xC9536346
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x55555555
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xDD)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x0
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x3F
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x0
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x15
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x2A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg2(cpu,caravelEnv,0xFF)
await wait_reg1(cpu,caravelEnv,0XD5)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
caravelEnv.release_gpio((37,0))
await wait_reg2(cpu,caravelEnv,0XFF)
if caravelEnv.monitor_gpio((37,0)).binstr != "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz":
cocotb.log.error(f"[TEST] ERROR: firmware can write to the gpios while they are configured as input_nopull gpio= {caravelEnv.monitor_gpio((37,0))}")
else:
cocotb.log.info(f"[TEST] [TEST] PASS: firmware cannot write to the gpios while they are configured as input_nopull gpio= {caravelEnv.monitor_gpio((37,0))}")
cocotb.log.info(f"[TEST] finish")
@ -121,13 +157,13 @@ async def gpio_all_i(dut):
@repot_test
async def gpio_all_i_pu(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
await caravelEnv.release_csb()
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
await caravelEnv.release_csb()
# monitor the output of padframe module it suppose to be all ones when no input is applied
await ClockCycles(caravelEnv.clk,100)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
@ -223,13 +259,13 @@ async def gpio_all_i_pu(dut):
@repot_test
async def gpio_all_i_pd(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
await caravelEnv.release_csb()
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
await caravelEnv.release_csb()
# monitor the output of padframe module it suppose to be all ones when no input is applied
await ClockCycles(caravelEnv.clk,100)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
@ -330,6 +366,7 @@ async def gpio_all_bidir(dut):
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0x1A)
await caravelEnv.release_csb()
cocotb.log.info("[TEST] finish configuring ")
i= 0x20
for j in range(5):
@ -361,59 +398,59 @@ async def gpio_all_bidir(dut):
await wait_reg1(cpu,caravelEnv,0x2A)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xFFA88C5A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x3F
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x0
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x15
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x2A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg2(cpu,caravelEnv,0xFF)
cocotb.log.info(f"[TEST] finish")

115
verilog/dv/cocotb/tests/gpio/gpio_all_bidir_user.c Normal file
View File

@ -0,0 +1,115 @@
#include <defs.h>
#include <stub.c>
#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
#define reg_oeb_userl (*(volatile uint32_t*)0x300FFFEC)
#define reg_oeb_userh (*(volatile uint32_t*)0x300FFFE8)
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_oeb_userl = 0x0;
reg_oeb_userh = 0x0;
reg_debug_1 = 0x1A; // try the gpios as output
reg_mprj_userl = 0x0;
reg_mprj_userh = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_userh = i;
reg_debug_2 = 37-j;
reg_mprj_userh = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_userh = 0x3f;
reg_mprj_userl = i;
reg_debug_2 = 32-j;
reg_mprj_userh = 0x00;
reg_mprj_userl = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
reg_oeb_userl = 0xFFFFFFFF;
reg_oeb_userh = 0x3F;
reg_mprj_userl =0;
reg_mprj_userh =0;
// test input
reg_debug_1 = 0XAA; // configuration done wait environment to send 0xFFFFFFFF to reg_mprj_userl
while (reg_mprj_userl != 0xFFFFFFFF);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xAAAAAAAA to reg_mprj_userl
while (reg_mprj_userl != 0xAAAAAAAA);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XCC; // configuration done wait environment to send 0x55555555 to reg_mprj_userl
while (reg_mprj_userl != 0x55555555);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XDD; // configuration done wait environment to send 0x0 to reg_mprj_userl
while (reg_mprj_userl != 0x0);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XD1;
while (reg_mprj_userh != 0x3F);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD2;
while (reg_mprj_userh != 0x0);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD3;
while (reg_mprj_userh != 0x15);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD4;
while (reg_mprj_userh != 0x2A);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD5;
reg_debug_2=0xFF;
}

29
verilog/dv/cocotb/tests/gpio/gpio_all_i.c
View File

@ -7,7 +7,7 @@ void main(){
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
@ -51,20 +51,35 @@ void main(){
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
while (reg_mprj_datal != 0xFFA88C5A);
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
while (reg_mprj_datal != 0xC9536346);
reg_debug_1 = 0XAA; // configuration done wait environment to send 0xFFFFFFFF to reg_mprj_datal
while (reg_mprj_datal != 0xFFFFFFFF);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xAAAAAAAA to reg_mprj_datal
while (reg_mprj_datal != 0xAAAAAAAA);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XCC; // configuration done wait environment to send 0x55555555 to reg_mprj_datal
while (reg_mprj_datal != 0x55555555);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XDD; // configuration done wait environment to send 0x0 to reg_mprj_datal
while (reg_mprj_datal != 0x0);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XD1;
while (reg_mprj_datah != 0x3F);
reg_debug_2 = reg_mprj_datah;
reg_debug_1 = 0XD2;
while (reg_mprj_datah != 0x0);
reg_debug_2 = reg_mprj_datah;
reg_debug_1 = 0XD3;
while (reg_mprj_datah != 0x15);
reg_debug_2 = reg_mprj_datah;
reg_debug_1 = 0XD4;
while (reg_mprj_datah != 0x2A);
reg_debug_2 = reg_mprj_datah;
reg_debug_1 = 0XD5;
reg_debug_1 = 0XD5; // for delay insertion for release
// trying to inject error by sending data to gpio by firmware where gpios configured as input
reg_mprj_datal = 0x5AE1FFB8; // random number
reg_mprj_datah = 0x1E; // random number
reg_debug_2 = 0xFF;
}

1
verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c
View File

@ -53,5 +53,6 @@ void main(){
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

58
verilog/dv/cocotb/tests/gpio/gpio_all_i_pd_user.c Normal file
View File

@ -0,0 +1,58 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

2
verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c
View File

@ -52,6 +52,6 @@ void main(){
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

64
verilog/dv/cocotb/tests/gpio/gpio_all_i_pu_user.c Normal file
View File

@ -0,0 +1,64 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
#define reg_oeb_userl (*(volatile uint32_t*)0x300FFFEC)
#define reg_oeb_userh (*(volatile uint32_t*)0x300FFFE8)
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLUP;
reg_mprj_userl = 0xFFFFFFFF;
reg_mprj_userh = 0x3F;
reg_oeb_userl = 0x0;
reg_oeb_userh = 0x0;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

88
verilog/dv/cocotb/tests/gpio/gpio_all_i_user.c Normal file
View File

@ -0,0 +1,88 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done wait environment to send 0xFFFFFFFF to reg_mprj_userl
while (reg_mprj_userl != 0xFFFFFFFF);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xAAAAAAAA to reg_mprj_userl
while (reg_mprj_userl != 0xAAAAAAAA);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XCC; // configuration done wait environment to send 0x55555555 to reg_mprj_userl
while (reg_mprj_userl != 0x55555555);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XDD; // configuration done wait environment to send 0x0 to reg_mprj_userl
while (reg_mprj_userl != 0x0);
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XD1;
while (reg_mprj_userh != 0x3F);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD2;
while (reg_mprj_userh != 0x0);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD3;
while (reg_mprj_userh != 0x15);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD4;
while (reg_mprj_userh != 0x2A);
reg_debug_2 = reg_mprj_userh;
reg_debug_1 = 0XD5;
reg_debug_1 = 0XD5; // for delay insertion for release
// trying to inject error by sending data to gpio by firmware where gpios configured as input
reg_mprj_userl = 0x5AE1FFB8; // random number
reg_mprj_userh = 0x1E; // random number
reg_debug_2 = 0xFF;
}

2
verilog/dv/cocotb/tests/gpio/gpio_all_o.c
View File

@ -77,7 +77,7 @@ void main(){
// try to give input
reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
int timeout = 1000;
int timeout = 100;
while (reg_mprj_datal != 0x8F66FD7B){
timeout--;
if (timeout==0){

8
verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c
View File

@ -4,7 +4,8 @@
// Debug reg DEBUG_ON
#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
#define reg_oeb_userl (*(volatile uint32_t*)0x300FFFEC)
#define reg_oeb_userh (*(volatile uint32_t*)0x300FFFE8)
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
@ -53,7 +54,8 @@ void main(){
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_oeb_userl = 0x0;
reg_oeb_userh = 0x0;
reg_debug_1 = 0xAA; // finish configuration
reg_mprj_userl = 0x0;
reg_mprj_userh = 0x0;
@ -80,7 +82,7 @@ void main(){
// try to give input
reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_userl
int timeout = 1000;
int timeout = 100;
while (reg_mprj_userl != 0x8F66FD7B){
timeout--;
if (timeout==0){

401
verilog/dv/cocotb/tests/gpio/gpio_user.py
View File

@ -15,12 +15,13 @@ reg = Regs()
@cocotb.test()
@repot_test
async def gpio_all_o_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
caravelEnv,clock = await test_configure(dut,timeout_cycles=542674)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xAA)
await caravelEnv.release_csb()
cocotb.log.info("[TEST] finish configuring as user output")
i= 0x20
for j in range(5):
@ -67,3 +68,401 @@ async def gpio_all_o_user(dut):
await ClockCycles(caravelEnv.clk, 10)
@cocotb.test()
@repot_test
async def gpio_all_i_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=56694)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0xFFFFFFFF
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xAAAAAAAA
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x55555555
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xDD)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x0
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x3F
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x0
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x15
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x2A
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0XD5)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
caravelEnv.release_gpio((37,0))
await wait_reg2(cpu,caravelEnv,0XFF)
if caravelEnv.monitor_gpio((37,0)).binstr != "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz":
cocotb.log.error(f"[TEST] ERROR: firmware can write to the gpios while they are configured as input_nopull gpio= {caravelEnv.monitor_gpio((37,0))}")
else:
cocotb.log.info(f"[TEST] [TEST] PASS: firmware cannot write to the gpios while they are configured as input_nopull gpio= {caravelEnv.monitor_gpio((37,0))}")
cocotb.log.info(f"[TEST] finish")
@cocotb.test()
@repot_test
async def gpio_all_i_pu_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
await caravelEnv.release_csb()
# monitor the output of padframe module it suppose to be all ones when no input is applied
await ClockCycles(caravelEnv.clk,100)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and float")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with zero
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with ones
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with zeros and float other half
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==1: #odd
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 0")
else:
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with odd half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==1: #odd
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with even half with 0")
else:
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with ones and float other half
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive with zeros then release all gpio
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
caravelEnv.release_gpio((37,0))
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and all released")
await ClockCycles(caravelEnv.clk,1000)
@cocotb.test()
@repot_test
async def gpio_all_i_pd_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
await caravelEnv.release_csb()
# monitor the output of padframe module it suppose to be all ones when no input is applied
await ClockCycles(caravelEnv.clk,100)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and float")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with zero
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with ones
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with zeros and float other half
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i]!="0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i]!="0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with even half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with ones and float other half
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==0: #even
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1")
else:
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==1: #odd
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1")
else:
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive with ones then release all gpio
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
caravelEnv.release_gpio((37,0))
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released")
await ClockCycles(caravelEnv.clk,1000)
@cocotb.test()
@repot_test
async def gpio_all_bidir_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=290455)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0x1A)
await caravelEnv.release_csb()
cocotb.log.info("[TEST] finish configuring ")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,0)).integer != i << 32:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i << 32)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,0)).integer != i :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
caravelEnv.release_gpio((37,0))
await ClockCycles(caravelEnv.clk, 10)
caravelEnv.drive_gpio_in((31,0),0)
await ClockCycles(caravelEnv.clk, 10)
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0xFFFFFFFF
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xAAAAAAAA
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x55555555
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xDD)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x0
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x3F
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x0
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x15
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0x2A
cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0XD5)
await wait_reg2(cpu,caravelEnv,0XFF)
cocotb.log.info(f"[TEST] finish")
await ClockCycles(caravelEnv.clk, 10)

2
verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c
View File

@ -14,5 +14,7 @@ void main(){
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 =0xAA;
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

3
verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c
View File

@ -9,6 +9,7 @@ void main(){
while (reg_debug_1 != 0xAA);
reg_hkspi_disable = 0;
// reg_hkspi_pll_ena =0;
reg_hkspi_pll_ena =0;
reg_debug_1 =0xBB;
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

9
verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py
View File

@ -23,6 +23,7 @@ async def clock_redirect(dut):
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
error_margin = 0.1
# calculate core clock
await cocotb.start(calculate_clk_period(dut.uut.clock,"core clock"))
await ClockCycles(caravelEnv.clk,110)
@ -41,8 +42,8 @@ async def clock_redirect(dut):
await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
await ClockCycles(caravelEnv.clk,110)
if user_clock != core_clock:
await ClockCycles(caravelEnv.clk,110)
if abs(user_clock - core_clock) > (error_margin*core_clock):
cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}")
else:
cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
@ -60,7 +61,7 @@ async def clock_redirect(dut):
await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect
await cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name))
await ClockCycles(caravelEnv.clk,110)
if caravel_clock != core_clock:
if abs(caravel_clock - core_clock) > error_margin*core_clock:
cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}")
else:
cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
@ -91,7 +92,7 @@ async def calculate_clk_period(clk,name):
@cocotb.test()
@repot_test
async def hk_disable(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=11243)
caravelEnv,clock = await test_configure(dut,timeout_cycles=12409)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

1
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c
View File

@ -5,6 +5,7 @@
void main()
{
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

1
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c
View File

@ -5,6 +5,7 @@
void main()
{
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

1
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c
View File

@ -5,6 +5,7 @@
void main()
{
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

4
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
View File

@ -110,10 +110,10 @@ async def hk_regs_wr_spi(dut):
if key == 'base_addr':
continue
address = regs[mem][key][0][7]
if address in [111,36]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled
if address in [111,36,10]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled and 10 0xa cpu irq is self resetting
continue
# address = int(key,16)
if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
if address in [0x69,0x6A,0x6B,0x6C,0x6D]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
continue
data_in = random.getrandbits(bits_num)
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")

6
verilog/dv/cocotb/tests/irq/IRQ_external.py
View File

@ -28,11 +28,7 @@ async def IRQ_external(dut):
phases_passes = 0
reg1 =0 # buffer
reg2 = 0 #buffer
await ClockCycles(caravelEnv.clk,10)
await write_reg_spi(caravelEnv,0x1c,1)
await ClockCycles(caravelEnv.clk,10)
cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}")
while True:
if reg2 != cpu.read_debug_reg2():
@ -40,6 +36,8 @@ async def IRQ_external(dut):
if reg2 == 0xFF: # test finish
break
if reg2 == 0xAA: # assert mprj 7
await write_reg_spi(caravelEnv,0x1c,1)
cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}")
caravelEnv.drive_gpio_in((7,7),0)
await ClockCycles(caravelEnv.clk,10)
caravelEnv.drive_gpio_in((7,7),1)

1
verilog/dv/cocotb/tests/logicAnalyzer/la.c
View File

@ -108,4 +108,5 @@ void main(){
reg_debug_2 = 0xFF;
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

36
verilog/dv/cocotb/tests/mem/mem_dff.c Normal file
View File

@ -0,0 +1,36 @@
#include <defs.h>
#define BYTE_SIZE 800
#define SHORT_SIZE BYTE_SIZE/2
#define INT_SIZE BYTE_SIZE/4
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
unsigned int *dff_start_address = (unsigned int *) 0x00000000;
unsigned int dff_size = 0x400/4;
for (unsigned int i = 0; i < dff_size; i++){
unsigned int data = (i + 7)*13;
*(dff_start_address+i) = data;
}
bool is_fail = false;
for (unsigned int i = 0; i < dff_size; i++){
unsigned int data = (i + 7)*13;
if (data != *(dff_start_address+i)){
reg_debug_2 = i;
reg_debug_1 = 0x1E;
is_fail = true;
break;
}
}
if (!is_fail)
reg_debug_1 = 0x1B;
// test finish
reg_debug_1 = 0xFF;
}

36
verilog/dv/cocotb/tests/mem/mem_dff2.c Normal file
View File

@ -0,0 +1,36 @@
#include <defs.h>
#define BYTE_SIZE 800
#define SHORT_SIZE BYTE_SIZE/2
#define INT_SIZE BYTE_SIZE/4
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
unsigned int *dff2_start_address = (unsigned int *) 0x00000400;
unsigned int dff2_size = 0x200 / 4;
for (unsigned int i = 0; i < dff2_size; i++){
unsigned int data = (i + 7)*13;
*(dff2_start_address+i) = data;
}
bool is_fail = false;
for (unsigned int i = 0; i < dff2_size; i++){
unsigned int data = (i + 7)*13;
if (data != *(dff2_start_address+i)){
reg_debug_2 = i;
reg_debug_1 = 0x1E;
is_fail = true;
break;
}
}
if (!is_fail)
reg_debug_1 = 0x1B;
// test finish
reg_debug_1 = 0xFF;
}

102
verilog/dv/cocotb/tests/mem/mem_stress.c
View File

@ -1,102 +0,0 @@
#include <defs.h>
/*
@ start of test
send packet with size = 1
@ pass bytes
send packet with size = 2
@ pass int
send packet with size = 3
@ pass short
send packet with size = 4
@ error reading
send packet with size = 9
@ test finish
send packet with size = 7
send packet with size = 7
send packet with size = 7
*/
#define BYTE_SIZE 800
#define SHORT_SIZE BYTE_SIZE/2
#define INT_SIZE BYTE_SIZE/4
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
unsigned char dff_bytes[BYTE_SIZE];
unsigned short *dff_shorts=(unsigned short *) dff_bytes;
unsigned int *dff_ints=(unsigned int *) dff_bytes;
unsigned char magic = 0x79;
unsigned int magic_int = 0x79797979;
unsigned short magic_short = 0x7979;
unsigned char magic1;
unsigned int magic1_int;
unsigned short magic1_short;
int i;
magic1 = magic;
for ( i=0; i<BYTE_SIZE; i++){
dff_bytes[i] = (magic1*3+5)|magic;
magic1 += 11;
}
magic1 = magic;
bool is_fail = false;
for ( i=0; i<BYTE_SIZE; i++){
unsigned char t = (magic1*3+5)|magic;
if (t != dff_bytes[i]){
reg_debug_1 = 0x1E; // fail reading bytes expected value
is_fail = true;
break;
}
magic1 += 11;
}
if (!is_fail)
reg_debug_1 = 0x1B; // pass reading bytes expected value
is_fail = false;
// int
magic1_int = magic_int;
for ( i=0; i<INT_SIZE; i++){
dff_ints[i] = (magic1_int*3+5)|magic_int;
magic1_int += 11;
}
magic1_int = magic_int;
for ( i=0; i<INT_SIZE; i++){
unsigned int t = (magic1_int*3+5)|magic_int;
if (t != dff_ints[i]){
reg_debug_1 = 0x2E; // fail reading ints expected value
is_fail = true;
break;
}
magic1_int += 11;
}
if (!is_fail)
reg_debug_1 = 0x2B; // pass reading ints expected value
is_fail = false;
// short
magic1_short = magic_short;
for ( i=0; i<SHORT_SIZE; i++){
dff_shorts[i] = (magic1_short*3+5)|magic_short;
magic1_short += 11;
}
magic1_short = magic_short;
for ( i=0; i<SHORT_SIZE; i++){
unsigned short t = (magic1_short*3+5)|magic_short;
if (t != dff_shorts[i]){
reg_debug_1 = 0x3E; // fail reading shorts expected value
is_fail = true;
break;
}
magic1_short += 11;
}
if (!is_fail)
reg_debug_1 = 0x3B; // pass reading ints expected value
// test finish
reg_debug_2 = 0xFF;
}

54
verilog/dv/cocotb/tests/mem/mem_stress.py
View File

@ -10,42 +10,64 @@ from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def mem_stress(dut):
async def mem_dff2(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mem stress test")
pass_list = (0x1B,0x2B,0x3B)
fail_list = (0x1E,0x2E,0x3E)
phases_fails = 3
pass_list = (0x1B)
fail_list = (0x1E)
phases_fails = 1
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
if cpu.read_debug_reg1() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] pass writing and reading from {phase_to_type(hex(reg1)[2])}")
cocotb.log.info(f"[TEST] pass writing and reading all dff2 memory ")
elif reg1 in fail_list: # pass phase
cocotb.log.error(f"[TEST] failed phase {phase_to_type(hex(reg1)[2])}")
await ClockCycles(caravelEnv.clk,1)
cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
await ClockCycles(caravelEnv.clk,100)
if phases_fails > 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
def phase_to_type(phase):
if phase == "1":
return "800 Bytes"
elif phase == "2":
return "200 Words"
elif phase == "3":
return "400 Halfwords"
@cocotb.test()
@repot_test
async def mem_dff(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mem stress test")
pass_list = (0x1B)
fail_list = (0x1E)
phases_fails = 1
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg1() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] pass writing and reading all dff memory ")
elif reg1 in fail_list: # pass phase
cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
await ClockCycles(caravelEnv.clk,100)
if phases_fails > 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

389
verilog/dv/cocotb/tests/sessions/session.bitbang_spi_i.vpd.tcl/session.bitbang_spi_i.vpd.tcl Normal file
View File

@ -0,0 +1,389 @@
# Begin_DVE_Session_Save_Info
# DVE full session
# Saved on Tue Oct 11 10:47:30 2022
# Designs open: 1
# V1: bitbang_spi_i.vpd
# Toplevel windows open: 2
# TopLevel.1
# TopLevel.2
# Source.1: caravel_top
# Wave.1: 19 signals
# Group count = 4
# Group Group1 signal count = 4
# Group Group2 signal count = 6
# Group Group3 signal count = 6
# Group Group4 signal count = 3
# End_DVE_Session_Save_Info
# DVE version: T-2022.06_Full64
# DVE build date: May 31 2022 20:53:03
#<Session mode="Full" path="/home/rady/caravel/caravel_redesign_cocotb_new/caravel/verilog/dv/cocotb/session.bitbang_spi_i.vpd.tcl" type="Debug">
gui_set_loading_session_type Post
gui_continuetime_set
# Close design
if { [gui_sim_state -check active] } {
gui_sim_terminate
}
gui_close_db -all
gui_expr_clear_all
# Close all windows
gui_close_window -type Console
gui_close_window -type Wave
gui_close_window -type Source
gui_close_window -type Schematic
gui_close_window -type Data
gui_close_window -type DriverLoad
gui_close_window -type List
gui_close_window -type Memory
gui_close_window -type HSPane
gui_close_window -type DLPane
gui_close_window -type Assertion
gui_close_window -type CovHier
gui_close_window -type CoverageTable
gui_close_window -type CoverageMap
gui_close_window -type CovDetail
gui_close_window -type Local
gui_close_window -type Stack
gui_close_window -type Watch
gui_close_window -type Group
gui_close_window -type Transaction
# Application preferences
gui_set_pref_value -key app_default_font -value {Helvetica,10,-1,5,50,0,0,0,0,0}
gui_src_preferences -tabstop 8 -maxbits 24 -windownumber 1
#<WindowLayout>
# DVE top-level session
# Create and position top-level window: TopLevel.1
if {![gui_exist_window -window TopLevel.1]} {
set TopLevel.1 [ gui_create_window -type TopLevel \
-icon $::env(DVE)/auxx/gui/images/toolbars/dvewin.xpm]
} else {
set TopLevel.1 TopLevel.1
}
gui_show_window -window ${TopLevel.1} -show_state maximized -rect {{0 29} {2559 1336}}
# ToolBar settings
gui_set_toolbar_attributes -toolbar {TimeOperations} -dock_state top
gui_set_toolbar_attributes -toolbar {TimeOperations} -offset 0
gui_show_toolbar -toolbar {TimeOperations}
gui_hide_toolbar -toolbar {&File}
gui_set_toolbar_attributes -toolbar {&Edit} -dock_state top
gui_set_toolbar_attributes -toolbar {&Edit} -offset 0
gui_show_toolbar -toolbar {&Edit}
gui_hide_toolbar -toolbar {CopyPaste}
gui_set_toolbar_attributes -toolbar {&Trace} -dock_state top
gui_set_toolbar_attributes -toolbar {&Trace} -offset 0
gui_show_toolbar -toolbar {&Trace}
gui_hide_toolbar -toolbar {TraceInstance}
gui_hide_toolbar -toolbar {BackTrace}
gui_set_toolbar_attributes -toolbar {&Scope} -dock_state top
gui_set_toolbar_attributes -toolbar {&Scope} -offset 0
gui_show_toolbar -toolbar {&Scope}
gui_set_toolbar_attributes -toolbar {&Window} -dock_state top
gui_set_toolbar_attributes -toolbar {&Window} -offset 0
gui_show_toolbar -toolbar {&Window}
gui_set_toolbar_attributes -toolbar {Signal} -dock_state top
gui_set_toolbar_attributes -toolbar {Signal} -offset 0
gui_show_toolbar -toolbar {Signal}
gui_set_toolbar_attributes -toolbar {Zoom} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom} -offset 0
gui_show_toolbar -toolbar {Zoom}
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -offset 0
gui_show_toolbar -toolbar {Zoom And Pan History}
gui_set_toolbar_attributes -toolbar {Grid} -dock_state top
gui_set_toolbar_attributes -toolbar {Grid} -offset 0
gui_show_toolbar -toolbar {Grid}
gui_hide_toolbar -toolbar {Simulator}
gui_hide_toolbar -toolbar {Interactive Rewind}
gui_hide_toolbar -toolbar {Testbench}
# End ToolBar settings
# Docked window settings
set HSPane.1 [gui_create_window -type HSPane -parent ${TopLevel.1} -dock_state left -dock_on_new_line true -dock_extent 343]
catch { set Hier.1 [gui_share_window -id ${HSPane.1} -type Hier] }
gui_set_window_pref_key -window ${HSPane.1} -key dock_width -value_type integer -value 343
gui_set_window_pref_key -window ${HSPane.1} -key dock_height -value_type integer -value -1
gui_set_window_pref_key -window ${HSPane.1} -key dock_offset -value_type integer -value 0
gui_update_layout -id ${HSPane.1} {{left 0} {top 0} {width 342} {height 773} {dock_state left} {dock_on_new_line true} {child_hier_colhier 298} {child_hier_coltype 100} {child_hier_colpd 0} {child_hier_col1 0} {child_hier_col2 1} {child_hier_col3 -1}}
set DLPane.1 [gui_create_window -type DLPane -parent ${TopLevel.1} -dock_state left -dock_on_new_line true -dock_extent 354]
catch { set Data.1 [gui_share_window -id ${DLPane.1} -type Data] }
gui_set_window_pref_key -window ${DLPane.1} -key dock_width -value_type integer -value 354
gui_set_window_pref_key -window ${DLPane.1} -key dock_height -value_type integer -value 772
gui_set_window_pref_key -window ${DLPane.1} -key dock_offset -value_type integer -value 0
gui_update_layout -id ${DLPane.1} {{left 0} {top 0} {width 353} {height 773} {dock_state left} {dock_on_new_line true} {child_data_colvariable 265} {child_data_colvalue 65} {child_data_coltype 64} {child_data_col1 0} {child_data_col2 1} {child_data_col3 2}}
set Console.1 [gui_create_window -type Console -parent ${TopLevel.1} -dock_state bottom -dock_on_new_line true -dock_extent 454]
gui_set_window_pref_key -window ${Console.1} -key dock_width -value_type integer -value 2500
gui_set_window_pref_key -window ${Console.1} -key dock_height -value_type integer -value 454
gui_set_window_pref_key -window ${Console.1} -key dock_offset -value_type integer -value 0
gui_update_layout -id ${Console.1} {{left 0} {top 0} {width 2559} {height 453} {dock_state bottom} {dock_on_new_line true}}
#### Start - Readjusting docked view's offset / size
set dockAreaList { top left right bottom }
foreach dockArea $dockAreaList {
set viewList [gui_ekki_get_window_ids -active_parent -dock_area $dockArea]
foreach view $viewList {
if {[lsearch -exact [gui_get_window_pref_keys -window $view] dock_width] != -1} {
set dockWidth [gui_get_window_pref_value -window $view -key dock_width]
set dockHeight [gui_get_window_pref_value -window $view -key dock_height]
set offset [gui_get_window_pref_value -window $view -key dock_offset]
if { [string equal "top" $dockArea] || [string equal "bottom" $dockArea]} {
gui_set_window_attributes -window $view -dock_offset $offset -width $dockWidth
} else {
gui_set_window_attributes -window $view -dock_offset $offset -height $dockHeight
}
}
}
}
#### End - Readjusting docked view's offset / size
gui_sync_global -id ${TopLevel.1} -option true
# MDI window settings
set Source.1 [gui_create_window -type {Source} -parent ${TopLevel.1}]
gui_show_window -window ${Source.1} -show_state maximized
gui_update_layout -id ${Source.1} {{show_state maximized} {dock_state undocked} {dock_on_new_line false}}
# End MDI window settings
# Create and position top-level window: TopLevel.2
if {![gui_exist_window -window TopLevel.2]} {
set TopLevel.2 [ gui_create_window -type TopLevel \
-icon $::env(DVE)/auxx/gui/images/toolbars/dvewin.xpm]
} else {
set TopLevel.2 TopLevel.2
}
gui_show_window -window ${TopLevel.2} -show_state maximized -rect {{0 29} {2559 1336}}
# ToolBar settings
gui_set_toolbar_attributes -toolbar {TimeOperations} -dock_state top
gui_set_toolbar_attributes -toolbar {TimeOperations} -offset 0
gui_show_toolbar -toolbar {TimeOperations}
gui_hide_toolbar -toolbar {&File}
gui_set_toolbar_attributes -toolbar {&Edit} -dock_state top
gui_set_toolbar_attributes -toolbar {&Edit} -offset 0
gui_show_toolbar -toolbar {&Edit}
gui_hide_toolbar -toolbar {CopyPaste}
gui_set_toolbar_attributes -toolbar {&Trace} -dock_state top
gui_set_toolbar_attributes -toolbar {&Trace} -offset 0
gui_show_toolbar -toolbar {&Trace}
gui_hide_toolbar -toolbar {TraceInstance}
gui_hide_toolbar -toolbar {BackTrace}
gui_set_toolbar_attributes -toolbar {&Scope} -dock_state top
gui_set_toolbar_attributes -toolbar {&Scope} -offset 0
gui_show_toolbar -toolbar {&Scope}
gui_set_toolbar_attributes -toolbar {&Window} -dock_state top
gui_set_toolbar_attributes -toolbar {&Window} -offset 0
gui_show_toolbar -toolbar {&Window}
gui_set_toolbar_attributes -toolbar {Signal} -dock_state top
gui_set_toolbar_attributes -toolbar {Signal} -offset 0
gui_show_toolbar -toolbar {Signal}
gui_set_toolbar_attributes -toolbar {Zoom} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom} -offset 0
gui_show_toolbar -toolbar {Zoom}
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -offset 0
gui_show_toolbar -toolbar {Zoom And Pan History}
gui_set_toolbar_attributes -toolbar {Grid} -dock_state top
gui_set_toolbar_attributes -toolbar {Grid} -offset 0
gui_show_toolbar -toolbar {Grid}
gui_hide_toolbar -toolbar {Simulator}
gui_hide_toolbar -toolbar {Interactive Rewind}
gui_set_toolbar_attributes -toolbar {Testbench} -dock_state top
gui_set_toolbar_attributes -toolbar {Testbench} -offset 0
gui_show_toolbar -toolbar {Testbench}
# End ToolBar settings
# Docked window settings
gui_sync_global -id ${TopLevel.2} -option true
# MDI window settings
set Wave.1 [gui_create_window -type {Wave} -parent ${TopLevel.2}]
gui_show_window -window ${Wave.1} -show_state maximized
gui_update_layout -id ${Wave.1} {{show_state maximized} {dock_state undocked} {dock_on_new_line false} {child_wave_left 743} {child_wave_right 1811} {child_wave_colname 369} {child_wave_colvalue 369} {child_wave_col1 0} {child_wave_col2 1}}
# End MDI window settings
gui_set_env TOPLEVELS::TARGET_FRAME(Source) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(Schematic) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(PathSchematic) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(Wave) none
gui_set_env TOPLEVELS::TARGET_FRAME(List) none
gui_set_env TOPLEVELS::TARGET_FRAME(Memory) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(DriverLoad) none
gui_update_statusbar_target_frame ${TopLevel.1}
gui_update_statusbar_target_frame ${TopLevel.2}
#</WindowLayout>
#<Database>
# DVE Open design session:
if { ![gui_is_db_opened -db {bitbang_spi_i.vpd}] } {
gui_open_db -design V1 -file bitbang_spi_i.vpd -to 8464250000 -nosource
}
gui_set_precision 1ps
gui_set_time_units 1ps
#</Database>
# DVE Global setting session:
# Global: Bus
# Global: Expressions
# Global: Signal Time Shift
# Global: Signal Compare
# Global: Signal Groups
set _session_group_1 Group1
gui_sg_create "$_session_group_1"
set Group1 "$_session_group_1"
gui_sg_addsignal -group "$_session_group_1" { {caravel_top.uut.gpio_control_bidir_1[0].serial_clock} {caravel_top.uut.gpio_control_bidir_1[0].serial_load} {caravel_top.uut.gpio_control_bidir_1[0].serial_data_in} {caravel_top.uut.gpio_control_bidir_1[0].shift_register} }
set _session_group_2 Group2
gui_sg_create "$_session_group_2"
set Group2 "$_session_group_2"
gui_sg_addsignal -group "$_session_group_2" { caravel_top.uut.housekeeping.serial_bb_clock caravel_top.uut.housekeeping.serial_bb_load caravel_top.uut.housekeeping.serial_bb_resetn caravel_top.uut.housekeeping.serial_bb_data_1 caravel_top.uut.housekeeping.serial_bb_data_2 caravel_top.uut.housekeeping.serial_bb_enable }
set _session_group_3 Group3
gui_sg_create "$_session_group_3"
set Group3 "$_session_group_3"
gui_sg_addsignal -group "$_session_group_3" { caravel_top.uut.housekeeping.hkspi.SCK caravel_top.uut.housekeeping.hkspi.SDI caravel_top.uut.housekeeping.hkspi.CSB caravel_top.uut.housekeeping.cdata caravel_top.uut.housekeeping.caddr caravel_top.uut.housekeeping.hkspi.wrstb }
set _session_group_4 Group4
gui_sg_create "$_session_group_4"
set Group4 "$_session_group_4"
gui_sg_addsignal -group "$_session_group_4" { caravel_top.uut.housekeeping.hkspi.SCK caravel_top.uut.housekeeping.csclk caravel_top.uut.housekeeping.wbbd_sck }
# Global: Highlighting
# Global: Stack
gui_change_stack_mode -mode list
# Post database loading setting...
# Restore C1 time
gui_set_time -C1_only 665850000
# Save global setting...
# Wave/List view global setting
gui_cov_show_value -switch false
# Close all empty TopLevel windows
foreach __top [gui_ekki_get_window_ids -type TopLevel] {
if { [llength [gui_ekki_get_window_ids -parent $__top]] == 0} {
gui_close_window -window $__top
}
}
gui_set_loading_session_type noSession
# DVE View/pane content session:
# Hier 'Hier.1'
gui_show_window -window ${Hier.1}
gui_list_set_filter -id ${Hier.1} -list { {Package 1} {All 0} {Process 1} {VirtPowSwitch 0} {UnnamedProcess 1} {UDP 0} {Function 1} {Block 1} {SrsnAndSpaCell 0} {OVA Unit 1} {LeafScCell 1} {LeafVlgCell 1} {Interface 1} {LeafVhdCell 1} {$unit 1} {NamedBlock 1} {Task 1} {VlgPackage 1} {ClassDef 1} {VirtIsoCell 0} }
gui_list_set_filter -id ${Hier.1} -text {*house*}
gui_hier_list_init -id ${Hier.1}
gui_change_design -id ${Hier.1} -design V1
catch {gui_list_expand -id ${Hier.1} caravel_top}
catch {gui_list_expand -id ${Hier.1} caravel_top.uut}
catch {gui_list_select -id ${Hier.1} {caravel_top.uut.housekeeping}}
gui_view_scroll -id ${Hier.1} -vertical -set 0
gui_view_scroll -id ${Hier.1} -horizontal -set 0
# Data 'Data.1'
gui_list_set_filter -id ${Data.1} -list { {Buffer 1} {Input 1} {Others 1} {Linkage 1} {Output 1} {LowPower 1} {Parameter 1} {All 1} {Aggregate 1} {LibBaseMember 1} {Event 1} {Assertion 1} {Constant 1} {Interface 1} {BaseMembers 1} {Signal 1} {$unit 1} {Inout 1} {Variable 1} }
gui_list_set_filter -id ${Data.1} -text {*wbbd_sck*}
gui_list_show_data -id ${Data.1} {caravel_top.uut.housekeeping}
gui_show_window -window ${Data.1}
catch { gui_list_select -id ${Data.1} {caravel_top.uut.housekeeping.wbbd_sck }}
gui_view_scroll -id ${Data.1} -vertical -set 0
gui_view_scroll -id ${Data.1} -horizontal -set 0
gui_view_scroll -id ${Hier.1} -vertical -set 0
gui_view_scroll -id ${Hier.1} -horizontal -set 0
# Source 'Source.1'
gui_src_value_annotate -id ${Source.1} -switch false
gui_set_env TOGGLE::VALUEANNOTATE 0
gui_open_source -id ${Source.1} -replace -active caravel_top /home/rady/caravel/caravel_redesign_cocotb_new/caravel/verilog/dv/cocotb/caravel_top.sv
gui_src_value_annotate -id ${Source.1} -switch true
gui_set_env TOGGLE::VALUEANNOTATE 1
gui_view_scroll -id ${Source.1} -vertical -set 160
gui_src_set_reusable -id ${Source.1}
# View 'Wave.1'
gui_wv_sync -id ${Wave.1} -switch false
set groupExD [gui_get_pref_value -category Wave -key exclusiveSG]
gui_set_pref_value -category Wave -key exclusiveSG -value {false}
set origWaveHeight [gui_get_pref_value -category Wave -key waveRowHeight]
gui_list_set_height -id Wave -height 25
set origGroupCreationState [gui_list_create_group_when_add -wave]
gui_list_create_group_when_add -wave -disable
gui_marker_create -id ${Wave.1} C2 620210463
gui_marker_select -id ${Wave.1} { C2 }
gui_marker_set_ref -id ${Wave.1} C1
gui_wv_zoom_timerange -id ${Wave.1} 665193119 667348726
gui_list_add_group -id ${Wave.1} -after {New Group} {Group1}
gui_list_add_group -id ${Wave.1} -after {New Group} {Group2}
gui_list_add_group -id ${Wave.1} -after {New Group} {Group3}
gui_list_add_group -id ${Wave.1} -after {New Group} {Group4}
gui_list_select -id ${Wave.1} {caravel_top.uut.housekeeping.csclk }
gui_seek_criteria -id ${Wave.1} {Rising}
gui_set_env TOGGLE::DEFAULT_WAVE_WINDOW ${Wave.1}
gui_set_pref_value -category Wave -key exclusiveSG -value $groupExD
gui_list_set_height -id Wave -height $origWaveHeight
if {$origGroupCreationState} {
gui_list_create_group_when_add -wave -enable
}
if { $groupExD } {
gui_msg_report -code DVWW028
}
gui_list_set_filter -id ${Wave.1} -list { {Buffer 1} {Input 1} {Others 1} {Linkage 1} {Output 1} {Parameter 1} {All 1} {Aggregate 1} {LibBaseMember 1} {Event 1} {Assertion 1} {Constant 1} {Interface 1} {BaseMembers 1} {Signal 1} {$unit 1} {Inout 1} {Variable 1} }
gui_list_set_filter -id ${Wave.1} -text {*}
gui_list_set_insertion_bar -id ${Wave.1} -group Group4 -item caravel_top.uut.housekeeping.wbbd_sck -position below
gui_marker_move -id ${Wave.1} {C1} 665850000
gui_view_scroll -id ${Wave.1} -vertical -set 0
gui_show_grid -id ${Wave.1} -enable false
# Restore toplevel window zorder
# The toplevel window could be closed if it has no view/pane
if {[gui_exist_window -window ${TopLevel.1}]} {
gui_set_active_window -window ${TopLevel.1}
gui_set_active_window -window ${Source.1}
gui_set_active_window -window ${DLPane.1}
}
if {[gui_exist_window -window ${TopLevel.2}]} {
gui_set_active_window -window ${TopLevel.2}
gui_set_active_window -window ${Wave.1}
}
#</Session>

4
verilog/dv/cocotb/tests/spi_master/spi_master.py
View File

@ -80,12 +80,14 @@ async def spi_master_temp(dut):
# second val
for i in range(8):
b = b + dut.bin35_monitor.value.binstr
await RisingEdge(dut.bin32_monitor)
if i != 7: # skip last cycle wait
await RisingEdge(dut.bin32_monitor)
cocotb.log.info (f" [TEST] b = {b} = {int(b,2)}")
s = int(a,2) + int(b,2)
s_bin = bin(s)[2:].zfill(8)
cocotb.log.info (f" [TEST] sending sum of {int(a,2)} + {int(b,2)} = {s} = {s_bin}")
await FallingEdge(dut.bin32_monitor)
for i in range(8):
dut.bin34_en.value = 1
dut.bin34.value = int(s_bin[i],2) # bin

2
verilog/dv/cocotb/tests/spi_master/spi_master_rd.c
View File

@ -17,6 +17,7 @@
#include <defs.h>
#include <csr.h>
#include <stub.c>
// --------------------------------------------------------
@ -176,5 +177,6 @@ void main()
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

2
verilog/dv/cocotb/tests/spi_master/spi_master_temp.c
View File

@ -17,6 +17,7 @@
#include <defs.h>
#include <csr.h>
#include <stub.c>
// --------------------------------------------------------
@ -107,5 +108,6 @@ void main()
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

13
verilog/dv/cocotb/tests/uart/uart.py
View File

@ -9,6 +9,7 @@ from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from interfaces.common import Macros
bit_time_ns = 0
@ -112,7 +113,11 @@ async def uart_send_char(caravelEnv,char):
async def uart_check_char_recieved(caravelEnv,cpu):
# check cpu recieved the correct character
while True:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
if not Macros['GL']:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
else:
reg_uart_data = "1001110"
reg1 = cpu.read_debug_reg1()
cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
if reg1 == 0x1B:
@ -149,7 +154,11 @@ async def connect_5_6(dut,caravelEnv):
async def uart_check_char_recieved_loopback(caravelEnv,cpu):
# check cpu recieved the correct character
while True:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
if not Macros['GL']:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
else:
reg_uart_data = "1001110"
reg1 = cpu.read_debug_reg1()
cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
if reg1 == 0x1B:

145
verilog/dv/cocotb/verify_cocotb.py
View File

@ -10,6 +10,7 @@ from fnmatch import fnmatch
from datetime import datetime
import random
from pathlib import Path
import shutil
iverilog = True
@ -30,12 +31,27 @@ def search_str(file_path, word):
else:
return "failed"
def change_dff(str,new_str,file_path):
# Read in the file
with open(file_path, 'r') as file :
filedata = file.read()
if new_str == "> dff2":
if new_str in filedata: # to avoid type dff22 types
return
# Replace the target string
filedata = filedata.replace(str, new_str)
# Write the file out again
with open(file_path, 'w') as file:
file.write(filedata)
class RunTest:
def __init__(self,test_name,sim) -> None:
def __init__(self,test_name,sim,corner) -> None:
self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
self.test_name = test_name
self.sim_type = sim
self.corner = corner
self.create_log_file()
self.hex_generate()
self.runTest()
@ -45,6 +61,8 @@ class RunTest:
self.cd_cocotb()
os.chdir(f"sim/{os.getenv('RUNTAG')}")
test_dir = f"{self.sim_type}-{self.test_name}"
if (self.sim_type == "GL_SDF"):
test_dir = f'{test_dir}-{self.corner}'
os.makedirs(f"{test_dir}",exist_ok=True)
self.cd_cocotb()
self.sim_path = f"sim/{os.getenv('RUNTAG')}/{test_dir}/"
@ -75,7 +93,7 @@ class RunTest:
os.system(f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
# vcs function
def runTest_vcs(self):
print(f"Start running test: {self.sim_type}-{self.test_name}")
@ -87,18 +105,22 @@ class RunTest:
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" '
else:
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" '
full_test_name = f"{self.sim_type}-{self.test_name}"
macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
if self.test_name == "la":
macros = f'{macros} +define+LA_TESTING'
if self.test_name == "gpio_all_o_user":
if self.test_name in ["gpio_all_o_user","gpio_all_i_user","gpio_all_i_pu_user","gpio_all_i_pd_user","gpio_all_bidir_user"]:
macros = f'{macros} +define+GPIO_TESTING'
# shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
# if os.path.exists(f'{self.test_full_dir}/test_data'):
# shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data')
if (self.sim_type=="GL_SDF"):
macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"-{self.corner}\\\"'
macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"{self.corner[-1]}{self.corner[-1]}\\\" +define+CORNER=\\\"{self.corner[0:3]}\\\"'
# corner example is corner nom-t so `SDF_POSTFIX = tt and `CORNER = nom
os.makedirs(f"annotation_logs",exist_ok=True)
dirs = f"{dirs} +incdir+\\\"{os.getenv('MCW_ROOT')}/verilog/\\\" "
# +incdir+\\\"{os.getenv('CARAVEL_ROOT')}/signoff/caravel/primetime-signoff/\\\"
full_test_name = f"{self.sim_type}-{self.test_name}-{self.corner}"
elif(self.sim_type=="GL"):
macros = f'{macros} +define+GL +define+SIM=GL'
elif (self.sim_type=="RTL"):
@ -111,12 +133,16 @@ class RunTest:
os.environ["TESTCASE"] = f"{self.test_name}"
os.environ["MODULE"] = f"caravel_tests"
os.environ["SIM"] = self.sim_type
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vcs {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
os.environ["TESTFULLNAME"] = f"{full_test_name}"
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{full_test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")
if os.path.exists(f"{self.cocotb_path}/sdfAnnotateInfo"):
shutil.move(f"{self.cocotb_path}/sdfAnnotateInfo", f"{self.sim_path}/sdfAnnotateInfo")
shutil.copyfile(f'{self.cocotb_path}/hex_files/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
def find(self,name, path):
for root, dirs, files in os.walk(path):
@ -133,6 +159,7 @@ class RunTest:
return (test_path)
def hex_generate(self):
tests_use_dff2 = ["mem_dff"]
#open docker
test_path =self.test_path()
self.cd_make()
@ -154,6 +181,9 @@ class RunTest:
f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
#change linker script to dff2
if self.test_name in tests_use_dff2:
change_dff(str="> dff",new_str="> dff2",file_path=LINKER_SCRIPT)
hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
@ -163,6 +193,8 @@ class RunTest:
if hex_gen_state != 0 :
print(f"fatal: Error when generating hex")
sys.exit()
if self.test_name in tests_use_dff2:
change_dff(str="> dff2",new_str="> dff",file_path=LINKER_SCRIPT)
def cd_make(self):
os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")
@ -171,11 +203,12 @@ class RunTest:
os.chdir(self.cocotb_path)
class RunRegression:
def __init__(self,regression,test,type_arg,testlist) -> None:
def __init__(self,regression,test,type_arg,testlist,corner) -> None:
self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
self.regression_arg = regression
self.test_arg = test
self.testlist_arg = testlist
self.corners = corner
if type_arg is None:
type_arg = "RTL"
self.type_arg = type_arg
@ -187,7 +220,7 @@ class RunRegression:
self.run_regression()
def get_tests(self):
self.tests = collections.defaultdict(lambda : collections.defaultdict(dict)) #key is testname and value is list of sim types
self.tests = collections.defaultdict(lambda : collections.defaultdict(lambda : collections.defaultdict(dict))) #key is testname and value is list of sim types
self.unknown_tests = 0
self.passed_tests = 0
self.failed_tests = 0
@ -198,8 +231,13 @@ class RunRegression:
if fnmatch(test,"_*"):
continue
for sim_type in sim_types:
if self.regression_arg in test_elements[sim_type]:
self.add_new_test(test_name=test,sim_type = sim_type)
if sim_type =="GL_SDF":
for corner in self.corners:
if self.regression_arg in test_elements[sim_type]:
self.add_new_test(test_name=test,sim_type = sim_type,corner = corner)
else:
if self.regression_arg in test_elements[sim_type]:
self.add_new_test(test_name=test,sim_type = sim_type,corner = "-")
if (len(self.tests)==0):
print(f"fatal:{self.regression_arg} is not a valid regression name please input a valid regression \ncheck tests.json for more info")
sys.exit()
@ -210,9 +248,15 @@ class RunRegression:
if test in self.tests_json:
if isinstance(self.type_arg,list):
for sim_type in self.type_arg:
self.add_new_test(test_name=test,sim_type = sim_type)
if sim_type =="GL_SDF":
for corner in self.corners:
self.add_new_test(test_name=test,sim_type = sim_type, corner = corner)
else: self.add_new_test(test_name=test,sim_type = sim_type,corner = "-")
else:
self.add_new_test(test_name=test,sim_type = self.type_arg)
if sim_type =="GL_SDF":
for corner in self.corners:
self.add_new_test(test_name=test,sim_type = sim_type, corner = corner)
else: self.add_new_test(test_name=test,sim_type = sim_type,corner = "-")
else:
if self.test_arg in self.tests_json:
@ -229,35 +273,37 @@ class RunRegression:
self.update_reg_log()
def add_new_test(self,test_name,sim_type):
self.tests[test_name][sim_type]["status"]= "pending"
self.tests[test_name][sim_type]["starttime"]= "-"
self.tests[test_name][sim_type]["endtime"]= "-"
self.tests[test_name][sim_type]["duration"] = "-"
self.tests[test_name][sim_type]["pass"]= "-"
def add_new_test(self,test_name,sim_type,corner):
self.tests[test_name][sim_type][corner]["status"]= "pending"
self.tests[test_name][sim_type][corner]["starttime"]= "-"
self.tests[test_name][sim_type][corner]["endtime"]= "-"
self.tests[test_name][sim_type][corner]["duration"] = "-"
self.tests[test_name][sim_type][corner]["pass"]= "-"
self.unknown_tests +=1
def run_regression(self):
for test,sim_types in self.tests.items():
for sim_type,status in sim_types.items(): # TODO: add multithreading or multiprocessing here
start_time = datetime.now()
self.tests[test][sim_type]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
self.tests[test][sim_type]["duration"] = "-"
self.tests[test][sim_type]["status"] = "running"
self.update_reg_log()
test_run = RunTest(test,sim_type)
self.tests[test][sim_type]["status"] = "done"
self.tests[test][sim_type]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
self.tests[test][sim_type]["duration"] = ("%.10s" % (datetime.now() - start_time))
self.tests[test][sim_type]["pass"]= test_run.passed
if test_run.passed == "passed":
self.passed_tests +=1
elif test_run.passed == "failed":
self.failed_tests +=1
self.unknown_tests -=1
self.update_reg_log()
if coverage:
self.generate_cov()
for sim_type,corners in sim_types.items(): # TODO: add multithreading or multiprocessing here
for corner,status in corners.items(): # TODO: add multithreading or multiprocessing here
start_time = datetime.now()
self.tests[test][sim_type][corner]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
self.tests[test][sim_type][corner]["duration"] = "-"
self.tests[test][sim_type][corner]["status"] = "running"
self.update_reg_log()
test_run = RunTest(test,sim_type,corner)
self.tests[test][sim_type][corner]["status"] = "done"
self.tests[test][sim_type][corner]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
self.tests[test][sim_type][corner]["duration"] = ("%.10s" % (datetime.now() - start_time))
self.tests[test][sim_type][corner]["pass"]= test_run.passed
if test_run.passed == "passed":
self.passed_tests +=1
elif test_run.passed == "failed":
self.failed_tests +=1
self.unknown_tests -=1
self.update_reg_log()
if coverage:
self.generate_cov()
#TODO: add send mail here
def generate_cov(self):
@ -272,9 +318,10 @@ class RunRegression:
f = open(file_name, "w")
f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
for test,sim_types in self.tests.items():
for sim_type,status in sim_types.items():
new_test_name= f"{sim_type}-{test}"
f.write(f"{new_test_name:<25} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
for sim_type,corners in sim_types.items():
for corner,status in corners.items():
new_test_name= f"{sim_type}-{test}-{corner}"
f.write(f"{new_test_name:<33} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ")
f.close()
@ -289,20 +336,21 @@ class main():
self.regression = args.regression
self.test = args.test
self.testlist = args.testlist
self.type = args.sim
self.sim = args.sim
self.tag = args.tag
self.corner = args.corner
self.maxerr = args.maxerr
self.check_valid_args()
self.set_tag()
self.def_env_vars()
RunRegression(self.regression,self.test,self.type,self.testlist)
RunRegression(self.regression,self.test,self.sim,self.testlist,self.corner)
def check_valid_args(self):
if all(v is None for v in [self.regression, self.test, self.testlist]):
print ("Fatal: Should provide at least one of the following options regression, test or testlist for more info use --help")
sys.exit()
if not set(self.type).issubset(["RTL","GL","GL_SDF"]):
print (f"Fatal: {self.type} isnt a correct type for -sim it should be one or combination of the following RTL, GL or GL_SDF")
if not set(self.sim).issubset(["RTL","GL","GL_SDF"]):
print (f"Fatal: {self.sim} isnt a correct type for -sim it should be one or combination of the following RTL, GL or GL_SDF")
sys.exit()
def set_tag(self):
self.TAG = None # tag will be set in the main phase and other functions will use it
@ -338,7 +386,8 @@ parser.add_argument('-testlist','-tl', help='path of testlist to be run ')
parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run_<random float>_<timestamp>_')
parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3')
parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used')
parser.add_argument('-cov','-c',action='store_true', help='enable code coverage')
parser.add_argument('-cov',action='store_true', help='enable code coverage')
parser.add_argument('-corner','-c', nargs='+' ,help='Corner type in case of GL_SDF run has to be provided')
args = parser.parse_args()
if (args.vcs) :
iverilog = False
@ -347,6 +396,8 @@ if args.cov:
coverage = True
if args.sim == None:
args.sim= ["RTL"]
if args.corner == None:
args.corner= ["nom-t"]
print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}")
main(args)

10
verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json
View File

@ -1,7 +1,7 @@
{
"_comment": "the list contain the fields in register with shift spcified [field name,name iniside housekeeping, shift, size,mode,reset,value(intial is reset value), SPI address map] the shift is from the base address like SPI, system and gpio base address",
"_comment2": "Base address is the first element and called first address",
"_not_used_currently":["0x34",[["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]], "0x30",[["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]],
"SPI":{ "base_addr": ["SPI_BASE_ADR",638582784],
"0x00": [["SPI status",null,0,8,"undefined",0,0,0]],
@ -22,9 +22,7 @@
"0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]],
"0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]],
"0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]],
"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]],
"0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]],
"0x30": [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]
"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]]
},
"GPIO":{ "base_addr": ["GPIO_BASE_ADR",637534208],
@ -44,8 +42,8 @@
"0x29": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",12,8],0,5,"RW",24,24,31]],
"0x2c": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",7,0],0,8,"RW",3,3,34]],
"0x2d": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",12,8],0,5,"RW",4,4,33]],
"0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",3,3,36]],
"0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",4,4,35]],
"0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",1,1,36]],
"0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",8,8,35]],
"0x34": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",7,0],0,8,"RW",3,3,38]],
"0x35": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",12,8],0,5,"RW",4,4,37]],
"0x38": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",7,0],0,8,"RW",3,3,40]],

34
verilog/rtl/__user_project_gpio_example.v
View File

@ -45,26 +45,40 @@ module user_project_gpio_example (
);
reg [31:0] io_l;
reg [5:0] io_h;
reg [31:0] oeb_l;
reg [5:0] oeb_h;
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i) begin
io_l <=0;
io_h <=0;
oeb_l <=0;
oeb_h <=0;
wbs_dat_o <=0;
wbs_ack_o <=0;
end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0))begin // write
end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[31:0]==32'h300FFFF4||wbs_adr_i[31:0]==32'h300FFFF0||wbs_adr_i[31:0]==32'h300FFFEC||wbs_adr_i[31:0]==32'h300FFFE8))begin // write
// write to io_l
io_l[7:0] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0];
io_l[15:8] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8];
io_l[23:16] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16];
io_l[31:24] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24];
io_l[7:0] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0];
io_l[15:8] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8];
io_l[23:16] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16];
io_l[31:24] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24];
// io_h
io_h[5:0] <= ((wbs_adr_i[3:0]==4'h4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0];
io_h[5:0] <= ((wbs_adr_i[31:0]==32'h300FFFF4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0];
// oeb_l
oeb_l[7:0] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[0])? wbs_dat_i[7:0] :oeb_l[7:0];
oeb_l[15:8] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[1])? wbs_dat_i[15:8] :oeb_l[15:8];
oeb_l[23:16] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[2])? wbs_dat_i[23:16] :oeb_l[23:16];
oeb_l[31:24] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[3])? wbs_dat_i[31:24] :oeb_l[31:24];
// oeb_h
oeb_h[7:0] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[0])? wbs_dat_i[7:0] :oeb_h[7:0];
oeb_h[15:8] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[1])? wbs_dat_i[15:8] :oeb_h[15:8];
oeb_h[23:16] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[2])? wbs_dat_i[23:16] :oeb_h[23:16];
oeb_h[31:24] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[3])? wbs_dat_i[31:24] :oeb_h[31:24];
wbs_ack_o <= 1;
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0)) begin // read
wbs_dat_o <= (wbs_adr_i[3:0]==4'h0)? io_in[31:0] : io_in[`MPRJ_IO_PADS-1:32];
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[31:0]==32'h300FFFF4||wbs_adr_i[31:0]==32'h300FFFF0||wbs_adr_i[31:0]==32'h300FFFEC||wbs_adr_i[31:0]==32'h300FFFE8)) begin // read
wbs_dat_o <= (wbs_adr_i[31:0]==32'h300FFFF0)? io_in[31:0] :(wbs_adr_i[31:0]==32'h300FFFF4)? io_in[`MPRJ_IO_PADS-1:32] : (wbs_adr_i[31:0]==32'h300FFFEC) ? io_oeb[31:0]: io_oeb[37:32];
wbs_ack_o <= 1;
end else begin
wbs_ack_o <= 0;
@ -73,7 +87,7 @@ module user_project_gpio_example (
end
assign io_out = {io_h,io_l};
assign io_oeb = 38'h0;
assign io_oeb = {oeb_h,oeb_l};
endmodule

38
verilog/rtl/__user_project_wrapper.v
View File

@ -108,42 +108,44 @@ wire [31:0] wbs_dat_o_gpio;
wire [31:0] wbs_dat_o_debug;
// reserve the last 2 regs for debugging registers
`ifndef GPIO_TESTING
// `ifndef GPIO_TESTING
assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0;
assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0;
`endif
// `endif
// `ifndef GPIO_TESTING
assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_user;
assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user;
// `endif
`ifndef GPIO_TESTING
assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_debug;
assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user;
assign wbs_ack_o_user = 0;
`endif
// // reserve the last 4 regs for debugging registers in case of user gpio testing
// `ifdef GPIO_TESTING
// assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0;
// assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0;
// `endif
// reserve the last 4 regs for debugging registers in case of user gpio testing
`ifdef GPIO_TESTING
assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0;
assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0;
`endif
`ifdef GPIO_TESTING
assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug;
assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user;
`endif
// `ifdef GPIO_TESTING
// assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug;
// assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user;
// `endif
`ifdef GPIO_TESTING
user_project_gpio_example gpio_testing(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_cyc_i(wbs_cyc_i_debug),
.wbs_cyc_i(wbs_cyc_i_user),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o_gpio),
.wbs_dat_o(wbs_dat_o_gpio),
.wbs_ack_o(wbs_ack_o_user),
.wbs_dat_o(wbs_dat_o_user),
.io_in(io_in),
.io_out(io_out),
.io_oeb(io_oeb));