mirror of https://github.com/efabless/caravel.git
update caravel/caravan signoff sdc with:
- add input transition range from `1ns` to `4ns` using `-min` and `-max` - add cap load range from `5pF` to `10pF` using `-min` and `-max` - add clock uncertainity `0.1` - remove power pads transition constraints - add maximum transition `1.5ns` constraint on HD cells at the ss corner
This commit is contained in:
Passant
parent
7facc3a6d7
commit
2b27894190
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@ -1,6 +1,6 @@
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### Caravan Signoff SDC
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### Rev 1
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### Date: 22/10/2022
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### Rev 2
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### Date: 28/10/2022
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## MASTER CLOCKS
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create_clock -name clk -period 25 [get_ports {clock}]
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@ -10,6 +10,8 @@ create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock
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create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
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# hk_serial_clk period is x2 core clock
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set_clock_uncertainty 0.1000 [get_clocks {clk hkspi_clk hk_serial_clk hk_serial_load}]
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set_clock_groups \
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-name clock_group \
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-logically_exclusive \
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@ -91,20 +93,15 @@ set_max_fanout 12 [current_design]
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set_case_analysis 0 [get_pins housekeeping/_3936_/S]
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set_case_analysis 0 [get_pins housekeeping/_3937_/S]
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# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0
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# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
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set_case_analysis 1 [get_pins padframe/*_pad/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_pad/DM[1]]
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set_case_analysis 0 [get_pins padframe/*_pad/DM[0]]
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set_case_analysis 0 [get_pins padframe/*_pad/SLOW]
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set_case_analysis 0 [get_pins padframe/*_pad/ANALOG_EN]
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set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[1]]
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set_case_analysis 0 [get_pins padframe/*_io_pad*/DM[0]]
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set_case_analysis 0 [get_pins padframe/*_io_pad*/SLOW]
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set_case_analysis 0 [get_pins padframe/*_io_pad*/ANALOG_EN]
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set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
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set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
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set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
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set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
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# the following pads are set as inputs
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set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
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set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
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set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
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@ -121,6 +118,11 @@ set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
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## FALSE PATHS (ASYNCHRONOUS INPUTS)
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set_false_path -from [get_ports {resetb}]
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# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
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# reset_path -from [get_ports mprj_io[4]]
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# reset_path -from [get_ports mprj_io[2]]
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#reset_path is not supported in PT read_sdc ^
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set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
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set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
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set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
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@ -160,18 +162,45 @@ set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgm
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set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
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set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
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# reset_path -from [get_ports mprj_io[4]]
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# reset_path -from [get_ports mprj_io[2]]
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set_false_path -from [get_ports gpio]
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#set_false_path -through [get_nets mprj_io_inp_dis[*]]
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# set_timing_derate -early 1
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# set_timing_derate -late 1
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set cap_load 10
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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# add loads for output ports (pads)
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set min_cap 5
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set max_cap 10
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puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
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# set_load 10 [all_outputs]
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set_load -min $min_cap [all_outputs]
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set_load -max $max_cap [all_outputs]
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#add input transition for the inputs pins
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set_input_transition 2 [all_inputs]
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#add input transition for the inputs ports (pads)
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# set_input_transition 2 [all_inputs]
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#add exception for power pads as 2ns on them results in max_tran violations (false viol)
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# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]]
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# remove_from_collection is not supported in PT read_sdc ^
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# set_input_transition 2 [all_inputs]
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# set_input_transition 0 [get_ports v*]
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set min_in_tran 1
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set max_in_tran 4
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puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
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set_input_transition -min $min_in_tran [all_inputs]
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set_input_transition -min 0 [get_ports v*]
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set_input_transition -max $max_in_tran [all_inputs]
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set_input_transition -max 0 [get_ports v*]
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# check ocv table (not provided) -- maybe try 8%
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set derate 0.0375
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puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
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set_timing_derate -early [expr 1-$derate]
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set_timing_derate -late [expr 1+$derate]
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# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
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# apply the constraint to hd cells at the ss corner only
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# if {$::env(PROC_CORNER) == "s"} {
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# set max_tran 1.5
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# set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
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# set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
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# set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
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# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
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# }
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# -filter not supported in PT read_sdc ^
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@ -1,6 +1,6 @@
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### Caravel Signoff SDC
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### Rev 2
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### Date: 14/10/2022
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### Rev 3
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### Date: 28/10/2022
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## MASTER CLOCKS
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create_clock -name clk -period 25 [get_ports {clock}]
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@ -10,6 +10,8 @@ create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock
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create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
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# hk_serial_clk period is x2 core clock
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set_clock_uncertainty 0.1000 [get_clocks {clk hkspi_clk hk_serial_clk hk_serial_load}]
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set_clock_groups \
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-name clock_group \
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-logically_exclusive \
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@ -91,20 +93,15 @@ set_max_fanout 12 [current_design]
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set_case_analysis 0 [get_pins housekeeping/_3936_/S]
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set_case_analysis 0 [get_pins housekeeping/_3937_/S]
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# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0
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# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
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set_case_analysis 1 [get_pins padframe/*_pad/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_pad/DM[1]]
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set_case_analysis 0 [get_pins padframe/*_pad/DM[0]]
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set_case_analysis 0 [get_pins padframe/*_pad/SLOW]
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set_case_analysis 0 [get_pins padframe/*_pad/ANALOG_EN]
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set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[1]]
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set_case_analysis 0 [get_pins padframe/*_io_pad*/DM[0]]
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set_case_analysis 0 [get_pins padframe/*_io_pad*/SLOW]
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set_case_analysis 0 [get_pins padframe/*_io_pad*/ANALOG_EN]
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set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
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set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
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set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
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set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
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# the following pads are set as inputs
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set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
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set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
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set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
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@ -121,6 +118,11 @@ set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
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## FALSE PATHS (ASYNCHRONOUS INPUTS)
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set_false_path -from [get_ports {resetb}]
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# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
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# reset_path -from [get_ports mprj_io[4]]
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# reset_path -from [get_ports mprj_io[2]]
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#reset_path is not supported in PT read_sdc ^
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set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
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set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
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set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
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@ -160,19 +162,45 @@ set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgm
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set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
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set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
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# reset_path -from [get_ports mprj_io[4]]
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# reset_path -from [get_ports mprj_io[2]]
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set_false_path -from [get_ports gpio]
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#set_false_path -through [get_nets mprj_io_inp_dis[*]]
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# set_timing_derate -early 1
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# set_timing_derate -late 1
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# TODO set this as parameter
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set cap_load 10
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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# add loads for output ports (pads)
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set min_cap 5
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set max_cap 10
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puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
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# set_load 10 [all_outputs]
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set_load -min $min_cap [all_outputs]
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set_load -max $max_cap [all_outputs]
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#add input transition for the inputs pins
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set_input_transition 2 [all_inputs]
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#add input transition for the inputs ports (pads)
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# set_input_transition 2 [all_inputs]
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#add exception for power pads as 2ns on them results in max_tran violations (false viol)
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# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]]
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# remove_from_collection is not supported in PT read_sdc ^
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# set_input_transition 2 [all_inputs]
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# set_input_transition 0 [get_ports v*]
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set min_in_tran 1
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set max_in_tran 4
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puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
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set_input_transition -min $min_in_tran [all_inputs]
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set_input_transition -min 0 [get_ports v*]
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set_input_transition -max $max_in_tran [all_inputs]
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set_input_transition -max 0 [get_ports v*]
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# check ocv table (not provided) -- maybe try 8%
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set derate 0.0375
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puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
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set_timing_derate -early [expr 1-$derate]
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set_timing_derate -late [expr 1+$derate]
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# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
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# apply the constraint to hd cells at the ss corner only
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# if {$::env(PROC_CORNER) == "s"} {
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# set max_tran 1.5
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# set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
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# set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
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# set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
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# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
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# }
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# -filter not supported in PT read_sdc ^
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